Blame view
drivers/timer/altera_timer.c
2.35 KB
a54915d8a
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 |
/* * (C) Copyright 2000-2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004, Psyent Corporation <www.psyent.com> * Scott McNutt <smcnutt@psyent.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <dm.h> #include <errno.h> #include <timer.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; |
1235e5a56
|
18 19 20 21 |
/* control register */ #define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */ #define ALTERA_TIMER_START BIT(2) /* Start timer */ #define ALTERA_TIMER_STOP BIT(3) /* Stop timer */ |
a54915d8a
|
22 23 24 25 26 27 28 29 30 31 32 |
struct altera_timer_regs { u32 status; /* Timer status reg */ u32 control; /* Timer control reg */ u32 periodl; /* Timeout period low */ u32 periodh; /* Timeout period high */ u32 snapl; /* Snapshot low */ u32 snaph; /* Snapshot high */ }; struct altera_timer_platdata { struct altera_timer_regs *regs; |
a54915d8a
|
33 |
}; |
9ca07ebba
|
34 |
static int altera_timer_get_count(struct udevice *dev, u64 *count) |
a54915d8a
|
35 36 37 38 39 40 41 42 43 44 45 |
{ struct altera_timer_platdata *plat = dev->platdata; struct altera_timer_regs *const regs = plat->regs; u32 val; /* Trigger update */ writel(0x0, ®s->snapl); /* Read timer value */ val = readl(®s->snapl) & 0xffff; val |= (readl(®s->snaph) & 0xffff) << 16; |
9ca07ebba
|
46 |
*count = timer_conv_64(~val); |
a54915d8a
|
47 48 49 50 51 52 |
return 0; } static int altera_timer_probe(struct udevice *dev) { |
a54915d8a
|
53 54 |
struct altera_timer_platdata *plat = dev->platdata; struct altera_timer_regs *const regs = plat->regs; |
a54915d8a
|
55 56 57 58 59 60 61 62 63 64 65 66 67 68 |
writel(0, ®s->status); writel(0, ®s->control); writel(ALTERA_TIMER_STOP, ®s->control); writel(0xffff, ®s->periodl); writel(0xffff, ®s->periodh); writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, ®s->control); return 0; } static int altera_timer_ofdata_to_platdata(struct udevice *dev) { struct altera_timer_platdata *plat = dev_get_platdata(dev); |
a821c4af7
|
69 |
plat->regs = map_physmem(devfdt_get_addr(dev), |
4c26ec17c
|
70 71 |
sizeof(struct altera_timer_regs), MAP_NOCACHE); |
a54915d8a
|
72 73 74 75 76 77 78 79 80 |
return 0; } static const struct timer_ops altera_timer_ops = { .get_count = altera_timer_get_count, }; static const struct udevice_id altera_timer_ids[] = { |
1235e5a56
|
81 82 |
{ .compatible = "altr,timer-1.0" }, {} |
a54915d8a
|
83 84 85 86 87 88 89 90 91 92 93 94 |
}; U_BOOT_DRIVER(altera_timer) = { .name = "altera_timer", .id = UCLASS_TIMER, .of_match = altera_timer_ids, .ofdata_to_platdata = altera_timer_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata), .probe = altera_timer_probe, .ops = &altera_timer_ops, .flags = DM_FLAG_PRE_RELOC, }; |