Blame view
include/usb/ehci-ci.h
9.72 KB
83d290c56 SPDX: Convert all... |
1 |
/* SPDX-License-Identifier: GPL-2.0+ */ |
6b92487dc USB ehci freescal... |
2 |
/* |
4ef01010a mpc83xx: USB: Reo... |
3 |
* Copyright (c) 2005, 2009 Freescale Semiconductor, Inc |
6b92487dc USB ehci freescal... |
4 5 |
* Copyright (c) 2005 MontaVista Software * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB |
6b92487dc USB ehci freescal... |
6 |
*/ |
e162c6b1a usb: Rename ehci-... |
7 8 |
#ifndef _EHCI_CI_H #define _EHCI_CI_H |
6b92487dc USB ehci freescal... |
9 |
|
4ef01010a mpc83xx: USB: Reo... |
10 |
#include <asm/processor.h> |
15231f6dd drivers/usb : Def... |
11 |
#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ |
6b92487dc USB ehci freescal... |
12 13 14 15 16 17 18 19 20 21 22 |
/* Global offsets */ #define FSL_SKIP_PCI 0x100 /* offsets for the non-ehci registers in the FSL SOC USB controller */ #define FSL_SOC_USB_ULPIVP 0x170 #define FSL_SOC_USB_PORTSC1 0x184 #define PORT_PTS_MSK (3 << 30) #define PORT_PTS_UTMI (0 << 30) #define PORT_PTS_ULPI (2 << 30) #define PORT_PTS_SERIAL (3 << 30) #define PORT_PTS_PTW (1 << 28) |
29c6fbe04 MPC5121: Add USB ... |
23 24 25 26 |
#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */ #define PORT_PTS_PHCD (1 << 23) #define PORT_PP (1 << 12) #define PORT_PR (1 << 8) |
6b92487dc USB ehci freescal... |
27 28 29 30 31 32 |
/* USBMODE Register bits */ #define CM_IDLE (0 << 0) #define CM_RESERVED (1 << 0) #define CM_DEVICE (2 << 0) #define CM_HOST (3 << 0) |
29c6fbe04 MPC5121: Add USB ... |
33 |
#define ES_BE (1 << 2) /* Big Endian Select, default is LE */ |
6b92487dc USB ehci freescal... |
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 |
#define USBMODE_RESERVED_2 (0 << 2) #define SLOM (1 << 3) #define SDIS (1 << 4) /* CONTROL Register bits */ #define ULPI_INT_EN (1 << 0) #define WU_INT_EN (1 << 1) #define USB_EN (1 << 2) #define LSF_EN (1 << 3) #define KEEP_OTG_ON (1 << 4) #define OTG_PORT (1 << 5) #define REFSEL_12MHZ (0 << 6) #define REFSEL_16MHZ (1 << 6) #define REFSEL_48MHZ (2 << 6) #define PLL_RESET (1 << 8) #define UTMI_PHY_EN (1 << 9) #define PHY_CLK_SEL_UTMI (0 << 10) #define PHY_CLK_SEL_ULPI (1 << 10) #define CLKIN_SEL_USB_CLK (0 << 11) #define CLKIN_SEL_USB_CLK2 (1 << 11) #define CLKIN_SEL_SYS_CLK (2 << 11) #define CLKIN_SEL_SYS_CLK2 (3 << 11) #define RESERVED_18 (0 << 13) #define RESERVED_17 (0 << 14) #define RESERVED_16 (0 << 15) #define WU_INT (1 << 16) #define PHY_CLK_VALID (1 << 17) #define FSL_SOC_USB_PORTSC2 0x188 |
29c6fbe04 MPC5121: Add USB ... |
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 |
/* OTG Status Control Register bits */ #define FSL_SOC_USB_OTGSC 0x1a4 #define CTRL_VBUS_DISCHARGE (0x1<<0) #define CTRL_VBUS_CHARGE (0x1<<1) #define CTRL_OTG_TERMINATION (0x1<<3) #define CTRL_DATA_PULSING (0x1<<4) #define CTRL_ID_PULL_EN (0x1<<5) #define HA_DATA_PULSE (0x1<<6) #define HA_BA (0x1<<7) #define STS_USB_ID (0x1<<8) #define STS_A_VBUS_VALID (0x1<<9) #define STS_A_SESSION_VALID (0x1<<10) #define STS_B_SESSION_VALID (0x1<<11) #define STS_B_SESSION_END (0x1<<12) #define STS_1MS_TOGGLE (0x1<<13) #define STS_DATA_PULSING (0x1<<14) #define INTSTS_USB_ID (0x1<<16) #define INTSTS_A_VBUS_VALID (0x1<<17) #define INTSTS_A_SESSION_VALID (0x1<<18) #define INTSTS_B_SESSION_VALID (0x1<<19) #define INTSTS_B_SESSION_END (0x1<<20) #define INTSTS_1MS (0x1<<21) #define INTSTS_DATA_PULSING (0x1<<22) #define INTR_USB_ID_EN (0x1<<24) #define INTR_A_VBUS_VALID_EN (0x1<<25) #define INTR_A_SESSION_VALID_EN (0x1<<26) #define INTR_B_SESSION_VALID_EN (0x1<<27) #define INTR_B_SESSION_END_EN (0x1<<28) #define INTR_1MS_TIMER_EN (0x1<<29) #define INTR_DATA_PULSING_EN (0x1<<30) #define INTSTS_MASK (0x00ff0000) |
29c6fbe04 MPC5121: Add USB ... |
95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 |
#define INTERRUPT_ENABLE_BITS_MASK \ (INTR_USB_ID_EN | \ INTR_1MS_TIMER_EN | \ INTR_A_VBUS_VALID_EN | \ INTR_A_SESSION_VALID_EN | \ INTR_B_SESSION_VALID_EN | \ INTR_B_SESSION_END_EN | \ INTR_DATA_PULSING_EN) #define INTERRUPT_STATUS_BITS_MASK \ (INTSTS_USB_ID | \ INTR_1MS_TIMER_EN | \ INTSTS_A_VBUS_VALID | \ INTSTS_A_SESSION_VALID | \ INTSTS_B_SESSION_VALID | \ INTSTS_B_SESSION_END | \ INTSTS_DATA_PULSING) |
6b92487dc USB ehci freescal... |
112 |
#define FSL_SOC_USB_USBMODE 0x1a8 |
29c6fbe04 MPC5121: Add USB ... |
113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 |
#define USBGENCTRL 0x200 /* NOTE: big endian */ #define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ #define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ #define GC_PPP (1 << 3) /* Port Power Polarity */ #define GC_PFP (1 << 2) /* Power Fault Polarity */ #define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ #define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ #define ISIPHYCTRL 0x204 /* NOTE: big endian */ #define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ #define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ #define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ #define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ #define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ |
6b92487dc USB ehci freescal... |
128 129 130 131 132 133 134 135 136 137 138 139 140 |
#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ #define SNOOP_SIZE_2GB 0x1e /* System Clock Control Register */ #define MPC83XX_SCCR_USB_MASK 0x00f00000 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 |
fff6ec382 Fix building for ... |
141 |
#if defined(CONFIG_MPC83xx) |
77354e9d5 powerpc/usb:Diffe... |
142 143 144 145 146 147 |
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR #if defined(CONFIG_MPC834x) #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR #else #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif |
a07bf180e mpc85xx: USB: Add... |
148 |
#elif defined(CONFIG_MPC85xx) |
77354e9d5 powerpc/usb:Diffe... |
149 150 |
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR |
88486d042 armv7: ls1021a: F... |
151 |
#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) |
9729dc956 include: usb: Ren... |
152 |
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR |
3f041f011 drivers: usb: fsl... |
153 |
#define CONFIG_SYS_FSL_USB2_ADDR 0 |
4ef01010a mpc83xx: USB: Reo... |
154 155 156 |
#endif /* |
896720ceb fsl/usb: Increase... |
157 158 159 160 161 162 163 |
* Increasing TX FIFO threshold value from 2 to 4 decreases * data burst rate with which data packets are posted from the TX * latency FIFO to compensate for latencies in DDR pipeline during DMA */ #define TXFIFOTHRESH 4 /* |
4ef01010a mpc83xx: USB: Reo... |
164 165 166 |
* USB Registers */ struct usb_ehci { |
29c6fbe04 MPC5121: Add USB ... |
167 168 169 170 171 172 173 174 175 176 177 178 |
u32 id; /* 0x000 - Identification register */ u32 hwgeneral; /* 0x004 - General hardware parameters */ u32 hwhost; /* 0x008 - Host hardware parameters */ u32 hwdevice; /* 0x00C - Device hardware parameters */ u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */ u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */ u8 res1[0x68]; u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */ u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */ u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ u32 sbuscfg; /* 0x090 - System Bus Interface Control */ |
d424efb2c usb: ehci-ci: Add... |
179 180 181 182 183 |
u32 sbusstatus; /* 0x094 - System Bus Interface Status */ u32 sbusmode; /* 0x098 - System Bus Interface Mode */ u32 genconfig; /* 0x09C - USB Core Configuration */ u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */ u8 res2[0x5c]; |
0255f2d87 ehci-fsl: correct... |
184 185 |
u8 caplength; /* 0x100 - Capability Register Length */ u8 res3[0x1]; |
4ef01010a mpc83xx: USB: Reo... |
186 187 188 |
u16 hciversion; /* 0x102 - Host Interface Version */ u32 hcsparams; /* 0x104 - Host Structural Parameters */ u32 hccparams; /* 0x108 - Host Capability Parameters */ |
0255f2d87 ehci-fsl: correct... |
189 |
u8 res4[0x14]; |
4ef01010a mpc83xx: USB: Reo... |
190 191 |
u32 dciversion; /* 0x120 - Device Interface Version */ u32 dciparams; /* 0x124 - Device Controller Params */ |
0255f2d87 ehci-fsl: correct... |
192 |
u8 res5[0x18]; |
4ef01010a mpc83xx: USB: Reo... |
193 194 195 196 |
u32 usbcmd; /* 0x140 - USB Command */ u32 usbsts; /* 0x144 - USB Status */ u32 usbintr; /* 0x148 - USB Interrupt Enable */ u32 frindex; /* 0x14C - USB Frame Index */ |
0255f2d87 ehci-fsl: correct... |
197 |
u8 res6[0x4]; |
4ef01010a mpc83xx: USB: Reo... |
198 199 200 |
u32 perlistbase; /* 0x154 - Periodic List Base - USB Device Address */ u32 ep_list_addr; /* 0x158 - Next Asynchronous List |
29c6fbe04 MPC5121: Add USB ... |
201 |
- End Point Address */ |
0255f2d87 ehci-fsl: correct... |
202 |
u8 res7[0x4]; |
4ef01010a mpc83xx: USB: Reo... |
203 |
u32 burstsize; /* 0x160 - Programmable Burst Size */ |
29c6fbe04 MPC5121: Add USB ... |
204 205 |
#define FSL_EHCI_TXPBURST(X) ((X) << 8) #define FSL_EHCI_RXPBURST(X) (X) |
4ef01010a mpc83xx: USB: Reo... |
206 207 |
u32 txfilltuning; /* 0x164 - Host TT Transmit pre-buffer packet tuning */ |
0255f2d87 ehci-fsl: correct... |
208 |
u8 res8[0x8]; |
4ef01010a mpc83xx: USB: Reo... |
209 |
u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ |
0255f2d87 ehci-fsl: correct... |
210 |
u8 res9[0xc]; |
4ef01010a mpc83xx: USB: Reo... |
211 212 |
u32 config_flag; /* 0x180 - Configured Flag Register */ u32 portsc; /* 0x184 - Port status/control */ |
0255f2d87 ehci-fsl: correct... |
213 |
u8 res10[0x1C]; |
29c6fbe04 MPC5121: Add USB ... |
214 |
u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */ |
4ef01010a mpc83xx: USB: Reo... |
215 |
u32 usbmode; /* 0x1a8 - USB Device Mode */ |
29c6fbe04 MPC5121: Add USB ... |
216 217 218 219 220 221 222 223 224 225 226 |
u32 epsetupstat; /* 0x1ac - End Point Setup Status */ u32 epprime; /* 0x1b0 - End Point Init Status */ u32 epflush; /* 0x1b4 - End Point De-initlialize */ u32 epstatus; /* 0x1b8 - End Point Status */ u32 epcomplete; /* 0x1bc - End Point Complete */ u32 epctrl0; /* 0x1c0 - End Point Control 0 */ u32 epctrl1; /* 0x1c4 - End Point Control 1 */ u32 epctrl2; /* 0x1c8 - End Point Control 2 */ u32 epctrl3; /* 0x1cc - End Point Control 3 */ u32 epctrl4; /* 0x1d0 - End Point Control 4 */ u32 epctrl5; /* 0x1d4 - End Point Control 5 */ |
0255f2d87 ehci-fsl: correct... |
227 |
u8 res11[0x28]; |
29c6fbe04 MPC5121: Add USB ... |
228 229 |
u32 usbgenctrl; /* 0x200 - USB General Control */ u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */ |
0255f2d87 ehci-fsl: correct... |
230 |
u8 res12[0x1F8]; |
4ef01010a mpc83xx: USB: Reo... |
231 232 233 234 235 |
u32 snoop1; /* 0x400 - Snoop 1 */ u32 snoop2; /* 0x404 - Snoop 2 */ u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ u32 prictrl; /* 0x40c - Priority Control */ u32 sictrl; /* 0x410 - System Interface Control */ |
0255f2d87 ehci-fsl: correct... |
236 |
u8 res13[0xEC]; |
4ef01010a mpc83xx: USB: Reo... |
237 |
u32 control; /* 0x500 - Control */ |
0255f2d87 ehci-fsl: correct... |
238 |
u8 res14[0xafc]; |
4ef01010a mpc83xx: USB: Reo... |
239 |
}; |
1ca562025 USB: MX5: add gen... |
240 241 242 |
/* * For MXC SOCs */ |
8eeb19be7 mx31: Move EHCI d... |
243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 |
/* values for portsc field */ #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) #define MXC_EHCI_FORCE_FS (1 << 24) #define MXC_EHCI_UTMI_8BIT (0 << 28) #define MXC_EHCI_UTMI_16BIT (1 << 28) #define MXC_EHCI_SERIAL (1 << 29) #define MXC_EHCI_MODE_UTMI (0 << 30) #define MXC_EHCI_MODE_PHILIPS (1 << 30) #define MXC_EHCI_MODE_ULPI (2 << 30) #define MXC_EHCI_MODE_SERIAL (3 << 30) /* values for flags field */ #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) #define MXC_EHCI_INTERFACE_MASK (0xf) |
1ca562025 USB: MX5: add gen... |
261 |
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) |
31ac2d0c6 ehci-mxc: Make EH... |
262 263 264 |
#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) #define MXC_EHCI_TTL_ENABLED (1 << 8) |
8eeb19be7 mx31: Move EHCI d... |
265 |
|
31ac2d0c6 ehci-mxc: Make EH... |
266 267 268 |
#define MXC_EHCI_INTERNAL_PHY (1 << 9) #define MXC_EHCI_IPPUE_DOWN (1 << 10) #define MXC_EHCI_IPPUE_UP (1 << 11) |
1ca562025 USB: MX5: add gen... |
269 |
|
229dbba9b usb:ehci-mx6 add ... |
270 |
int usb_phy_mode(int port); |
1ca562025 USB: MX5: add gen... |
271 272 |
/* Board-specific initialization */ int board_ehci_hcd_init(int port); |
2dcff642e usb: ehci-ci: Add... |
273 |
int board_ehci_power(int port, int on); |
229dbba9b usb:ehci-mx6 add ... |
274 |
int board_usb_phy_mode(int port); |
1ca562025 USB: MX5: add gen... |
275 |
|
e162c6b1a usb: Rename ehci-... |
276 |
#endif /* _EHCI_CI_H */ |