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arch/arm/dts/imx8mq-smarc.dts
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U-Boot lf_v2020.0...
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017 NXP
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
/dts-v1/;
#include "imx8mq.dtsi"
/ {
model = "Embedian SMARC-iMX8M Computer on Module";
compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0xc0000000>;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
buck2_reg: regulator-buck2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_buck2>;
compatible = "regulator-gpio";
regulator-name = "vdd_arm";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
states = <1000000 0x0
900000 0x1>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 1000000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
status = "disabled";
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: 5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
/* external oscillator of mcp2515 on SPI1.0 and SPI1.1 */
clk25m: clock-25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "clk25m";
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
fsl,magic-packet;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
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at803x,eee-disabled;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
fsl,pfuze-support-disable-sw;
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
s35390a: s35390a@30 {
compatible = "sii,s35390a";
reg = <0x30>;
};
cape_eeprom0: cape_eeprom@57 {
compatible = "at,24c256";
reg = <0x57>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
dsi_lvds_bridge: sn65dsi84@2c {
status = "disabled";
reg = <0x2c>;
compatible = "ti,sn65dsi84";
enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio4>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
/* AUO G070VW01 7-inch 800x480 LVDS Display */
sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;
/* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;*/
/* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;*/
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
ext_osc= <1>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
ext_osc = <1>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&snvs_pwrkey {
status = "okay";
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "peripheral";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
mmc-hs400-1_8v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
sd-uhs-sdr104;
sd-uhs-ddr50;
status = "okay";
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio1 0 GPIO_ACTIVE_LOW>,
<&gpio3 15 GPIO_ACTIVE_LOW>,
<&gpio3 17 GPIO_ACTIVE_LOW>;
fsl,spi-num-chipselects = <4>;
/*dmas = <&sdma2 10 24 0>, <&sdma2 11 24 0>;
dma-names = "rx", "tx";*/
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <24000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
spi-max-frequency = <24000000>;
};
can1: can@2 {
compatible = "microchip,mcp2515";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
clocks = <&clk25m>;
vdd-supply = <®_3p3v>;
xceiver-supply = <®_5p0v>;
status = "okay";
};
can2: can@3 {
compatible = "microchip,mcp2515";
reg = <3>;
interrupt-parent = <&gpio3>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
clocks = <&clk25m>;
vdd-supply = <®_3p3v>;
xceiver-supply = <®_5p0v>;
status = "okay";
};
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&dcss {
status = "okay";
port@0 {
dcss_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
&hdmi {
compatible = "fsl,imx8mq-hdmi";
status = "okay";
display-timings {
native-mode = <&timing1>;
timing1: timing1 {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <720>;
hfront-porch = <220>;
hback-porch = <110>;
hsync-len = <40>;
vback-porch = <5>;
vfront-porch = <20>;
vsync-len = <5>;
};
};
port@0 {
hdmi_in: endpoint {
remote-endpoint = <&dcss_out>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl_buck2: vddarmgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f
MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f
MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x7f
MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x7f
>;
};
pinctrl_i2c4_gpio: i2c4grp-gpio {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x7f
MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x7f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x79 /* RTS */
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x79 /* CTS */
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x79
MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x79
MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x79 /* RTS */
MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x79 /* CTS */
>;
};
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>;
};
pinctrl_ss_sel: usb3ssgrp{
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdog1grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19
>;
};
pinctrl_wifi_reset: wifiresetgrp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
>;
};
};
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