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arch/arm/dts/imx6qdl-sabreauto.dtsi
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67f165ddf arm: dts: Update ... |
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// SPDX-License-Identifier: GPL-2.0+ // // Copyright 2012 Freescale Semiconductor, Inc. // Copyright 2011 Linaro Ltd. |
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// Copyright 2017 NXP. |
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#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> / { |
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aliases { mxcfb0 = &mxcfb1; mxcfb1 = &mxcfb2; mxcfb2 = &mxcfb3; mxcfb3 = &mxcfb4; |
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}; |
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chosen { stdout-path = &uart4; |
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}; gpio-keys { |
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compatible = "gpio-keys1"; |
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pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; home { label = "Home"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; |
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gpio-key,wakeup; |
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linux,code = <KEY_HOME>; |
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}; back { label = "Back"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; |
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gpio-key,wakeup; |
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linux,code = <KEY_BACK>; |
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}; program { label = "Program"; gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
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gpio-key,wakeup; |
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linux,code = <KEY_PROGRAM>; |
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}; volume-up { label = "Volume Up"; gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; |
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gpio-key,wakeup; |
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linux,code = <KEY_VOLUMEUP>; |
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}; volume-down { label = "Volume Down"; gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; |
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gpio-key,wakeup; |
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linux,code = <KEY_VOLUMEDOWN>; |
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}; }; memory: memory { reg = <0x10000000 0x80000000>; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; user { label = "debug"; gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; |
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}; }; clocks { codec_osc: anaclk2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; }; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_audio: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "cs42888_supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; |
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reg_3p3v: 3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; |
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reg_usb_h1_vbus: regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_usb_otg_vbus: regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; |
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reg_si4763_vio1: regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vio1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; reg_si4763_vio2: regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "vio2"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; reg_si4763_vd: regulator@5 { compatible = "regulator-fixed"; reg = <5>; regulator-name = "vd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; reg_si4763_va: regulator@6 { compatible = "regulator-fixed"; reg = <6>; regulator-name = "va"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; }; reg_sd3_vmmc: regulator@7 { compatible = "regulator-fixed"; regulator-name = "P3V3_SDa_SWITCHED"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; enable-active-high; |
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u-boot,off-on-delay-us = <20000>; |
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/* remove below line to enable this regulator */ status = "disabled"; }; reg_can_en: regulator@8 { compatible = "regulator-fixed"; reg = <8>; regulator-name = "can-en"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_can_stby: regulator@9 { compatible = "regulator-fixed"; reg = <9>; regulator-name = "can-stby"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <®_can_en>; }; }; hannstar_cabc { compatible = "hannstar,cabc"; lvds_share { gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; }; }; sound-hdmi { compatible = "fsl,imx6q-audio-hdmi", "fsl,imx-audio-hdmi"; model = "imx-audio-hdmi"; hdmi-controller = <&hdmi_audio>; }; mxcfb1: fb@0 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "ldb"; interface_pix_fmt = "RGB666"; default_bpp = <16>; int_clk = <0>; late_init = <0>; status = "disabled"; }; mxcfb2: fb@1 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "hdmi"; interface_pix_fmt = "RGB24"; mode_str ="1920x1080M@60"; default_bpp = <24>; int_clk = <0>; late_init = <0>; status = "disabled"; }; mxcfb3: fb@2 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "lcd"; interface_pix_fmt = "RGB565"; mode_str ="CLAA-WVGA"; default_bpp = <16>; int_clk = <0>; late_init = <0>; status = "disabled"; }; mxcfb4: fb@3 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "ldb"; interface_pix_fmt = "RGB666"; default_bpp = <16>; int_clk = <0>; late_init = <0>; status = "disabled"; }; clocks { codec_osc: anaclk2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; }; |
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}; sound-cs42888 { compatible = "fsl,imx6-sabreauto-cs42888", |
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"fsl,imx-audio-cs42888"; |
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model = "imx-cs42888"; |
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esai-controller = <&esai>; asrc-controller = <&asrc>; |
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audio-codec = <&codec>; |
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}; sound-fm { compatible = "fsl,imx-audio-si476x", "fsl,imx-tuner-si476x"; model = "imx-radio-si4763"; ssi-controller = <&ssi2>; fm-controller = <&si476x_codec>; mux-int-port = <2>; mux-ext-port = <5>; |
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}; sound-spdif { compatible = "fsl,imx-audio-spdif", "fsl,imx-sabreauto-spdif"; model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; }; backlight { compatible = "pwm-backlight"; pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; status = "okay"; }; i2cmux { compatible = "i2c-mux-gpio"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3mux>; mux-gpios = <&gpio5 4 0>; i2c-parent = <&i2c3>; idle-state = <0>; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; |
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adv7180: adv7180@21 { compatible = "adv,adv7180"; |
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reg = <0x21>; |
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pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu1_1>; clocks = <&clks IMX6QDL_CLK_CKO>; clock-names = "csi_mclk"; DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ AVDD-supply = <®_3p3v>; /* 1.8v */ DVDD-supply = <®_3p3v>; /* 1.8v */ PVDD-supply = <®_3p3v>; /* 1.8v */ pwn-gpios = <&max7310_b 2 0>; csi_id = <0>; mclk = <24000000>; mclk_source = <0>; cvbs = <1>; |
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}; max7310_a: gpio@30 { compatible = "maxim,max7310"; reg = <0x30>; gpio-controller; #gpio-cells = <2>; }; max7310_b: gpio@32 { compatible = "maxim,max7310"; reg = <0x32>; gpio-controller; #gpio-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_max7310>; reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; max7310_c: gpio@34 { compatible = "maxim,max7310"; reg = <0x34>; gpio-controller; #gpio-cells = <2>; }; |
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isl29023@44 { compatible = "fsl,isl29023"; |
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reg = <0x44>; |
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rext = <499>; |
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interrupt-parent = <&gpio5>; |
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interrupts = <17 2>; |
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}; |
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mag3110@0e { |
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compatible = "fsl,mag3110"; reg = <0x0e>; |
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position = <2>; |
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interrupt-parent = <&gpio2>; |
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interrupts = <29 1>; |
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}; |
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mma8451@1c { |
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compatible = "fsl,mma8451"; reg = <0x1c>; |
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position = <7>; |
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interrupt-parent = <&gpio6>; |
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interrupts = <31 8>; interrupt-route = <1>; |
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}; }; }; |
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v4l2_cap_0 { compatible = "fsl,imx6q-v4l2-capture"; ipu_id = <0>; csi_id = <0>; mclk_source = <0>; status = "okay"; }; v4l2_out { compatible = "fsl,mxc_v4l2_output"; status = "okay"; }; |
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}; &ipu1_csi0_from_ipu1_csi0_mux { bus-width = <8>; }; &ipu1_csi0_mux_from_parallel_sensor { |
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/* Downstream driver doesn't use endpoints */ /* |
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remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; |
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*/ |
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bus-width = <8>; }; &ipu1_csi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu1_csi0>; }; |
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&audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; |
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&clks { assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, <&clks IMX6QDL_PLL4_BYPASS>, <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_PLL4_POST_DIV>; assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, <&clks IMX6QDL_PLL4_BYPASS_SRC>, |
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<&clks IMX6QDL_CLK_PLL2_PFD0_352M>, <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; |
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assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; }; |
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&dcic1 { dcic_id = <0>; dcic_mux = "dcic-hdmi"; status = "okay"; }; &dcic2 { dcic_id = <1>; dcic_mux = "dcic-lvds0"; status = "okay"; }; |
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&ecspi1 { |
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fsl,spi-num-chipselects = <1>; |
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cs-gpios = <&gpio3 19 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "disabled"; /* pin conflict with WEIM NOR */ flash: m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; }; }; &esai { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esai>; assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, <&clks IMX6QDL_CLK_ESAI_EXTAL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <24576000>; status = "okay"; }; &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; |
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fsl,magic-packet; |
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fsl,err006687-workaround-present; status = "okay"; }; |
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&can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */ xceiver-supply = <®_can_stby>; status = "disabled"; /* pin conflict with fec */ }; &can2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <®_can_stby>; status = "okay"; }; |
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&gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; |
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status = "disabled"; /* pin conflict with uart3 */ nand-on-flash-bbt; }; &hdmi_audio { |
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status = "okay"; }; |
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&hdmi_cec { |
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pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_cec>; |
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status = "okay"; }; &hdmi_core { ipu_id = <0>; disp_id = <1>; status = "okay"; }; &hdmi_video { fsl,phy_reg_vlev = <0x0294>; fsl,phy_reg_cksymtx = <0x800d>; |
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status = "okay"; }; &i2c2 { clock-frequency = <100000>; |
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pinctrl-names = "default", "gpio"; |
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pinctrl-0 = <&pinctrl_i2c2>; |
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pinctrl-1 = <&pinctrl_i2c2_gpio>; scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; |
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status = "okay"; |
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egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_egalax_int>; interrupt-parent = <&gpio2>; interrupts = <28 2>; wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; }; pmic: pfuze100@08 { |
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compatible = "fsl,pfuze100"; reg = <0x08>; regulators { sw1a_reg: sw1ab { regulator-min-microvolt = <300000>; regulator-max-microvolt = <1875000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; }; sw1c_reg: sw1c { regulator-min-microvolt = <300000>; regulator-max-microvolt = <1875000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; }; sw2_reg: sw2 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; sw3a_reg: sw3a { regulator-min-microvolt = <400000>; regulator-max-microvolt = <1975000>; regulator-boot-on; regulator-always-on; }; sw3b_reg: sw3b { regulator-min-microvolt = <400000>; regulator-max-microvolt = <1975000>; regulator-boot-on; regulator-always-on; }; sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; swbst_reg: swbst { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5150000>; }; snvs_reg: vsnvs { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; regulator-boot-on; regulator-always-on; }; vref_reg: vrefddr { regulator-boot-on; regulator-always-on; }; vgen1_reg: vgen1 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; }; vgen2_reg: vgen2 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; }; vgen3_reg: vgen3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen5_reg: vgen5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen6_reg: vgen6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; |
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hdmi_edid: edid@50 { compatible = "fsl,imx6-hdmi-i2c"; reg = <0x50>; }; |
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codec: cs42888@48 { compatible = "cirrus,cs42888"; reg = <0x48>; clocks = <&codec_osc>; clock-names = "mclk"; VA-supply = <®_audio>; VD-supply = <®_audio>; VLS-supply = <®_audio>; VLC-supply = <®_audio>; }; |
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si4763: si4763@63 { compatible = "si4761"; reg = <0x63>; va-supply = <®_si4763_va>; vd-supply = <®_si4763_vd>; vio1-supply = <®_si4763_vio1>; vio2-supply = <®_si4763_vio2>; revision-a10; /* set to default A10 compatible command set */ si476x_codec: si476x-codec { compatible = "si476x-codec"; }; |
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}; }; &i2c3 { |
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pinctrl-names = "default", "gpio"; |
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pinctrl-0 = <&pinctrl_i2c3>; |
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pinctrl-1 = <&pinctrl_i2c3_gpio>; scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; |
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status = "okay"; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; imx6qdl-sabreauto { |
800a1c47f MLK-18147-1 arm: ... |
669 670 671 672 673 674 675 |
pinctrl_audmux: audmux { fsl,pins = < MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 >; }; |
67f165ddf arm: dts: Update ... |
676 677 |
pinctrl_hog: hoggrp { fsl,pins = < |
800a1c47f MLK-18147-1 arm: ... |
678 |
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059 |
67f165ddf arm: dts: Update ... |
679 680 |
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 |
800a1c47f MLK-18147-1 arm: ... |
681 682 683 684 685 686 |
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059 |
67f165ddf arm: dts: Update ... |
687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 |
>; }; pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 >; }; pinctrl_ecspi1_cs: ecspi1cs { fsl,pins = < MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 >; }; |
800a1c47f MLK-18147-1 arm: ... |
703 |
pinctrl_egalax_int: egalax_intgrp { |
67f165ddf arm: dts: Update ... |
704 |
fsl,pins = < |
800a1c47f MLK-18147-1 arm: ... |
705 |
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 |
67f165ddf arm: dts: Update ... |
706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 |
>; }; pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 |
800a1c47f MLK-18147-1 arm: ... |
726 727 728 729 730 731 |
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; pinctrl_enet_irq: enetirqgrp { fsl,pins = < |
67f165ddf arm: dts: Update ... |
732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 |
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; pinctrl_esai: esaigrp { fsl,pins = < MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 >; }; |
800a1c47f MLK-18147-1 arm: ... |
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 |
pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 >; }; pinctrl_gpio_keys: gpio_keysgrp { |
67f165ddf arm: dts: Update ... |
765 |
fsl,pins = < |
800a1c47f MLK-18147-1 arm: ... |
766 767 768 769 770 |
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 |
67f165ddf arm: dts: Update ... |
771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 |
>; }; pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 >; }; pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 >; }; |
800a1c47f MLK-18147-1 arm: ... |
801 |
pinctrl_i2c2: i2c2grp { |
67f165ddf arm: dts: Update ... |
802 |
fsl,pins = < |
800a1c47f MLK-18147-1 arm: ... |
803 804 |
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
67f165ddf arm: dts: Update ... |
805 806 |
>; }; |
800a1c47f MLK-18147-1 arm: ... |
807 |
pinctrl_i2c2_gpio: i2c2grp_gpio { |
67f165ddf arm: dts: Update ... |
808 |
fsl,pins = < |
800a1c47f MLK-18147-1 arm: ... |
809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 |
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b8b1 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b8b1 >; }; pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ fsl,pins = < MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 |
67f165ddf arm: dts: Update ... |
835 836 837 838 839 840 841 842 843 |
>; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 >; }; |
800a1c47f MLK-18147-1 arm: ... |
844 845 846 847 848 849 850 |
pinctrl_i2c3_gpio: i2c3grp_gpio { fsl,pins = < MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b8b1 >; }; |
67f165ddf arm: dts: Update ... |
851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 |
pinctrl_i2c3mux: i2c3muxgrp { fsl,pins = < MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 >; }; pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 >; }; pinctrl_max7310: max7310grp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 >; }; |
800a1c47f MLK-18147-1 arm: ... |
879 880 881 882 883 884 885 |
pinctrl_mlb: mlb { fsl,pins = < MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 >; }; |
67f165ddf arm: dts: Update ... |
886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 |
pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 >; }; pinctrl_gpt_input_capture0: gptinputcapture0grp { fsl,pins = < MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 >; }; pinctrl_gpt_input_capture1: gptinputcapture1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 >; }; pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 >; }; |
800a1c47f MLK-18147-1 arm: ... |
909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 |
pinctrl_uart3_1: uart3grp-1 { fsl,pins = < MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; }; pinctrl_uart3dte_1: uart3dtegrp-1 { fsl,pins = < MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 >; }; |
67f165ddf arm: dts: Update ... |
926 927 928 929 930 931 932 933 934 935 936 937 |
pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 >; }; pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 >; }; |
800a1c47f MLK-18147-1 arm: ... |
938 939 940 941 942 943 944 945 946 947 |
pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 >; }; |
67f165ddf arm: dts: Update ... |
948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 |
pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 >; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 >; }; pinctrl_weim_cs0: weimcs0grp { fsl,pins = < MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 >; }; pinctrl_weim_nor: weimnorgrp { fsl,pins = < MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 >; }; |
800a1c47f MLK-18147-1 arm: ... |
1046 1047 1048 1049 1050 1051 |
pinctrl_hdmi_cec: hdmicecgrp { fsl,pins = < MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 >; }; |
67f165ddf arm: dts: Update ... |
1052 1053 1054 1055 1056 1057 1058 1059 1060 |
}; }; &ldb { status = "okay"; lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; |
800a1c47f MLK-18147-1 arm: ... |
1061 |
primary; |
67f165ddf arm: dts: Update ... |
1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 |
status = "okay"; display-timings { native-mode = <&timing0>; timing0: hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; hback-porch = <220>; hfront-porch = <40>; vback-porch = <21>; vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; }; }; }; |
800a1c47f MLK-18147-1 arm: ... |
1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 |
lvds-channel@1 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; display-timings { native-mode = <&timing1>; timing1: hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; hback-porch = <220>; hfront-porch = <40>; vback-porch = <21>; vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; }; }; }; }; &mlb { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mlb>; status = "okay"; |
67f165ddf arm: dts: Update ... |
1106 1107 1108 1109 1110 1111 1112 |
}; &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; |
800a1c47f MLK-18147-1 arm: ... |
1113 1114 1115 |
&pcie { status = "okay"; }; |
67f165ddf arm: dts: Update ... |
1116 1117 1118 |
&spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdif>; |
800a1c47f MLK-18147-1 arm: ... |
1119 1120 1121 1122 |
assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>, <&clks IMX6QDL_CLK_SPDIF_PODF>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>; assigned-clock-rates = <0>, <227368421>; |
67f165ddf arm: dts: Update ... |
1123 1124 |
status = "okay"; }; |
800a1c47f MLK-18147-1 arm: ... |
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 |
&snvs_poweroff { status = "okay"; }; &ssi2 { assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>; fsl,mode = "i2s-master"; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_1>; pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ fsl,uart-has-rtscts; status = "okay"; /* for DTE mode, add below change */ /* fsl,dte-mode; */ /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ }; |
67f165ddf arm: dts: Update ... |
1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 |
&uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; &usbh1 { vbus-supply = <®_usb_h1_vbus>; status = "okay"; }; &usbotg { vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; |
800a1c47f MLK-18147-1 arm: ... |
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 |
srp-disable; hnp-disable; adp-disable; status = "okay"; }; &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; no-1-8-v; keep-power-in-suspend; enable-sdio-wakeup; |
67f165ddf arm: dts: Update ... |
1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 |
status = "okay"; }; &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
800a1c47f MLK-18147-1 arm: ... |
1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 |
/* * Due to board issue, we can not use external regulator for card slot * by default since the card power is shared with card detect pullup. * Disabling the vmmc regulator will cause unexpected card detect * interrupts. * HW rework is needed to fix this isssue. Remove R695 first, then you * can open below line to enable the using of external regulator. * Then you will be able to power off the card during suspend. This is * especially needed for a SD3.0 card re-enumeration working on UHS mode * Note: reg_sd3_vmmc is also need to be enabled */ /* vmmc-supply = <®_sd3_vmmc>; */ keep-power-in-suspend; enable-sdio-wakeup; |
67f165ddf arm: dts: Update ... |
1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 |
status = "okay"; }; &weim { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; ranges = <0 0 0x08000000 0x08000000>; status = "disabled"; /* pin conflict with SPI NOR */ nor@0,0 { compatible = "cfi-flash"; reg = <0 0 0x02000000>; #address-cells = <1>; #size-cells = <1>; bank-width = <2>; fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 0x0000c000 0x1404a38e 0x00000000>; }; }; |