/* SPDX-License-Identifier: GPL-2.0+ */

  /*
   * Configuation settings for the Renesas Technology RSK 7203
   *
   * Copyright (C) 2008 Nobuhiro Iwamatsu
   * Copyright (C) 2008 Renesas Solutions Corp.

   */
  
  #ifndef __RSK7203_H
  #define __RSK7203_H

  #define CONFIG_CPU_SH7203	1

  #define CONFIG_LOADADDR		0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */

  #define CONFIG_DISPLAY_BOARDINFO

  #undef	CONFIG_SHOW_BOOT_PROGRESS
  
  /* MEMORY */
  #define RSK7203_SDRAM_BASE	0x0C000000
  #define RSK7203_FLASH_BASE_1	0x20000000	/* Non cache */
  #define RSK7203_FLASH_BANK_SIZE	(4 * 1024 * 1024)

  /* List of legal baudrate settings for this board */

  #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

  
  /* SCIF */

  #define CONFIG_CONS_SCIF0	1

  #define CONFIG_SYS_MEMTEST_START	RSK7203_SDRAM_BASE
  #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))

  #define CONFIG_SYS_SDRAM_BASE		RSK7203_SDRAM_BASE
  #define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)

  #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
  #define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
  #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
  #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)

  #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

  
  /* FLASH */

  #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  #undef	CONFIG_SYS_FLASH_QUIET_TEST
  #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
  #define CONFIG_SYS_FLASH_BASE		RSK7203_FLASH_BASE_1
  #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
  #define CONFIG_SYS_MAX_FLASH_SECT	64
  #define CONFIG_SYS_MAX_FLASH_BANKS	1

  #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
  #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  #define CONFIG_SYS_FLASH_ERASE_TOUT	12000
  #define CONFIG_SYS_FLASH_WRITE_TOUT	500

  
  /* Board Clock */
  #define CONFIG_SYS_CLK_FREQ	33333333

  #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ

  #define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */

  #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)

  
  #endif	/* __RSK7203_H */