Blame view
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
2.45 KB
08ac386bb ARM64: zynqmp: Ad... |
1 2 3 4 5 6 7 |
/* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015 - 2016, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * |
5fe03269f arm64: zynqmp: Us... |
8 |
* SPDX-License-Identifier: GPL-2.0+ |
08ac386bb ARM64: zynqmp: Ad... |
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 |
*/ /dts-v1/; #include "zynqmp.dtsi" #include "zynqmp-clk.dtsi" / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &qspi; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; |
c926e6fbb ARM64: zynqmp: Re... |
40 |
memory@0 { |
08ac386bb ARM64: zynqmp: Ad... |
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 |
device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; }; &can0 { status = "okay"; }; &can1 { status = "okay"; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
57 58 59 60 |
}; &fpd_dma_chan2 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
61 62 63 64 65 66 67 68 |
}; &fpd_dma_chan3 { status = "okay"; }; &fpd_dma_chan4 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
69 70 71 72 73 74 75 76 |
}; &fpd_dma_chan5 { status = "okay"; }; &fpd_dma_chan6 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
77 78 79 80 81 82 83 84 |
}; &fpd_dma_chan7 { status = "okay"; }; &fpd_dma_chan8 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 |
}; &lpd_dma_chan1 { status = "okay"; }; &lpd_dma_chan2 { status = "okay"; }; &lpd_dma_chan3 { status = "okay"; }; &lpd_dma_chan4 { status = "okay"; }; &lpd_dma_chan5 { status = "okay"; }; &lpd_dma_chan6 { status = "okay"; }; &lpd_dma_chan7 { status = "okay"; }; &lpd_dma_chan8 { status = "okay"; }; &xlnx_dp { status = "okay"; }; &xlnx_dpdma { status = "okay"; }; &gem0 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 |
phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
147 148 149 150 151 152 |
phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
153 154 155 156 157 158 |
phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; |
08ac386bb ARM64: zynqmp: Ad... |
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 |
phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &gpio { status = "okay"; }; &gpu { status = "okay"; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; &rtc { status = "okay"; }; &uart0 { status = "okay"; }; &uart1 { status = "okay"; }; &watchdog0 { status = "okay"; }; |