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include/configs/highbank.h
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/* * Copyright 2010-2011 Calxeda, Inc. * |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ #ifndef __CONFIG_H #define __CONFIG_H |
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#define CONFIG_SYS_DCACHE_OFF |
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20) |
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#define CONFIG_SYS_TIMER_RATE (150000000/256) #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) #define CONFIG_SYS_TIMER_COUNTS_DOWN |
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/* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
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#define CONFIG_PL011_CLOCK 150000000 #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } #define CONFIG_CONS_INDEX 0 |
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#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ |
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#define CONFIG_MISC_INIT_R |
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#define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) |
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#define CONFIG_CALXEDA_XGMAC |
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/* * Command line configuration. */ |
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#define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_RESET_TO_RETRY |
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/* * Miscellaneous configurable options */ |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_SYS_LOAD_ADDR 0x800000 |
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#define CONFIG_SYS_64BIT_LBA |
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/*----------------------------------------------------------------------- |
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* Physical Memory Map |
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* The DRAM is already setup, so do not touch the DT node later. |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 0 |
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#define PHYS_SDRAM_1_SIZE (4089 << 20) #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000) |
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/* Environment data setup */ |
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ #define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */ #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_INIT_SP_ADDR 0x01000000 #define CONFIG_SKIP_LOWLEVEL_INIT #endif |