Blame view
post/lib_powerpc/rlwinm.c
2.66 KB
ad5bb451a Restructure POST ... |
1 2 3 4 |
/* * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * |
1a4596601 Add GPL-2.0+ SPDX... |
5 |
* SPDX-License-Identifier: GPL-2.0+ |
ad5bb451a Restructure POST ... |
6 7 8 9 10 11 12 13 14 15 16 17 |
*/ #include <common.h> /* * CPU test * Shift instructions: rlwinm * * The test contains a pre-built table of instructions, operands and * expected results. For each table entry, the test will cyclically use * different sets of operand registers and result registers. */ |
ad5bb451a Restructure POST ... |
18 19 |
#include <post.h> #include "cpu_asm.h" |
6d0f6bcf3 rename CFG_ macro... |
20 |
#if CONFIG_POST & CONFIG_SYS_POST_CPU |
ad5bb451a Restructure POST ... |
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 |
extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); static struct cpu_post_rlwinm_s { ulong cmd; ulong op1; uchar op2; uchar mb; uchar me; ulong res; } cpu_post_rlwinm_table[] = { { |
53677ef18 Big white-space c... |
36 |
OP_RLWINM, |
ad5bb451a Restructure POST ... |
37 38 39 40 41 42 43 |
0xffff0000, 24, 16, 23, 0x0000ff00 }, }; |
d2397817f post: use ARRAY_SIZE |
44 |
static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table); |
ad5bb451a Restructure POST ... |
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 |
int cpu_post_test_rlwinm (void) { int ret = 0; unsigned int i, reg; int flag = disable_interrupts(); for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++) { struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i; for (reg = 0; reg < 32 && ret == 0; reg++) { unsigned int reg0 = (reg + 0) % 32; unsigned int reg1 = (reg + 1) % 32; unsigned int stk = reg < 16 ? 31 : 15; |
53677ef18 Big white-space c... |
61 |
unsigned long code[] = |
ad5bb451a Restructure POST ... |
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 |
{ ASM_STW(stk, 1, -4), ASM_ADDI(stk, 1, -16), ASM_STW(3, stk, 8), ASM_STW(reg0, stk, 4), ASM_STW(reg1, stk, 0), ASM_LWZ(reg0, stk, 8), ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), ASM_STW(reg1, stk, 8), ASM_LWZ(reg1, stk, 0), ASM_LWZ(reg0, stk, 4), ASM_LWZ(3, stk, 8), ASM_ADDI(1, stk, 16), ASM_LWZ(stk, 1, -4), ASM_BLR, }; |
53677ef18 Big white-space c... |
78 |
unsigned long codecr[] = |
ad5bb451a Restructure POST ... |
79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 |
{ ASM_STW(stk, 1, -4), ASM_ADDI(stk, 1, -16), ASM_STW(3, stk, 8), ASM_STW(reg0, stk, 4), ASM_STW(reg1, stk, 0), ASM_LWZ(reg0, stk, 8), ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | BIT_C, ASM_STW(reg1, stk, 8), ASM_LWZ(reg1, stk, 0), ASM_LWZ(reg0, stk, 4), ASM_LWZ(3, stk, 8), ASM_ADDI(1, stk, 16), ASM_LWZ(stk, 1, -4), ASM_BLR, }; ulong res; ulong cr; if (ret == 0) { |
53677ef18 Big white-space c... |
101 102 |
cr = 0; cpu_post_exec_21 (code, & cr, & res, test->op1); |
ad5bb451a Restructure POST ... |
103 |
|
53677ef18 Big white-space c... |
104 |
ret = res == test->res && cr == 0 ? 0 : -1; |
ad5bb451a Restructure POST ... |
105 |
|
53677ef18 Big white-space c... |
106 107 |
if (ret != 0) { |
93e145964 Coding Style clea... |
108 109 |
post_log ("Error at rlwinm test %d ! ", i); |
53677ef18 Big white-space c... |
110 |
} |
ad5bb451a Restructure POST ... |
111 112 113 114 |
} if (ret == 0) { |
53677ef18 Big white-space c... |
115 |
cpu_post_exec_21 (codecr, & cr, & res, test->op1); |
ad5bb451a Restructure POST ... |
116 |
|
53677ef18 Big white-space c... |
117 |
ret = res == test->res && |
ad5bb451a Restructure POST ... |
118 |
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; |
53677ef18 Big white-space c... |
119 120 |
if (ret != 0) { |
93e145964 Coding Style clea... |
121 122 123 |
post_log ("Error at rlwinm test %d ! ", i); } |
ad5bb451a Restructure POST ... |
124 125 126 127 128 |
} } } if (flag) |
53677ef18 Big white-space c... |
129 |
enable_interrupts(); |
ad5bb451a Restructure POST ... |
130 131 132 133 134 |
return ret; } #endif |