Blame view
post/lib_powerpc/twox.c
2.75 KB
ad5bb451a
|
1 2 3 4 |
/* * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * |
1a4596601
|
5 |
* SPDX-License-Identifier: GPL-2.0+ |
ad5bb451a
|
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 |
*/ #include <common.h> /* * CPU test * Binary instructions instr rA,rS * * Logic instructions: cntlzw * Arithmetic instructions: extsb, extsh * The test contains a pre-built table of instructions, operands and * expected results. For each table entry, the test will cyclically use * different sets of operand registers and result registers. */ |
ad5bb451a
|
21 22 |
#include <post.h> #include "cpu_asm.h" |
6d0f6bcf3
|
23 |
#if CONFIG_POST & CONFIG_SYS_POST_CPU |
ad5bb451a
|
24 25 26 27 28 29 30 31 32 33 34 35 |
extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); static struct cpu_post_twox_s { ulong cmd; ulong op; ulong res; } cpu_post_twox_table[] = { { |
53677ef18
|
36 |
OP_EXTSB, |
ad5bb451a
|
37 38 39 40 |
3, 3 }, { |
53677ef18
|
41 |
OP_EXTSB, |
ad5bb451a
|
42 43 44 45 |
0xff, -1 }, { |
53677ef18
|
46 |
OP_EXTSH, |
ad5bb451a
|
47 48 49 50 |
3, 3 }, { |
53677ef18
|
51 |
OP_EXTSH, |
ad5bb451a
|
52 53 54 55 |
0xff, 0xff }, { |
53677ef18
|
56 |
OP_EXTSH, |
ad5bb451a
|
57 58 59 60 |
0xffff, -1 }, { |
53677ef18
|
61 |
OP_CNTLZW, |
ad5bb451a
|
62 63 64 65 |
0x000fffff, 12 }, }; |
d2397817f
|
66 |
static unsigned int cpu_post_twox_size = ARRAY_SIZE(cpu_post_twox_table); |
ad5bb451a
|
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 |
int cpu_post_test_twox (void) { int ret = 0; unsigned int i, reg; int flag = disable_interrupts(); for (i = 0; i < cpu_post_twox_size && ret == 0; i++) { struct cpu_post_twox_s *test = cpu_post_twox_table + i; for (reg = 0; reg < 32 && ret == 0; reg++) { unsigned int reg0 = (reg + 0) % 32; unsigned int reg1 = (reg + 1) % 32; unsigned int stk = reg < 16 ? 31 : 15; |
53677ef18
|
83 |
unsigned long code[] = |
ad5bb451a
|
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 |
{ ASM_STW(stk, 1, -4), ASM_ADDI(stk, 1, -16), ASM_STW(3, stk, 8), ASM_STW(reg0, stk, 4), ASM_STW(reg1, stk, 0), ASM_LWZ(reg0, stk, 8), ASM_11X(test->cmd, reg1, reg0), ASM_STW(reg1, stk, 8), ASM_LWZ(reg1, stk, 0), ASM_LWZ(reg0, stk, 4), ASM_LWZ(3, stk, 8), ASM_ADDI(1, stk, 16), ASM_LWZ(stk, 1, -4), ASM_BLR, }; |
53677ef18
|
100 |
unsigned long codecr[] = |
ad5bb451a
|
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 |
{ ASM_STW(stk, 1, -4), ASM_ADDI(stk, 1, -16), ASM_STW(3, stk, 8), ASM_STW(reg0, stk, 4), ASM_STW(reg1, stk, 0), ASM_LWZ(reg0, stk, 8), ASM_11X(test->cmd, reg1, reg0) | BIT_C, ASM_STW(reg1, stk, 8), ASM_LWZ(reg1, stk, 0), ASM_LWZ(reg0, stk, 4), ASM_LWZ(3, stk, 8), ASM_ADDI(1, stk, 16), ASM_LWZ(stk, 1, -4), ASM_BLR, }; ulong res; ulong cr; if (ret == 0) { |
53677ef18
|
122 123 |
cr = 0; cpu_post_exec_21 (code, & cr, & res, test->op); |
ad5bb451a
|
124 |
|
53677ef18
|
125 |
ret = res == test->res && cr == 0 ? 0 : -1; |
ad5bb451a
|
126 |
|
53677ef18
|
127 128 |
if (ret != 0) { |
93e145964
|
129 130 |
post_log ("Error at twox test %d ! ", i); |
53677ef18
|
131 |
} |
ad5bb451a
|
132 133 134 135 |
} if (ret == 0) { |
53677ef18
|
136 |
cpu_post_exec_21 (codecr, & cr, & res, test->op); |
ad5bb451a
|
137 |
|
53677ef18
|
138 |
ret = res == test->res && |
ad5bb451a
|
139 |
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; |
53677ef18
|
140 141 |
if (ret != 0) { |
93e145964
|
142 143 144 |
post_log ("Error at twox test %d ! ", i); } |
ad5bb451a
|
145 146 147 148 149 |
} } } if (flag) |
53677ef18
|
150 |
enable_interrupts(); |
ad5bb451a
|
151 152 153 154 155 |
return ret; } #endif |