// SPDX-License-Identifier: GPL-2.0+
  /*
   * Copyright 2019 NXP
   */
  
  #include <common.h>
  #include <errno.h>
  #include <hang.h>
  #include <miiphy.h>
  #include <netdev.h>
  #include <asm/io.h>
  #include <asm/mach-imx/iomux-v3.h>
  #include <asm-generic/gpio.h>
  #include <asm/arch/imx8mp_pins.h>
  #include <asm/arch/sys_proto.h>
  #include <asm/mach-imx/gpio.h>
  #include <asm/mach-imx/mxc_i2c.h>
  #include <asm/arch/clock.h>
  #include <spl.h>
  #include <asm/mach-imx/dma.h>
  #include <power/pmic.h>
  #include "../../freescale/common/tcpc.h"
  #include <usb.h>
  #include <dwc3-uboot.h>
  #include <mmc.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
  #define QSPI_PAD_CTRL   (PAD_CTL_DSE2 | PAD_CTL_HYS)
  #define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  #define WEAK_PULLUP 	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  #define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  #define I2C_PAD_CTRL 	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)	
  
  #ifdef CONFIG_CONSOLE_SER0
  static iomux_v3_cfg_t const uart1_pads[] = {
  	MX8MP_PAD_SD1_CMD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX8MP_PAD_SD1_CLK__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  #endif
  
  #ifdef CONFIG_CONSOLE_SER1
  static iomux_v3_cfg_t const uart4_pads[] = {
  	MX8MP_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX8MP_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  #endif
  
  #ifdef CONFIG_CONSOLE_SER2
  static iomux_v3_cfg_t const uart3_pads[] = {
  	MX8MP_PAD_SD1_DATA7__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX8MP_PAD_SD1_DATA6__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  #endif
  
  #ifdef CONFIG_CONSOLE_SER3
  static iomux_v3_cfg_t const uart2_pads[] = {
  	MX8MP_PAD_SD1_DATA3__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX8MP_PAD_SD1_DATA2__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  #endif
  
  static iomux_v3_cfg_t const wdog_pads[] = {
  	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  };
  
  /* MISC PINs */
  static iomux_v3_cfg_t const misc_pads[] = {
  	MX8MP_PAD_SD1_DATA5__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),		/*S146, PCIE_WAKE */
  	MX8MP_PAD_I2C4_SCL__PCIE_CLKREQ_B | MUX_PAD_CTRL(WEAK_PULLUP),		/*P78, PCIE_A_CKREQ# */
  	MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),		
  /*P123, BOOT_SEL0# */
  	MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),		
  /*P124, BOOT_SEL1# */
  	MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P125, BOOT_SEL2# */
  };
  
  static void setup_iomux_misc(void)
  {
          imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
  
  	/* Set PCIE_WAKE# as Input */
  	gpio_request(IMX_GPIO_NR(2, 7), "PCIE_WAKE#");
  	gpio_direction_input(IMX_GPIO_NR(2, 7));
  	/* Set BOOT_SEL0# as Input */
  	gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL0#");
  	gpio_direction_input(IMX_GPIO_NR(1, 5));
  	/* Set BOOT_SEL1# as Input */
  	gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL1#");
  	gpio_direction_input(IMX_GPIO_NR(1, 6));
  	/* Set BOOT_SEL2# as Input */
  	gpio_request(IMX_GPIO_NR(1, 7), "BOOT_SEL2#");
  	gpio_direction_input(IMX_GPIO_NR(1, 7));
  }
  
  /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/
  static iomux_v3_cfg_t const gpio_pads[] = {
  	MX8MP_PAD_NAND_DATA00__GPIO3_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P108, GPIO0*/
  	MX8MP_PAD_NAND_DATA01__GPIO3_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P109, GPIO1*/
  	MX8MP_PAD_NAND_DATA02__GPIO3_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P110, GPIO2*/
  	MX8MP_PAD_NAND_DATA03__GPIO3_IO09 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P111, GPIO3*/
  	MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P112, GPIO4*/
  	MX8MP_PAD_I2C4_SDA__GPIO5_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P113, GPIO5*/
  	MX8MP_PAD_SAI3_TXC__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P114, GPIO6*/
  	MX8MP_PAD_SAI3_TXD__GPIO5_IO01 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P115, GPIO7*/
  	MX8MP_PAD_SAI3_RXC__GPIO4_IO29 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P116, GPIO8*/
  	MX8MP_PAD_SPDIF_TX__GPIO5_IO03 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P114, GPIO9*/
  	MX8MP_PAD_SPDIF_RX__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),		/*P115, GPIO10*/
  	MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),	/*P116, GPIO11*/
  };
  
  static void setup_iomux_gpio(void)
  {
          imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  
          /* Set GPIO0 as Output Low*/
          gpio_request(IMX_GPIO_NR(3, 6), "GPIO0");
          gpio_direction_output(IMX_GPIO_NR(3, 6), 0);
          /* Set GPIO1 as Output Low*/
          gpio_request(IMX_GPIO_NR(3, 7), "GPIO1");
          gpio_direction_output(IMX_GPIO_NR(3, 7), 0);
          /* Set GPIO2 as Output Low*/
          gpio_request(IMX_GPIO_NR(3, 8), "GPIO2");
          gpio_direction_output(IMX_GPIO_NR(3, 8), 0);
          /* Set GPIO3 as Output Low*/
          gpio_request(IMX_GPIO_NR(3, 9), "GPIO3");
          gpio_direction_output(IMX_GPIO_NR(3, 9), 0);
          /* Set GPIO4 as Output Low*/
          gpio_request(IMX_GPIO_NR(1, 15), "GPIO4");
          gpio_direction_output(IMX_GPIO_NR(1, 15), 0);
          /* Set GPIO5 as Output Low*/
          gpio_request(IMX_GPIO_NR(5, 21), "GPIO5");
          gpio_direction_output(IMX_GPIO_NR(5, 21), 0);
          /* Set GPIO6 as Input*/
          gpio_request(IMX_GPIO_NR(5, 0), "GPIO6");
          gpio_direction_input(IMX_GPIO_NR(5, 0));
          /* Set GPIO7 as Input*/
          gpio_request(IMX_GPIO_NR(5, 1), "GPIO7");
          gpio_direction_input(IMX_GPIO_NR(5, 1));
          /* Set GPIO8 as Input*/
          gpio_request(IMX_GPIO_NR(4, 29), "GPIO8");
          gpio_direction_input(IMX_GPIO_NR(4, 29));
          /* Set GPIO9 as Input*/
          gpio_request(IMX_GPIO_NR(5, 3), "GPIO9");
          gpio_direction_input(IMX_GPIO_NR(5, 3));
          /* Set GPIO10 as Input*/
          gpio_request(IMX_GPIO_NR(5, 4), "GPIO10");
          gpio_direction_input(IMX_GPIO_NR(5, 4));
          /* Set GPIO11 as Input*/
          gpio_request(IMX_GPIO_NR(5, 5), "GPIO11");
          gpio_direction_input(IMX_GPIO_NR(5, 5));
  }
  
  #ifdef CONFIG_SYS_I2C
  /*I2C2, I2C_LCD*/
  struct i2c_pads_info i2c_pad_info2 = {
  	.scl = {
  		.i2c_mode = MX8MP_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(5, 16),
  	},
  	.sda = {
  		.i2c_mode = MX8MP_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(5, 17),
  	},
  };
  
  /*I2C3, I2C_GP*/
  struct i2c_pads_info i2c_pad_info3 = {
  	.scl = {
  		.i2c_mode = MX8MP_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(5, 18),
  	},
  	.sda = {
  		.i2c_mode = MX8MP_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(5, 19),
  	},
  };
  
  /*I2C4, I2C_CAM0*/
  struct i2c_pads_info i2c_pad_info4 = {
  	.scl = {
  		.i2c_mode = MX8MP_PAD_ECSPI2_MISO__I2C4_SCL | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(5, 12),
  	},
  	.sda = {
  		.i2c_mode = MX8MP_PAD_ECSPI2_SS0__I2C4_SDA | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(5, 13),
  	},
  };
  
  /*I2C6, I2C_CAM1*/
  struct i2c_pads_info i2c_pad_info6 = {
  	.scl = {
  		.i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(3, 19),
  	},
  	.sda = {
  		.i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | I2C_PAD_CTRL,
  		.gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | I2C_PAD_CTRL,
  		.gp = IMX_GPIO_NR(3, 20),
  	},
  };
  #endif
  
  #ifdef CONFIG_NAND_MXS
  
  static void setup_gpmi_nand(void)
  {
  	init_nand_clk();
  }
  #endif
  
  int board_early_init_f(void)
  {
  	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  
  	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  
  	set_wdog_reset(wdog);
  
  #ifdef CONFIG_CONSOLE_SER0
  	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  	init_uart_clk(0);
  #endif
  
  #ifdef CONFIG_CONSOLE_SER1
          imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  	init_uart_clk(3);
  #endif
  
  #ifdef CONFIG_CONSOLE_SER2
  	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  	init_uart_clk(2);
  #endif
  
  #ifdef CONFIG_CONSOLE_SER3
  	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  	init_uart_clk(1);
  #endif
  
  	return 0;
  }
  
  #ifdef CONFIG_OF_BOARD_SETUP
  int ft_board_setup(void *blob, bd_t *bd)
  {
  #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
  #ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
  	int rc;
  	phys_addr_t ecc_start = 0x120000000;
  	size_t ecc_size = 0x20000000;
  
  	rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size);
  	if (rc < 0) {
  		printf("Could not create ecc reserved-memory node.
  ");
  		return rc;
  	}
  #else
  	int rc;
  	phys_addr_t ecc0_start = 0xb0000000;
  	phys_addr_t ecc1_start = 0x130000000;
  	phys_addr_t ecc2_start = 0x1b0000000;
  	size_t ecc_size = 0x10000000;
  
  	rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size);
  	if (rc < 0) {
  		printf("Could not create ecc0 reserved-memory node.
  ");
  		return rc;
  	}
  
  	rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size);
  	if (rc < 0) {
  		printf("Could not create ecc1 reserved-memory node.
  ");
  		return rc;
  	}
  
  	rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size);
  	if (rc < 0) {
  		printf("Could not create ecc2 reserved-memory node.
  ");
  		return rc;
  	}
  #endif
  #endif
  
  	return 0;
  }
  #endif
  
  #ifdef CONFIG_FEC_MXC
  #define FEC_IRQ_PAD IMX_GPIO_NR(4, 21)
  static iomux_v3_cfg_t const fec1_irq_pads[] = {
  	MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static void setup_iomux_fec(void)
  {
  	imx_iomux_v3_setup_multiple_pads(fec1_irq_pads,
  					 ARRAY_SIZE(fec1_irq_pads));
  
  	gpio_request(FEC_IRQ_PAD, "fec1_irq");
  	gpio_direction_input(FEC_IRQ_PAD);
  }
  
  static int setup_fec(void)
  {
  	struct iomuxc_gpr_base_regs *gpr =
  		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  
  	setup_iomux_fec();
  
  	/* Enable RGMII TX clk output */
  	setbits_le32(&gpr->gpr[1], BIT(22));
  
  	//return set_clk_enet(ENET_125MHZ);
  	return 0;
  }
  #endif
  
  #ifdef CONFIG_DWC_ETH_QOS
  
  #define EQOS_IRQ_PAD IMX_GPIO_NR(4, 3)
  static iomux_v3_cfg_t const eqos_irq_pads[] = {
  	MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static void setup_iomux_eqos(void)
  {
  	imx_iomux_v3_setup_multiple_pads(eqos_irq_pads,
  					 ARRAY_SIZE(eqos_irq_pads));
  
  	gpio_request(EQOS_IRQ_PAD, "eqos_irq");
  	gpio_direction_input(EQOS_IRQ_PAD);
  }
  
  static int setup_eqos(void)
  {
  	struct iomuxc_gpr_base_regs *gpr =
  		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  
  	setup_iomux_eqos();
  
  	/* set INTF as RGMII, enable RGMII TXC clock */
  	clrsetbits_le32(&gpr->gpr[1],
  			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
  	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
  
  	return set_clk_eqos(ENET_125MHZ);
  }
  #endif
  
  #if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS)
  int board_phy_config(struct phy_device *phydev)
  {
  	if (phydev->drv->config)
  		phydev->drv->config(phydev);
  	return 0;
  }
  #endif
  
  /*USB Enable Over-Current Pin Setting*/
  static iomux_v3_cfg_t const usb_en_oc_pads[] = {
  	MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
  	MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
  };
  
  static void setup_iomux_usb_en_oc(void)
  {
  	imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads,
  					ARRAY_SIZE(usb_en_oc_pads));
  
  	gpio_request(IMX_GPIO_NR(1, 12), "usb0_en");
  	gpio_direction_output(IMX_GPIO_NR(1, 12), 1);
  	gpio_request(IMX_GPIO_NR(1, 13), "usb0_oc#");
  	gpio_direction_input(IMX_GPIO_NR(1, 13));
  }
  
  #ifdef CONFIG_USB_TCPC
  struct tcpc_port port1;
  struct tcpc_port port2;
  
  static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
  {
  	struct udevice *bus;
  	struct udevice *i2c_dev = NULL;
  	int ret;
  	uint8_t valb;
  
  	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
  	if (ret) {
  		printf("%s: Can't find bus
  ", __func__);
  		return -EINVAL;
  	}
  
  	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
  	if (ret) {
  		printf("%s: Can't find device id=0x%x
  ",
  			__func__, addr);
  		return -ENODEV;
  	}
  
  	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
  	if (ret) {
  		printf("%s dm_i2c_read failed, err %d
  ", __func__, ret);
  		return -EIO;
  	}
  	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
  	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
  	if (ret) {
  		printf("%s dm_i2c_write failed, err %d
  ", __func__, ret);
  		return -EIO;
  	}
  
  	/* Set OVP threshold to 23V */
  	valb = 0x6;
  	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
  	if (ret) {
  		printf("%s dm_i2c_write failed, err %d
  ", __func__, ret);
  		return -EIO;
  	}
  
  	return 0;
  }
  
  int pd_switch_snk_enable(struct tcpc_port *port)
  {
  	if (port == &port1) {
  		debug("Setup pd switch on port 1
  ");
  		return setup_pd_switch(1, 0x72);
  	} else
  		return -EINVAL;
  }
  
  /* Port2 is the power supply, port 1 does not support power */
  struct tcpc_port_config port1_config = {
  	.i2c_bus = 1, /*i2c2*/
  	.addr = 0x50,
  	.port_type = TYPEC_PORT_UFP,
  	.max_snk_mv = 20000,
  	.max_snk_ma = 3000,
  	.max_snk_mw = 45000,
  	.op_snk_mv = 15000,
  	.switch_setup_func = &pd_switch_snk_enable,
  	.disable_pd = true,
  };
  
  struct tcpc_port_config port2_config = {
  	.i2c_bus = 2, /*i2c3*/
  	.addr = 0x50,
  	.port_type = TYPEC_PORT_UFP,
  	.max_snk_mv = 20000,
  	.max_snk_ma = 3000,
  	.max_snk_mw = 45000,
  	.op_snk_mv = 15000,
  };
  
  #define USB_TYPEC_SEL IMX_GPIO_NR(4, 20)
  #define USB_TYPEC_EN IMX_GPIO_NR(2, 20)
  
  static iomux_v3_cfg_t ss_mux_gpio[] = {
  	MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  void ss_mux_select(enum typec_cc_polarity pol)
  {
  	if (pol == TYPEC_POLARITY_CC1)
  		gpio_direction_output(USB_TYPEC_SEL, 0);
  	else
  		gpio_direction_output(USB_TYPEC_SEL, 1);
  }
  
  static int setup_typec(void)
  {
  	int ret;
  	struct gpio_desc per_12v_desc;
  
  	debug("tcpc_init port 2
  ");
  	ret = tcpc_init(&port2, port2_config, NULL);
  	if (ret) {
  		printf("%s: tcpc port2 init failed, err=%d
  ",
  		       __func__, ret);
  	} else if (tcpc_pd_sink_check_charging(&port2)) {
  		printf("Power supply on USB2
  ");
  
  		/* Enable PER 12V, any check before it? */
  		ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc);
  		if (ret) {
  			printf("%s lookup gpio@20_1 failed ret = %d
  ", __func__, ret);
  			return -ENODEV;
  		}
  
  		ret = dm_gpio_request(&per_12v_desc, "per_12v_en");
  		if (ret) {
  			printf("%s request per_12v failed ret = %d
  ", __func__, ret);
  			return -EIO;
  		}
  
  		/* Enable PER 12V regulator */
  		dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  	}
  
  	debug("tcpc_init port 1
  ");
  	imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
  	gpio_request(USB_TYPEC_SEL, "typec_sel");
  	gpio_request(USB_TYPEC_EN, "typec_en");
  	gpio_direction_output(USB_TYPEC_EN, 0);
  
  	ret = tcpc_init(&port1, port1_config, &ss_mux_select);
  	if (ret) {
  		printf("%s: tcpc port1 init failed, err=%d
  ",
  		       __func__, ret);
  	} else {
  		return ret;
  	}
  
  	return ret;
  }
  #endif
  
  #ifdef CONFIG_USB_DWC3
  
  #define USB_PHY_CTRL0			0xF0040
  #define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
  
  #define USB_PHY_CTRL1			0xF0044
  #define USB_PHY_CTRL1_RESET		BIT(0)
  #define USB_PHY_CTRL1_COMMONONN		BIT(1)
  #define USB_PHY_CTRL1_ATERESET		BIT(3)
  #define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
  #define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
  
  #define USB_PHY_CTRL2			0xF0048
  #define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
  
  #define USB_PHY_CTRL6			0xF0058
  
  #define HSIO_GPR_BASE                               (0x32F10000U)
  #define HSIO_GPR_REG_0                              (HSIO_GPR_BASE)
  #define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT    (1)
  #define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN          (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT)
  
  
  static struct dwc3_device dwc3_device_data = {
  #ifdef CONFIG_SPL_BUILD
  	.maximum_speed = USB_SPEED_HIGH,
  #else
  	.maximum_speed = USB_SPEED_SUPER,
  #endif
  	.base = USB1_BASE_ADDR,
  	.dr_mode = USB_DR_MODE_PERIPHERAL,
  	.index = 0,
  	.power_down_scale = 2,
  };
  
  int usb_gadget_handle_interrupts(void)
  {
  	dwc3_uboot_handle_interrupt(0);
  	return 0;
  }
  
  static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
  {
  	u32 RegData;
  
  	/* enable usb clock via hsio gpr */
  	RegData = readl(HSIO_GPR_REG_0);
  	RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN;
  	writel(RegData, HSIO_GPR_REG_0);
  
  	/* USB3.0 PHY signal fsel for 100M ref */
  	RegData = readl(dwc3->base + USB_PHY_CTRL0);
  	RegData = (RegData & 0xfffff81f) | (0x2a<<5);
  	writel(RegData, dwc3->base + USB_PHY_CTRL0);
  
  	RegData = readl(dwc3->base + USB_PHY_CTRL6);
  	RegData &=~0x1;
  	writel(RegData, dwc3->base + USB_PHY_CTRL6);
  
  	RegData = readl(dwc3->base + USB_PHY_CTRL1);
  	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
  			USB_PHY_CTRL1_COMMONONN);
  	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
  	writel(RegData, dwc3->base + USB_PHY_CTRL1);
  
  	RegData = readl(dwc3->base + USB_PHY_CTRL0);
  	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
  	writel(RegData, dwc3->base + USB_PHY_CTRL0);
  
  	RegData = readl(dwc3->base + USB_PHY_CTRL2);
  	RegData |= USB_PHY_CTRL2_TXENABLEN0;
  	writel(RegData, dwc3->base + USB_PHY_CTRL2);
  
  	RegData = readl(dwc3->base + USB_PHY_CTRL1);
  	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
  	writel(RegData, dwc3->base + USB_PHY_CTRL1);
  }
  #endif
  
  #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
  #define USB2_PWR_EN IMX_GPIO_NR(1, 14)
  int board_usb_init(int index, enum usb_init_type init)
  {
  	int ret = 0;
  	imx8m_usb_power(index, true);
  
  	if (index == 0 && init == USB_INIT_DEVICE) {
  #ifdef CONFIG_USB_TCPC
  		ret = tcpc_setup_ufp_mode(&port1);
  		if (ret)
  			return ret;
  #endif
  		dwc3_nxp_usb_phy_init(&dwc3_device_data);
  		return dwc3_uboot_init(&dwc3_device_data);
  	} else if (index == 0 && init == USB_INIT_HOST) {
  #ifdef CONFIG_USB_TCPC
  		ret = tcpc_setup_dfp_mode(&port1);
  #endif
  		return ret;
  	} else if (index == 1 && init == USB_INIT_HOST) {
  		/* Enable GPIO1_IO14 for 5V VBUS */
  		gpio_request(USB2_PWR_EN, "usb2_pwr");
  		gpio_direction_output(USB2_PWR_EN, 1);
  	}
  
  	return 0;
  }
  
  int board_usb_cleanup(int index, enum usb_init_type init)
  {
  	int ret = 0;
  	if (index == 0 && init == USB_INIT_DEVICE) {
  		dwc3_uboot_exit(index);
  	} else if (index == 0 && init == USB_INIT_HOST) {
  #ifdef CONFIG_USB_TCPC
  		ret = tcpc_disable_src_vbus(&port1);
  #endif
  	} else if (index == 1 && init == USB_INIT_HOST) {
  		/* Disable GPIO1_IO14 for 5V VBUS */
  		gpio_direction_output(USB2_PWR_EN, 0);
  	}
  
  	imx8m_usb_power(index, false);
  
  	return ret;
  }
  
  #ifdef CONFIG_USB_TCPC
  /* Not used so far */
  int board_typec_get_mode(int index)
  {
  	int ret = 0;
  	enum typec_cc_polarity pol;
  	enum typec_cc_state state;
  
  	if (index == 0) {
  		tcpc_setup_ufp_mode(&port1);
  
  		ret = tcpc_get_cc_status(&port1, &pol, &state);
  		if (!ret) {
  			if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
  				return USB_INIT_HOST;
  		}
  
  		return USB_INIT_DEVICE;
  	} else {
  		return USB_INIT_HOST;
  	}
  }
  #endif
  #endif
  
  #define FSL_SIP_GPC			0xC2000000
  #define FSL_SIP_CONFIG_GPC_PM_DOMAIN	0x3
  #define DISPMIX				13
  #define MIPI				15
  
  int board_init(void)
  {
  	setup_iomux_misc();
  	setup_iomux_gpio();
  	setup_iomux_usb_en_oc();
  #ifdef CONFIG_USB_TCPC
  	setup_typec();
  #endif
  
  #ifdef CONFIG_FEC_MXC
  	setup_fec();
  #endif
  
  #ifdef CONFIG_DWC_ETH_QOS
  	/* clock, pin, gpr */
  	setup_eqos();
  #endif
  
  #ifdef CONFIG_NAND_MXS
  	setup_gpmi_nand();
  #endif
  
  #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
  	init_usb_clk();
  #endif
  
  	/* enable the dispmix & mipi phy power domain */
  	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
  	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
  
  	return 0;
  }
  
  int board_late_init(void)
  {
  	/* Read Module Information from on module EEPROM and pass
  	 * mac address to kernel
  	*/
  	struct udevice *dev;
  	int ret;
  	u8 name[8];
  	u8 serial[12];
  	u8 revision[4];
  	u8 mac[6];
  	u8 mac1[6];
  
  	ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev);
  	if (ret) {
  		debug("failed to get eeprom
  ");
  		return 0;
  	}
  
  	/* Board ID */
  	ret = dm_i2c_read(dev, 0x4, name, 8);
  	if (ret) {
  		debug("failed to read board ID from EEPROM
  ");
  		return 0;
  	}
  	puts("---------Embedian SMARC-iMX8MP------------
  ");
  	printf("  Board ID:             %c%c%c%c%c%c%c%c
  ",
  		name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]);
  
  	/* Board Hardware Revision */
  	ret = dm_i2c_read(dev, 0xc, revision, 4);
  	if (ret) {
  		debug("failed to read hardware revison from EEPROM
  ");
  		return 0;
  	}
  	printf("  Hardware Revision:    %c%c%c%c
  ",
  		revision[0], revision[1], revision[2], revision[3]);
  
  	/* Serial number */
  	ret = dm_i2c_read(dev, 0x10, serial, 12);
  	if (ret) {
  		debug("failed to read srial number from EEPROM
  ");
  		return 0;
  	}
  	printf("  Serial Number#:       %c%c%c%c%c%c%c%c%c%c%c%c
  ",
  		serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]);
  
  	/*MAC address */
  	ret = dm_i2c_read(dev, 0x3c, mac, 6);
  	if (ret) {
  		debug("failed to read eth0 mac address from EEPROM
  ");
  		return 0;
  	}
  
  	if (is_valid_ethaddr(mac))
  	printf("  MAC Address:          %02x:%02x:%02x:%02x:%02x:%02x
  ",
  		mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  		eth_env_set_enetaddr("ethaddr", mac);
  
  	/* MAC2 address */
  	ret = dm_i2c_read(dev, 0x42, mac1, 6);
  	if (ret) {
  		debug("failed to read eth1 mac address from EEPROM
  ");
  		return 0;
  	}
  
  	if (is_valid_ethaddr(mac1))
  	printf("  MAC1 Address:         %02x:%02x:%02x:%02x:%02x:%02x
  ",
  		mac1[0], mac1[1], mac1[2], mac1[3], mac1[4], mac1[5]);
  		eth_env_set_enetaddr("eth1addr", mac1);
  	puts("-----------------------------------------
  ");
  
  #ifdef CONFIG_ENV_IS_IN_MMC
  	board_late_mmc_env_init();
  #endif
  #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  	env_set("board_name", "SMARC");
  	env_set("board_rev", "iMX8MP");
  #endif
  
  	if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
  		puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...
  ");
  		hang();
  	} else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
  		puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...
  ");
  		env_set_ulong("usb dev", 1);
  		env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;");
  	} else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
  		puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...
  ");
  		hang();
  	} else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
  		puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...
  ");
  		env_set_ulong("mmcdev", 1);

  		env_set("bootcmd", "i2c dev 0; i2c mw 0x25 0x0a 0x3; mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");

  	} else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
  		puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...
  ");
  		env_set_ulong("mmcdev", 2);

  		env_set("bootcmd", "i2c dev 0; i2c mw 0x25 0x0a 0x3; mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");

  	} else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
  		puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...
  ");
  		env_set("bootcmd", "run netboot;");
  	} else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
  		puts("Carrier SPI Boot is not supported...
  ");
  		hang();
  	} else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
  		puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...
  ");
  		hang();
  	} else {
  		puts("unsupported boot devices
  ");
  		hang();
  	}
  
  	return 0;
  }
  
  #ifdef CONFIG_IMX_BOOTAUX
  ulong board_get_usable_ram_top(ulong total_size)
  {
  	/* Reserve 16M memory used by M core vring/buffer, which begins at 16MB before optee */
  	if (rom_pointer[1])
  		return gd->ram_top - SZ_16M;
  
  	return gd->ram_top;
  }
  #endif
  
  #ifdef CONFIG_FSL_FASTBOOT
  #ifdef CONFIG_ANDROID_RECOVERY
  
  int is_recovery_key_pressing(void)
  {
  	return 0; /*TODO*/
  }
  #endif /*CONFIG_ANDROID_RECOVERY*/
  #endif /*CONFIG_FSL_FASTBOOT*/
  
  #ifdef CONFIG_ANDROID_SUPPORT
  bool is_power_key_pressed(void) {
  	return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
  }
  #endif
  
  #ifdef CONFIG_SPL_MMC_SUPPORT
  
  #define UBOOT_RAW_SECTOR_OFFSET 0x40
  unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
  {
  	u32 boot_dev = spl_boot_device();
  	switch (boot_dev) {
  		case BOOT_DEVICE_MMC2:
  			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
  		default:
  			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
  	}
  }
  #endif