// SPDX-License-Identifier: GPL-2.0+

  /*
   * Copyright (C) 2015 Freescale Semiconductor, Inc.

   */

  #include <init.h>

  #include <asm/arch/clock.h>
  #include <asm/arch/imx-regs.h>
  #include <asm/arch/mx7-pins.h>
  #include <asm/arch/sys_proto.h>
  #include <asm/gpio.h>

  #include <asm/mach-imx/iomux-v3.h>

  #include <asm/io.h>
  #include <linux/sizes.h>
  #include <common.h>

  #include <fsl_esdhc_imx.h>

  #include <mmc.h>
  #include <miiphy.h>

  #include <power/pmic.h>
  #include <power/pfuze3000_pmic.h>
  #include "../common/pfuze.h"
  #include <i2c.h>

  #include <asm/mach-imx/mxc_i2c.h>

  #include <asm/arch/crm_regs.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
  #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)

  #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  	PAD_CTL_DSE_3P3V_49OHM)

  #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)

  #define SPI_PAD_CTRL \
    (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)

  #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)

  #ifdef CONFIG_MXC_SPI

  static iomux_v3_cfg_t const ecspi3_pads[] = {
      MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
      MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
      MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
      MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  int board_spi_cs_gpio(unsigned bus, unsigned cs)
  {
           return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
  }
  
  static void setup_spi(void)
  {
           imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
  }

  #endif

  int dram_init(void)
  {
  	gd->ram_size = PHYS_SDRAM_SIZE;
  
  	return 0;
  }
  
  static iomux_v3_cfg_t const wdog_pads[] = {
  	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static iomux_v3_cfg_t const uart1_pads[] = {
  	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };

  #ifdef CONFIG_NAND_MXS
  static iomux_v3_cfg_t const gpmi_pads[] = {
  	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_CLK__NAND_CLE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_CMD__NAND_ALE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_STROBE__NAND_RE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SD3_RESET_B__NAND_WE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SAI1_MCLK__NAND_WP_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SAI1_TX_SYNC__NAND_DQS	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  };
  
  static void setup_gpmi_nand(void)
  {
  	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  
  	/* NAND_USDHC_BUS_CLK is set in rom */
  	set_clk_nand();
  }
  #endif

  #ifdef CONFIG_VIDEO_MXS
  static iomux_v3_cfg_t const lcd_pads[] = {
  	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  
  	MX7D_PAD_LCD_RESET__GPIO3_IO4	| MUX_PAD_CTRL(LCD_PAD_CTRL),
  };
  
  static iomux_v3_cfg_t const pwm_pads[] = {
  	/* Use GPIO for Brightness adjustment, duty cycle = period */
  	MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static int setup_lcd(void)
  {
  	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  
  	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
  
  	/* Reset LCD */

  	gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");

  	gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
  	udelay(500);
  	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
  
  	/* Set Brightness to high */

  	gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");

  	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
  
  	return 0;
  }
  #endif

  static void setup_iomux_uart(void)
  {
  	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  }

  int board_mmc_get_env_dev(int devno)

  {

  	if (devno == 2)
  		devno--;

  	return devno;

  }

  int mmc_map_to_kernel_blk(int dev_no)

  {
  	if (dev_no == 1)
  		dev_no++;
  
  	return dev_no;
  }

  #ifdef CONFIG_FEC_MXC

  static int setup_fec(void)
  {
  	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  
  	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
  	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  		(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
  		 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);

  	return set_clk_enet(ENET_125MHZ);

  }

  int board_phy_config(struct phy_device *phydev)
  {
  	/* enable rgmii rxc skew and phy mode select to RGMII copper */
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
  
  	if (phydev->drv->config)
  		phydev->drv->config(phydev);
  	return 0;
  }
  #endif

  #ifdef CONFIG_FSL_QSPI

  int board_qspi_init(void)
  {

  	/* Set the clock */
  	set_clk_qspi();
  
  	return 0;
  }
  #endif

  int board_early_init_f(void)
  {
  	setup_iomux_uart();

  	return 0;
  }
  
  int board_init(void)
  {
  	/* address of boot parameters */
  	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

  #ifdef CONFIG_FEC_MXC
  	setup_fec();
  #endif

  #ifdef CONFIG_NAND_MXS
  	setup_gpmi_nand();
  #endif

  #ifdef CONFIG_VIDEO_MXS
  	setup_lcd();
  #endif

  #ifdef CONFIG_FSL_QSPI
  	board_qspi_init();
  #endif

  #ifdef CONFIG_MXC_SPI
         setup_spi();
  #endif

  	return 0;
  }

  #ifdef CONFIG_DM_PMIC

  int power_init_board(void)
  {

  	struct udevice *dev;
  	int ret, dev_id, rev_id;

  	ret = pmic_get("pfuze3000@8", &dev);

  	if (ret == -ENODEV)
  		return 0;
  	if (ret != 0)

  		return ret;

  	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x
  ", dev_id, rev_id);

  	pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);

  	/*
  	 * Set the voltage of VLDO4 output to 2.8V which feeds
  	 * the MIPI DSI and MIPI CSI inputs.
  	 */
  	pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);

  	return 0;
  }
  #endif
  
  int board_late_init(void)
  {

  	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

  	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

  	set_wdog_reset(wdog);
  
  	/*
  	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
  	 * since we use PMIC_PWRON to reset the board.
  	 */
  	clrsetbits_le16(&wdog->wcr, 0, 0x10);

  
  	return 0;
  }

  int checkboard(void)
  {

  	char *mode;
  
  	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
  		mode = "secure";
  	else
  		mode = "non-secure";
  
  	printf("Board: i.MX7D SABRESD in %s mode
  ", mode);

  
  	return 0;
  }