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board/embedian/smarcimx8mm/spl.c
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/* * Copyright 2018-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <spl.h> #include <asm/io.h> #include <errno.h> #include <asm/io.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/arch/imx8mm_pins.h> #include <asm/arch/sys_proto.h> #include <power/pmic.h> #include <power/bd71837.h> #include <asm/arch/clock.h> #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/mxc_i2c.h> #include <fsl_esdhc.h> #include <mmc.h> #include <asm/arch/imx8m_ddr.h> DECLARE_GLOBAL_DATA_PTR; void spl_dram_init(void) { ddr_init(&dram_timing); } #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, .gp = IMX_GPIO_NR(5, 14), }, .sda = { .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, .gp = IMX_GPIO_NR(5, 15), }, }; #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) |
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) |
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#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ PAD_CTL_FSEL2) #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) static iomux_v3_cfg_t const usdhc1_pads[] = { IMX8MM_PAD_SD1_CLK_USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_CMD_USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc2_pads[] = { IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), }; static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC1_BASE_ADDR, 0, 8}, {USDHC2_BASE_ADDR, 0, 4}, }; int board_mmc_init(bd_t *bis) { int i, ret; /* * According to the board_mmc_init() the following map is done: * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
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gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); |
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gpio_direction_output(USDHC1_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC1_PWR_GPIO, 1); break; case 1: usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); gpio_direction_output(USDHC2_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC2_PWR_GPIO, 1); break; default: printf("Warning: you configured more USDHC controllers" "(%d) than supported by the board ", i + 1); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) return ret; } return 0; } int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; switch (cfg->esdhc_base) { |
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case USDHC1_BASE_ADDR: |
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ret = 1; break; case USDHC2_BASE_ADDR: gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); gpio_direction_input(USDHC2_CD_GPIO); ret = !gpio_get_value(USDHC2_CD_GPIO); return ret; } return 1; } /* RESET_OUT */ static iomux_v3_cfg_t const reset_out_pads[] = { IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), }; static void setup_iomux_reset_out(void) { imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); /* Set CPU RESET_OUT as Output */ gpio_request(IMX_GPIO_NR(3, 12), "CPU_RESET"); gpio_direction_output(IMX_GPIO_NR(3, 12) , 0); } #ifdef CONFIG_POWER #define I2C_PMIC 0 int power_init_board(void) { struct pmic *p; int ret; ret = power_bd71837_init(I2C_PMIC); if (ret) printf("power init failed"); p = pmic_get("BD71837"); pmic_probe(p); /* decrease RESET key long push time from the default 10s to 10ms */ pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); /* unlock the PMIC regs */ pmic_reg_write(p, BD71837_REGLOCK, 0x1); /* increase VDD_SOC to typical value 0.85v before first DRAM access */ pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); #ifndef CONFIG_IMX8M_LPDDR4 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); #endif /* lock the PMIC regs */ pmic_reg_write(p, BD71837_REGLOCK, 0x11); return 0; } #endif void spl_board_init(void) { #ifndef CONFIG_SPL_USB_SDP_SUPPORT /* Serial download mode */ if (is_usb_boot()) { puts("Back to ROM, SDP "); restore_boot_params(); } #endif puts("Normal Boot "); setup_iomux_reset_out(); } #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { /* Just empty function now - can't decide what to choose */ debug("%s: %s ", __func__, name); return 0; } #endif void board_init_f(ulong dummy) { int ret; /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); arch_cpu_init(); board_early_init_f(); timer_init(); preloader_console_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); ret = spl_init(); if (ret) { debug("spl_init() failed: %d ", ret); hang(); } enable_tzc380(); /* Adjust pmic voltage to 1.0V for 800M */ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); power_init_board(); /* DDR initialization */ spl_dram_init(); board_init_r(NULL, 0); } |