menu "MIPS architecture"
  	depends on MIPS
  
  config SYS_ARCH
  	default "mips"
  
  config SYS_CPU
  	default "mips32" if CPU_MIPS32
  	default "mips64" if CPU_MIPS64
  
  choice
  	prompt "Target select"
  	optional
  
  config TARGET_QEMU_MIPS
  	bool "Support qemu-mips"
  	select SUPPORTS_BIG_ENDIAN
  	select SUPPORTS_LITTLE_ENDIAN
  	select SUPPORTS_CPU_MIPS32_R1
  	select SUPPORTS_CPU_MIPS32_R2
  	select SUPPORTS_CPU_MIPS64_R1
  	select SUPPORTS_CPU_MIPS64_R2
  	select ROM_EXCEPTION_VECTORS
  
  config TARGET_MALTA
  	bool "Support malta"
  	select DM
  	select DM_SERIAL
  	select DYNAMIC_IO_PORT_BASE
  	select MIPS_CM
  	select MIPS_L2_CACHE
  	select OF_CONTROL
  	select OF_ISA_BUS
  	select SUPPORTS_BIG_ENDIAN
  	select SUPPORTS_LITTLE_ENDIAN
  	select SUPPORTS_CPU_MIPS32_R1
  	select SUPPORTS_CPU_MIPS32_R2
  	select SUPPORTS_CPU_MIPS32_R6
  	select SUPPORTS_CPU_MIPS64_R1
  	select SUPPORTS_CPU_MIPS64_R2
  	select SUPPORTS_CPU_MIPS64_R6
  	select SWAP_IO_SPACE
  	select MIPS_L1_CACHE_SHIFT_6
  	select ROM_EXCEPTION_VECTORS
  
  config TARGET_VCT
  	bool "Support vct"
  	select SUPPORTS_BIG_ENDIAN
  	select SUPPORTS_CPU_MIPS32_R1
  	select SUPPORTS_CPU_MIPS32_R2
  	select SYS_MIPS_CACHE_INIT_RAM_LOAD
  	select ROM_EXCEPTION_VECTORS
  
  config TARGET_DBAU1X00
  	bool "Support dbau1x00"
  	select SUPPORTS_BIG_ENDIAN
  	select SUPPORTS_LITTLE_ENDIAN
  	select SUPPORTS_CPU_MIPS32_R1
  	select SUPPORTS_CPU_MIPS32_R2
  	select SYS_MIPS_CACHE_INIT_RAM_LOAD
  	select ROM_EXCEPTION_VECTORS
  	select MIPS_TUNE_4KC
  
  config TARGET_PB1X00
  	bool "Support pb1x00"
  	select SUPPORTS_LITTLE_ENDIAN
  	select SUPPORTS_CPU_MIPS32_R1
  	select SUPPORTS_CPU_MIPS32_R2
  	select SYS_MIPS_CACHE_INIT_RAM_LOAD
  	select ROM_EXCEPTION_VECTORS
  	select MIPS_TUNE_4KC
  
  config ARCH_ATH79
  	bool "Support QCA/Atheros ath79"
  	select OF_CONTROL
  	select DM
  
  config ARCH_BMIPS
  	bool "Support BMIPS SoCs"
  	select OF_CONTROL
  	select DM
  	select CLK
  	select CPU
  	select RAM
  	select SYSRESET
  
  config MACH_PIC32
  	bool "Support Microchip PIC32"
  	select OF_CONTROL
  	select DM
  
  config TARGET_BOSTON
  	bool "Support Boston"
  	select DM
  	select DM_SERIAL
  	select OF_CONTROL
  	select MIPS_CM
  	select MIPS_L1_CACHE_SHIFT_6
  	select MIPS_L2_CACHE
  	select OF_BOARD_SETUP
  	select SUPPORTS_BIG_ENDIAN
  	select SUPPORTS_LITTLE_ENDIAN
  	select SUPPORTS_CPU_MIPS32_R1
  	select SUPPORTS_CPU_MIPS32_R2
  	select SUPPORTS_CPU_MIPS32_R6
  	select SUPPORTS_CPU_MIPS64_R1
  	select SUPPORTS_CPU_MIPS64_R2
  	select SUPPORTS_CPU_MIPS64_R6
  	select ROM_EXCEPTION_VECTORS
  
  config TARGET_XILFPGA
  	bool "Support Imagination Xilfpga"
  	select OF_CONTROL
  	select DM
  	select DM_SERIAL
  	select DM_GPIO
  	select DM_ETH
  	select SUPPORTS_LITTLE_ENDIAN
  	select SUPPORTS_CPU_MIPS32_R1
  	select SUPPORTS_CPU_MIPS32_R2
  	select MIPS_L1_CACHE_SHIFT_4
  	select ROM_EXCEPTION_VECTORS
  	help
  	  This supports IMGTEC MIPSfpga platform
  
  endchoice
  
  source "board/dbau1x00/Kconfig"
  source "board/imgtec/boston/Kconfig"
  source "board/imgtec/malta/Kconfig"
  source "board/imgtec/xilfpga/Kconfig"
  source "board/micronas/vct/Kconfig"
  source "board/pb1x00/Kconfig"
  source "board/qemu-mips/Kconfig"
  source "arch/mips/mach-ath79/Kconfig"
  source "arch/mips/mach-bmips/Kconfig"
  source "arch/mips/mach-pic32/Kconfig"
  
  if MIPS
  
  choice
  	prompt "Endianness selection"
  	help
  	  Some MIPS boards can be configured for either little or big endian
  	  byte order. These modes require different U-Boot images. In general there
  	  is one preferred byteorder for a particular system but some systems are
  	  just as commonly used in the one or the other endianness.
  
  config SYS_BIG_ENDIAN
  	bool "Big endian"
  	depends on SUPPORTS_BIG_ENDIAN
  
  config SYS_LITTLE_ENDIAN
  	bool "Little endian"
  	depends on SUPPORTS_LITTLE_ENDIAN
  
  endchoice
  
  choice
  	prompt "CPU selection"
  	default CPU_MIPS32_R2
  
  config CPU_MIPS32_R1
  	bool "MIPS32 Release 1"
  	depends on SUPPORTS_CPU_MIPS32_R1
  	select 32BIT
  	help
  	  Choose this option to build an U-Boot for release 1 through 5 of the
  	  MIPS32 architecture.
  
  config CPU_MIPS32_R2
  	bool "MIPS32 Release 2"
  	depends on SUPPORTS_CPU_MIPS32_R2
  	select 32BIT
  	help
  	  Choose this option to build an U-Boot for release 2 through 5 of the
  	  MIPS32 architecture.
  
  config CPU_MIPS32_R6
  	bool "MIPS32 Release 6"
  	depends on SUPPORTS_CPU_MIPS32_R6
  	select 32BIT
  	help
  	  Choose this option to build an U-Boot for release 6 or later of the
  	  MIPS32 architecture.
  
  config CPU_MIPS64_R1
  	bool "MIPS64 Release 1"
  	depends on SUPPORTS_CPU_MIPS64_R1
  	select 64BIT
  	help
  	  Choose this option to build a kernel for release 1 through 5 of the
  	  MIPS64 architecture.
  
  config CPU_MIPS64_R2
  	bool "MIPS64 Release 2"
  	depends on SUPPORTS_CPU_MIPS64_R2
  	select 64BIT
  	help
  	  Choose this option to build a kernel for release 2 through 5 of the
  	  MIPS64 architecture.
  
  config CPU_MIPS64_R6
  	bool "MIPS64 Release 6"
  	depends on SUPPORTS_CPU_MIPS64_R6
  	select 64BIT
  	help
  	  Choose this option to build a kernel for release 6 or later of the
  	  MIPS64 architecture.
  
  endchoice
  
  menu "General setup"
  
  config ROM_EXCEPTION_VECTORS
  	bool "Build U-Boot image with exception vectors"
  	help
  	  Enable this to include exception vectors in the U-Boot image. This is
  	  required if the U-Boot entry point is equal to the address of the
  	  CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
  	  U-Boot booted from parallel NOR flash).
  	  Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
  	  In that case the image size will be reduced by 0x500 bytes.
  
  config MIPS_CM_BASE
  	hex "MIPS CM GCR Base Address"
  	depends on MIPS_CM
  	default 0x16100000 if TARGET_BOSTON
  	default 0x1fbf8000
  	help
  	  The physical base address at which to map the MIPS Coherence Manager
  	  Global Configuration Registers (GCRs). This should be set such that
  	  the GCRs occupy a region of the physical address space which is
  	  otherwise unused, or at minimum that software doesn't need to access.
  
  endmenu
  
  menu "OS boot interface"
  
  config MIPS_BOOT_CMDLINE_LEGACY
  	bool "Hand over legacy command line to Linux kernel"
  	default y
  	help
  	  Enable this option if you want U-Boot to hand over the Yamon-style
  	  command line to the kernel. All bootargs will be prepared as argc/argv
  	  compatible list. The argument count (argc) is stored in register $a0.
  	  The address of the argument list (argv) is stored in register $a1.
  
  config MIPS_BOOT_ENV_LEGACY
  	bool "Hand over legacy environment to Linux kernel"
  	default y
  	help
  	  Enable this option if you want U-Boot to hand over the Yamon-style
  	  environment to the kernel. Information like memory size, initrd
  	  address and size will be prepared as zero-terminated key/value list.
  	  The address of the environment is stored in register $a2.
  
  config MIPS_BOOT_FDT
  	bool "Hand over a flattened device tree to Linux kernel"
  	default n
  	help
  	  Enable this option if you want U-Boot to hand over a flattened
  	  device tree to the kernel. According to UHI register $a0 will be set
  	  to -2 and the FDT address is stored in $a1.
  
  endmenu
  
  config SUPPORTS_BIG_ENDIAN
  	bool
  
  config SUPPORTS_LITTLE_ENDIAN
  	bool
  
  config SUPPORTS_CPU_MIPS32_R1
  	bool
  
  config SUPPORTS_CPU_MIPS32_R2
  	bool
  
  config SUPPORTS_CPU_MIPS32_R6
  	bool
  
  config SUPPORTS_CPU_MIPS64_R1
  	bool
  
  config SUPPORTS_CPU_MIPS64_R2
  	bool
  
  config SUPPORTS_CPU_MIPS64_R6
  	bool
  
  config CPU_MIPS32
  	bool
  	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
  
  config CPU_MIPS64
  	bool
  	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
  
  config MIPS_TUNE_4KC
  	bool
  
  config MIPS_TUNE_14KC
  	bool
  
  config MIPS_TUNE_24KC
  	bool
  
  config MIPS_TUNE_34KC
  	bool
  
  config MIPS_TUNE_74KC
  	bool
  
  config 32BIT
  	bool
  
  config 64BIT
  	bool
  
  config SWAP_IO_SPACE
  	bool
  
  config SYS_MIPS_CACHE_INIT_RAM_LOAD
  	bool
  
  config MIPS_INIT_STACK_IN_SRAM
  	bool
  	default n
  	help
  	  Select this if the initial stack frame could be setup in SRAM.
  	  Normally the initial stack frame is set up in DRAM which is often
  	  only available after lowlevel_init. With this option the initial
  	  stack frame and the early C environment is set up before
  	  lowlevel_init. Thus lowlevel_init does not need to be implemented
  	  in assembler.
  
  config SYS_DCACHE_SIZE
  	int
  	default 0
  	help
  	  The total size of the L1 Dcache, if known at compile time.
  
  config SYS_DCACHE_LINE_SIZE
  	int
  	default 0
  	help
  	  The size of L1 Dcache lines, if known at compile time.
  
  config SYS_ICACHE_SIZE
  	int
  	default 0
  	help
  	  The total size of the L1 ICache, if known at compile time.
  
  config SYS_ICACHE_LINE_SIZE
  	int
  	default 0
  	help
  	  The size of L1 Icache lines, if known at compile time.
  
  config SYS_CACHE_SIZE_AUTO
  	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
  		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
  	help
  	  Select this (or let it be auto-selected by not defining any cache
  	  sizes) in order to allow U-Boot to automatically detect the sizes
  	  of caches at runtime. This has a small cost in code size & runtime
  	  so if you know the cache configuration for your system at compile
  	  time it would be beneficial to configure it.
  
  config MIPS_L1_CACHE_SHIFT_4
  	bool
  
  config MIPS_L1_CACHE_SHIFT_5
  	bool
  
  config MIPS_L1_CACHE_SHIFT_6
  	bool
  
  config MIPS_L1_CACHE_SHIFT_7
  	bool
  
  config MIPS_L1_CACHE_SHIFT
  	int
  	default "7" if MIPS_L1_CACHE_SHIFT_7
  	default "6" if MIPS_L1_CACHE_SHIFT_6
  	default "5" if MIPS_L1_CACHE_SHIFT_5
  	default "4" if MIPS_L1_CACHE_SHIFT_4
  	default "5"
  
  config MIPS_L2_CACHE
  	bool
  	help
  	  Select this if your system includes an L2 cache and you want U-Boot
  	  to initialise & maintain it.
  
  config DYNAMIC_IO_PORT_BASE
  	bool
  
  config MIPS_CM
  	bool
  	help
  	  Select this if your system contains a MIPS Coherence Manager and you
  	  wish U-Boot to configure it or make use of it to retrieve system
  	  information such as cache configuration.
  
  endif
  
  endmenu