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board/pb1x00/pb1x00.c
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/* * (C) Copyright 2003 * Thomas.Lange@corelatus.se * |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ #include <common.h> #include <command.h> |
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#include <mach/au1x00.h> |
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#include <asm/mipsregs.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int dram_init(void) |
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{ /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ |
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gd->ram_size = 64 * 1024 * 1024; return 0; |
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} #define BCSR_PCMCIA_PC0DRVEN 0x0010 #define BCSR_PCMCIA_PC0RST 0x0080 |
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/* In arch/mips/cpu/cpu.c */ |
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void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); int checkboard (void) { |
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#if defined(CONFIG_IDE_PCMCIA) && 0 |
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u16 status; |
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#endif |
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/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; u32 proc_id; *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ |
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proc_id = read_c0_prid(); |
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switch (proc_id >> 24) { case 0: puts ("Board: Pb1000 "); printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x ", (proc_id >> 8) & 0xFF, proc_id & 0xFF); break; case 1: puts ("Board: Pb1500 "); printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x ", (proc_id >> 8) & 0xFF, proc_id & 0xFF); break; case 2: puts ("Board: Pb1100 "); printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x ", (proc_id >> 8) & 0xFF, proc_id & 0xFF); break; default: printf ("Unsupported cpu %d, proc_id=0x%x ", proc_id >> 24, proc_id); } |
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set_io_port_base(0); |
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#if defined(CONFIG_IDE_PCMCIA) && 0 /* Enable 3.3 V on slot 0 ( VCC ) No 5V */ status = 4; *pcmcia_bcsr = status; status |= BCSR_PCMCIA_PC0DRVEN; *pcmcia_bcsr = status; au_sync(); udelay(300*1000); status |= BCSR_PCMCIA_PC0RST; *pcmcia_bcsr = status; au_sync(); udelay(100*1000); /* PCMCIA is on a 36 bit physical address. We need to map it into a 32 bit addresses */ #if 0 /* We dont need theese unless we run whole pcmcia package */ write_one_tlb(20, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ |
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CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ |
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0x3C000017, /* Lo0 */ 0x3C200017); /* Lo1 */ write_one_tlb(21, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ |
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CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ |
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0x3D000017, /* Lo0 */ 0x3D200017); /* Lo1 */ #endif /* 0 */ write_one_tlb(22, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ |
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CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ |
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0x3E000017, /* Lo0 */ 0x3E200017); /* Lo1 */ #endif /* CONFIG_IDE_PCMCIA */ return 0; } |