From 05922b0abf848949df778c19312cb1cf7fdfbe6a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 9 May 2016 17:31:34 +0800 Subject: [PATCH] MLK-12767 imx6ull: fix runtime checking for i.MX6ULL Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan --- arch/arm/cpu/armv7/mx6/clock.c | 27 +++++++++++++++++---------- arch/arm/cpu/armv7/mx6/soc.c | 19 +++++++++++-------- arch/arm/imx-common/init.c | 2 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 6 +++--- arch/arm/include/asm/arch-mx6/imx-regs.h | 4 ++-- 5 files changed, 34 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index e7a0f91..03d58fa 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -133,7 +133,7 @@ void enable_uart_clk(unsigned char enable) { u32 mask; - if (is_cpu_type(MXC_CPU_MX6UL)) + if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) mask = MXC_CCM_CCGR5_UART_MASK; else mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; @@ -184,7 +184,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) reg &= ~mask; __raw_writel(reg, &imx_ccm->CCGR2); } else { - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6ULL)) { mask = MXC_CCM_CCGR6_I2C4_MASK; addr = &imx_ccm->CCGR6; } else { @@ -295,7 +296,8 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) switch (pll) { case PLL_BUS: - if (!is_cpu_type(MXC_CPU_MX6UL)) { + if (!is_cpu_type(MXC_CPU_MX6UL) && + !is_cpu_type(MXC_CPU_MX6ULL)) { if (pfd_num == 3) { /* No PFD3 on PPL2 */ return 0; @@ -396,7 +398,8 @@ static u32 get_ipg_per_clk(void) reg = __raw_readl(&imx_ccm->cscmr1); if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || - is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { + is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6ULL)) { if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) return MXC_HCLK; /* OSC 24Mhz */ } @@ -413,7 +416,8 @@ static u32 get_uart_clk(void) reg = __raw_readl(&imx_ccm->cscdr1); if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || - is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { + is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6ULL)) { if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) freq = MXC_HCLK; } @@ -433,7 +437,8 @@ static u32 get_cspi_clk(void) MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) || - is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { + is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6ULL)) { if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) return MXC_HCLK / (cspi_podf + 1); } @@ -496,7 +501,7 @@ static u32 get_mmdc_ch0_clk(void) u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || - is_cpu_type(MXC_CPU_MX6SL)) { + is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6ULL)) { podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { @@ -634,7 +639,8 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) debug("mxs_set_lcdclk, freq = %dKHz\n", freq); - if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) { + if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL) && + !is_cpu_type(MXC_CPU_MX6ULL)) { debug("This chip not support lcd!\n"); return; } @@ -768,7 +774,7 @@ int enable_lcdif_clock(u32 base_addr) MXC_CCM_CCGR3_DISP_AXI_MASK) : (MXC_CCM_CCGR3_LCDIF1_PIX_MASK | MXC_CCM_CCGR3_DISP_AXI_MASK); - } else if (is_cpu_type(MXC_CPU_MX6UL)) { + } else if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) { if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; @@ -938,7 +944,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) } else if (fec_id == 1) { /* Only i.MX6SX/UL support ENET2 */ if (!(is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX6UL))) + is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6ULL))) return -EINVAL; reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 1eae50b..d54b581 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -130,7 +130,7 @@ u32 get_cpu_speed_grade_hz(void) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; - if (is_cpu_type(MXC_CPU_MX6UL)) { + if (is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) { if (val == OCOTP_CFG3_SPEED_528MHZ) return 528000000; else if (val == OCOTP_CFG3_SPEED_696MHZ) @@ -302,7 +302,8 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6ULL)) reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); else reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); @@ -446,8 +447,8 @@ static void imx_set_pcie_phy_power_down(void) int arch_cpu_init(void) { - if (!is_cpu_type(MXC_CPU_MX6SL) && !!is_cpu_type(MXC_CPU_MX6SX) - && !is_cpu_type(MXC_CPU_MX6UL)) { + if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6SX) + && !is_cpu_type(MXC_CPU_MX6UL) && !is_cpu_type(MXC_CPU_MX6ULL)) { /* * imx6sl doesn't have pcie at all. * this bit is not used by imx6sx anymore @@ -534,10 +535,12 @@ int arch_cpu_init(void) imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ - if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6UL)) + if (!is_cpu_type(MXC_CPU_MX6SL) && !is_cpu_type(MXC_CPU_MX6UL) && + !is_cpu_type(MXC_CPU_MX6ULL)) imx_set_pcie_phy_power_down(); - if (!is_mx6dqp() && !is_cpu_type(MXC_CPU_MX6UL)) + if (!is_mx6dqp() && !is_cpu_type(MXC_CPU_MX6UL) && + !is_cpu_type(MXC_CPU_MX6ULL)) imx_set_vddpu_power_down(); #ifdef CONFIG_APBH_DMA @@ -642,8 +645,8 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs; - if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) && - dev_id == 1) { + if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6ULL)) && dev_id == 1) { u32 value = readl(&fuse->mac_addr2); mac[0] = value >> 24 ; mac[1] = value >> 16 ; diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index 17aa3fe..695894e 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -80,7 +80,7 @@ void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || - is_soc_type(MXC_SOC_MX7)) + is_cpu_type(MXC_CPU_MX6ULL) || is_soc_type(MXC_SOC_MX7)) writew(enable, &wdog3->wmcr); #ifdef CONFIG_MX7D writew(enable, &wdog4->wmcr); diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 1a97b01..0999055 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -429,15 +429,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4ed7b37..4d4b307 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -412,13 +412,13 @@ #include /* only for i.MX6SX/UL */ -#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ +#define WDOG3_BASE_ADDR (((is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ MX6UL_LCDIF1_BASE_ADDR : \ ((is_cpu_type(MXC_CPU_MX6ULL)) ? \ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)) -#define UART6_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ +#define UART6_BASE_ADDR (((is_cpu_type(MXC_CPU_MX6UL)) || is_cpu_type(MXC_CPU_MX6ULL)) ? \ MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR) #define MXS_LCDIF_BASE LCDIF1_BASE_ADDR -- 1.9.1