Correct PPC Timebase register definitions (SPRN_TBRL...)

Patch by Stefan Roese, 07 Nov 2005

Correct PPC Timebase register definitions (SPRN_TBRL...)
Patch by Stefan Roese, 07 Nov 2005
Stefan Roese
1 parent f190c11b1f
Showing 2 changed files with 7 additions and 4 deletions Side-by-side Diff
CHANGELOG
include/asm-ppc/processor.h
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
  
+* Correct PPC Timebase register definitions (SPRN_TBRL...)
+  Patch by Stefan Roese, 07 Nov 2005
+
 * Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
   Patch by Stefan Roese, 05 Nov 2005
  
@@ -310,10 +310,10 @@
 #define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
 #define SPRN_TBLO	0x3DD	/* Time Base Low */
 #define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
-#define SPRN_TBRL	0x10D	/* Time Base Read Lower Register */
-#define SPRN_TBRU	0x10C	/* Time Base Read Upper Register */
-#define SPRN_TBWL	0x11D	/* Time Base Write Lower Register */
-#define SPRN_TBWU	0x11C	/* Time Base Write Upper Register */
+#define SPRN_TBRL	0x10C	/* Time Base Read Lower Register */
+#define SPRN_TBRU	0x10D	/* Time Base Read Upper Register */
+#define SPRN_TBWL	0x11C	/* Time Base Write Lower Register */
+#define SPRN_TBWU	0x11D	/* Time Base Write Upper Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_TCR	0x3DA	/* Timer Control Register */
 #else
...	...	@@ -2,6 +2,9 @@
2	2	Changes for U-Boot 1.1.4:
3	3	======================================================================
4	4
	5	+* Correct PPC Timebase register definitions (SPRN_TBRL...)
	6	+ Patch by Stefan Roese, 07 Nov 2005
	7	+
5	8	* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
6	9	Patch by Stefan Roese, 05 Nov 2005
7	10
...	...	@@ -310,10 +310,10 @@
310	310	#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
311	311	#define SPRN_TBLO 0x3DD /* Time Base Low */
312	312	#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
313		-#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */
314		-#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
315		-#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
316		-#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
	313	+#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
	314	+#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
	315	+#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
	316	+#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
317	317	#ifndef CONFIG_BOOKE
318	318	#define SPRN_TCR 0x3DA /* Timer Control Register */
319	319	#else