Commit 1f2779187832deea28480c20c16ac687fdaf6ce4
Committed by
Ji Luo
Ji Luo
1 parent
be25ff5c10
Exists in
smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga
and in
4 other branches
MA-14519 Phanbell: Explicitly set buck voltages in SPL
* Bucks 1-4 will be reconfigured via DVS in the kernel. * Buck 5 is explicitly set to 1.0V * Regulator lock/unlock is added, this ensures that in warm or cold reset the values will be set. Change-Id: I8d8be74bddbbd081030fe1762b9f9c6534c7fb77
Showing 1 changed file with 19 additions and 10 deletions Side-by-side Diff
board/freescale/imx8mq_aiy/spl.c
| 1 | 1 | /* |
| 2 | - * Copyright 2017 NXP | |
| 2 | + * Copyright 2019 NXP | |
| 3 | 3 | * |
| 4 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | 5 | */ |
| 6 | 6 | |
| 7 | 7 | |
| 8 | 8 | |
| 9 | 9 | |
| 10 | 10 | |
| 11 | 11 | |
| ... | ... | @@ -167,23 +167,32 @@ |
| 167 | 167 | p = pmic_get("BD71837"); |
| 168 | 168 | pmic_probe(p); |
| 169 | 169 | |
| 170 | - /* unlock the PMIC regs */ | |
| 170 | + /* Unlock reg */ | |
| 171 | 171 | pmic_reg_write(p, BD71837_REGLOCK, 0x1); |
| 172 | 172 | |
| 173 | - /* Set BUCK2 output for ARM to 0.85v */ | |
| 174 | - pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x0f); | |
| 173 | + /* Set BUCK5 output for DRAM to 1.0V */ | |
| 174 | + /* 0.70,0.80,0.90,1.00, 1.05,1.10,1.20,1.35 */ | |
| 175 | + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3); | |
| 175 | 176 | |
| 176 | - /* Set BUCK5 output for DRAM to 0.9V */ | |
| 177 | - pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2); | |
| 177 | + /* Set BUCK3 output for VDD_GPU_0V9 to 0.90V */ | |
| 178 | + /* 0.7-1.3 (10mVstep) */ | |
| 179 | + pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14); | |
| 178 | 180 | |
| 179 | - /* Set BUCK6 output for VDD_3V3 to 3.1V */ | |
| 180 | - pmic_reg_write(p, BD71837_BUCK6_VOLT, 0x1); | |
| 181 | + /* Set BUCK4 output for VDD_VPU_0V9 to 0.90V */ | |
| 182 | + /* 0.7-1.3 (10mVstep) */ | |
| 183 | + pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14); | |
| 181 | 184 | |
| 182 | - /* Set BUCK7 output for VDD_1V8 to 1.695V */ | |
| 183 | - pmic_reg_write(p, BD71837_BUCK7_VOLT, 0x1); | |
| 185 | + /* Set BUCK2 output for VDD_ARM_0V9 to 0.90V */ | |
| 186 | + /* 0.7-1.3 (10mVstep) */ | |
| 187 | + pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x14); | |
| 184 | 188 | |
| 189 | + /* Set BUCK1 output for VDD_SOC_0V9 to 0.90V */ | |
| 190 | + /* 0.7-1.3 (10mVstep) */ | |
| 191 | + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x14); | |
| 192 | + | |
| 185 | 193 | /* lock the PMIC regs */ |
| 186 | 194 | pmic_reg_write(p, BD71837_REGLOCK, 0x11); |
| 195 | + | |
| 187 | 196 | return 0; |
| 188 | 197 | } |
| 189 | 198 | #endif |