diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 179d796..91a24b3 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -261,13 +261,6 @@ void update_rtc_magic(void)
*/
int board_early_init_f(void)
{
-#ifdef CONFIG_NOR_BOOT
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init();
- gd->have_console = 1;
-#elif defined(CONFIG_SPL_BUILD)
- preloader_console_init();
-#endif
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 97bbfe2..1806c85 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -108,6 +108,38 @@
#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
+/* Samsung K4B4G1646E-BYK0 */
+#define K4B4G1646EBYK0_EMIF_READ_LATENCY 0x100007
+#define K4B4G1646EBYK0_EMIF_TIM1 0x0AAAE51B
+#define K4B4G1646EBYK0_EMIF_TIM2 0x267B7FDA
+#define K4B4G1646EBYK0_EMIF_TIM3 0x501F877F
+#define K4B4G1646EBYK0_EMIF_SDCFG 0x61C05332
+#define K4B4G1646EBYK0_EMIF_SDREF 0xC30
+#define K4B4G1646EBYK0_ZQ_CFG 0x50074BE4
+#define K4B4G1646EBYK0_RATIO 0x80
+#define K4B4G1646EBYK0_INVERT_CLKOUT 0x0
+#define K4B4G1646EBYK0_RD_DQS 0x3B
+#define K4B4G1646EBYK0_WR_DQS 0x4A
+#define K4B4G1646EBYK0_PHY_WR_DATA 0x83
+#define K4B4G1646EBYK0_PHY_FIFO_WE 0xA4
+#define K4B4G1646EBYK0_IOCTRL_VALUE 0x18B
+
+/* Micron MT41K256M16HA-125ITE */
+#define MT41K256M16HA125ITE_EMIF_READ_LATENCY 0x100007
+#define MT41K256M16HA125ITE_EMIF_TIM1 0x0AAAE51B
+#define MT41K256M16HA125ITE_EMIF_TIM2 0x267B7FDA
+#define MT41K256M16HA125ITE_EMIF_TIM3 0x501F877F
+#define MT41K256M16HA125ITE_EMIF_SDCFG 0x61C05332
+#define MT41K256M16HA125ITE_EMIF_SDREF 0xC30
+#define MT41K256M16HA125ITE_ZQ_CFG 0x50074BE4
+#define MT41K256M16HA125ITE_RATIO 0x80
+#define MT41K256M16HA125ITE_INVERT_CLKOUT 0x0
+#define MT41K256M16HA125ITE_RD_DQS 0x3D
+#define MT41K256M16HA125ITE_WR_DQS 0x4B
+#define MT41K256M16HA125ITE_PHY_WR_DATA 0x7F
+#define MT41K256M16HA125ITE_PHY_FIFO_WE 0x9D
+#define MT41K256M16HA125ITE_IOCTRL_VALUE 0x18B
+
/* Micron MT41J512M8RH-125 on EVM v1.5 */
#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
diff --git a/board/embedian/smarct335x/board.c b/board/embedian/smarct335x/board.c
index e2d74aa..703d920 100644
--- a/board/embedian/smarct335x/board.c
+++ b/board/embedian/smarct335x/board.c
@@ -127,10 +127,17 @@ static const struct ddr_data ddr3_beagleblack_data = {
};
static const struct ddr_data ddr3_smarct335x_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+ .datardsratio0 = K4B4G1646EBYK0_RD_DQS,
+ .datawdsratio0 = K4B4G1646EBYK0_WR_DQS,
+ .datafwsratio0 = K4B4G1646EBYK0_PHY_FIFO_WE,
+ .datawrsratio0 = K4B4G1646EBYK0_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_smarct335x80_data = {
+ .datardsratio0 = MT41K256M16HA125ITE_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125ITE_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125ITE_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125ITE_PHY_WR_DATA,
};
static const struct ddr_data ddr3_evm_data = {
@@ -163,14 +170,25 @@ static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
};
static const struct cmd_control ddr3_smarct335x_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd0csratio = K4B4G1646EBYK0_RATIO,
+ .cmd0iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd1csratio = K4B4G1646EBYK0_RATIO,
+ .cmd1iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd2csratio = K4B4G1646EBYK0_RATIO,
+ .cmd2iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_smarct335x80_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125ITE_RATIO,
+ .cmd0iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125ITE_RATIO,
+ .cmd1iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125ITE_RATIO,
+ .cmd2iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
@@ -206,13 +224,23 @@ static struct emif_regs ddr3_beagleblack_emif_reg_data = {
};
static struct emif_regs ddr3_smarct335x_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+ .sdram_config = K4B4G1646EBYK0_EMIF_SDCFG,
+ .ref_ctrl = K4B4G1646EBYK0_EMIF_SDREF,
+ .sdram_tim1 = K4B4G1646EBYK0_EMIF_TIM1,
+ .sdram_tim2 = K4B4G1646EBYK0_EMIF_TIM2,
+ .sdram_tim3 = K4B4G1646EBYK0_EMIF_TIM3,
+ .zq_config = K4B4G1646EBYK0_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = K4B4G1646EBYK0_EMIF_READ_LATENCY,
+};
+
+static struct emif_regs ddr3_smarct335x80_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125ITE_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125ITE_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125ITE_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125ITE_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125ITE_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125ITE_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125ITE_EMIF_READ_LATENCY,
};
static struct emif_regs ddr3_evm_emif_reg_data = {
@@ -463,11 +491,19 @@ const struct ctrl_ioregs ioregs_bonelt = {
};
const struct ctrl_ioregs ioregs_smarct335x = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
+ .cm1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
+ .cm2ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
+ .dt0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
+ .dt1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_smarct335x80 = {
+ .cm0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_evm15 = {
@@ -510,20 +546,35 @@ void sdram_init(void)
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
- else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
+ else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
+ /*
+ * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
+ * This is safe enough to do on older revs.
+ */
+ gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
+ gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
+ gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
+ gpio_direction_output(GPIO_LCD_PWM_EN, 1);
+ config_ddr(400, &ioregs_smarct335x,
+ &ddr3_smarct335x_data,
+ &ddr3_smarct335x_cmd_ctrl_data,
+ &ddr3_smarct335x_emif_reg_data, 0);
+ udelay(1600);
+ }
+ else if (board_is_smarc_t335x_80(&header)) {
/*
* SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
* This is safe enough to do on older revs.
*/
- gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
+ gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
gpio_direction_output(GPIO_LCD_PWM_EN, 1);
- config_ddr(400, &ioregs_smarct335x,
- &ddr3_smarct335x_data,
- &ddr3_smarct335x_cmd_ctrl_data,
- &ddr3_smarct335x_emif_reg_data, 0);
- puts("Set DDR3 to 800MHz.\n");
+ config_ddr(400, &ioregs_smarct335x80,
+ &ddr3_smarct335x80_data,
+ &ddr3_smarct335x80_cmd_ctrl_data,
+ &ddr3_smarct335x80_emif_reg_data, 0);
+ udelay(1600);
}
else if (board_is_evm_15_or_later(&header))
config_ddr(400, &ioregs_evm15, &ddr3_evm_data,