Commit 2ce35d537bb0213da95b597d3176051319bcdca6

Authored by Eric Lee
1 parent c2f85087ff

Make changes for rev. 00E0 hardware revision

Showing 2 changed files with 15 additions and 11 deletions Side-by-side Diff

arch/arm/dts/imx8mq-smarc.dts
... ... @@ -219,7 +219,6 @@
219 219 vgen6_reg: vgen6 {
220 220 regulator-min-microvolt = <1800000>;
221 221 regulator-max-microvolt = <3300000>;
222   - regulator-always-on;
223 222 };
224 223 };
225 224 };
... ... @@ -666,9 +665,8 @@
666 665 fsl,pins = <
667 666 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79
668 667 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79
669   - MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */
670   - MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */
671   -
  668 + MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x79 /* RTS */
  669 + MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x79 /* CTS */
672 670 >;
673 671 };
674 672  
... ... @@ -681,8 +679,10 @@
681 679  
682 680 pinctrl_uart4: uart4grp {
683 681 fsl,pins = <
684   - MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79
685   - MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79
  682 + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x79
  683 + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x79
  684 + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x79 /* RTS */
  685 + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x79 /* CTS */
686 686 >;
687 687 };
688 688  
board/embedian/smarcimx8mq/smarcimx8mq.c
... ... @@ -56,6 +56,9 @@
56 56 static iomux_v3_cfg_t const uart2_pads[] = {
57 57 IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
58 58 IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  59 + IMX8MQ_PAD_UART4_TXD__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  60 + IMX8MQ_PAD_UART4_RXD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  61 +
59 62 };
60 63 #endif
61 64  
62 65  
... ... @@ -68,10 +71,10 @@
68 71  
69 72 #ifdef CONFIG_CONSOLE_SER0
70 73 static iomux_v3_cfg_t const uart4_pads[] = {
71   - IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  74 + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
72 75 IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
73 76 IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
74   - IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  77 + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
75 78 };
76 79 #endif
77 80  
... ... @@ -124,7 +127,8 @@
124 127 IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE*/
125 128 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /*S148, LID#*/
126 129 IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), /*S149, SLEEP#*/
127   - IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/
  130 + IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
  131 +/*S151, CHARGING#*/
128 132 IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*S152, CHARGER_PRSNT#*/
129 133 IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /*S153, CARRIER_STBY#*/
130 134 IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*S156, BATLOW#*/
... ... @@ -143,8 +147,8 @@
143 147 gpio_request(IMX_GPIO_NR(1, 12), "SLEEP#");
144 148 gpio_direction_input(IMX_GPIO_NR(1, 12));
145 149 /* Set CARRIER_CHARGING# as Input*/
146   - gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#");
147   - gpio_direction_input(IMX_GPIO_NR(1, 01));
  150 + gpio_request(IMX_GPIO_NR(3, 11), "CHARGING#");
  151 + gpio_direction_input(IMX_GPIO_NR(3, 11));
148 152 /* Set CARRIER_CHARGER_PRSNT# as Input*/
149 153 gpio_request(IMX_GPIO_NR(4, 22), "CHARGER_PRSNT#");
150 154 gpio_direction_input(IMX_GPIO_NR(4, 22));