From 2d41934ee1ca738d6a2083dc43304fa55ff5e547 Mon Sep 17 00:00:00 2001
From: Eric Lee <eric.lee@embedian.com>
Date: Tue, 8 Sep 2020 16:32:07 +0800
Subject: [PATCH] U-Boot v2020.04 Support for SMARC-iMX8MM, Initial Release

---
 arch/arm/dts/Makefile                      |    1 +
 arch/arm/dts/imx8mm-smarc.dts              |  731 ++++++
 arch/arm/dts/imx8mm.dtsi                   |    2 +-
 arch/arm/mach-imx/imx8m/Kconfig            |    7 +
 board/embedian/smarcimx8mm/Kconfig         |   12 +
 board/embedian/smarcimx8mm/MAINTAINERS     |    7 +
 board/embedian/smarcimx8mm/Makefile        |   12 +
 board/embedian/smarcimx8mm/README          |   38 +
 board/embedian/smarcimx8mm/lpddr4_timing.c | 3691 ++++++++++++++++++++++++++++
 board/embedian/smarcimx8mm/smarcimx8mm.c   |  673 +++++
 board/embedian/smarcimx8mm/spl.c           |  291 +++
 configs/smarcimx8mm_2g_ser0_defconfig      |  130 +
 configs/smarcimx8mm_2g_ser1_defconfig      |  130 +
 configs/smarcimx8mm_2g_ser2_defconfig      |  130 +
 configs/smarcimx8mm_2g_ser3_defconfig      |  130 +
 configs/smarcimx8mm_4g_ser0_defconfig      |  128 +
 configs/smarcimx8mm_4g_ser1_defconfig      |  128 +
 configs/smarcimx8mm_4g_ser2_defconfig      |  128 +
 configs/smarcimx8mm_4g_ser3_defconfig      |  128 +
 drivers/mtd/spi/spi-nor-ids.c              |    2 +-
 include/configs/smarcimx8mm.h              |  379 +++
 include/configs/smarcimx8mm_android.h      |   76 +
 22 files changed, 6952 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/imx8mm-smarc.dts
 create mode 100644 board/embedian/smarcimx8mm/Kconfig
 create mode 100644 board/embedian/smarcimx8mm/MAINTAINERS
 create mode 100644 board/embedian/smarcimx8mm/Makefile
 create mode 100644 board/embedian/smarcimx8mm/README
 create mode 100644 board/embedian/smarcimx8mm/lpddr4_timing.c
 create mode 100644 board/embedian/smarcimx8mm/smarcimx8mm.c
 create mode 100644 board/embedian/smarcimx8mm/spl.c
 create mode 100644 configs/smarcimx8mm_2g_ser0_defconfig
 create mode 100644 configs/smarcimx8mm_2g_ser1_defconfig
 create mode 100644 configs/smarcimx8mm_2g_ser2_defconfig
 create mode 100644 configs/smarcimx8mm_2g_ser3_defconfig
 create mode 100644 configs/smarcimx8mm_4g_ser0_defconfig
 create mode 100644 configs/smarcimx8mm_4g_ser1_defconfig
 create mode 100644 configs/smarcimx8mm_4g_ser2_defconfig
 create mode 100644 configs/smarcimx8mm_4g_ser3_defconfig
 create mode 100644 include/configs/smarcimx8mm.h
 create mode 100644 include/configs/smarcimx8mm_android.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 48a6014..f261471 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -783,6 +783,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 
 dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-evk.dtb \
+	imx8mm-smarc.dtb \
 	imx8mm-ddr4-evk.dtb \
 	imx8mm-ddr3l-val.dtb \
 	imx8mm-ddr4-val.dtb \
diff --git a/arch/arm/dts/imx8mm-smarc.dts b/arch/arm/dts/imx8mm-smarc.dts
new file mode 100644
index 0000000..7721f07
--- /dev/null
+++ b/arch/arm/dts/imx8mm-smarc.dts
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2020 EMBEDIAN, INC.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mm.dtsi"
+
+/ {
+	model = "Embedian SMARC-iMX8MM Computer on Module";
+	compatible = "embedian,smarcimx8mm", "fsl,imx8mm";
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		off-on-delay-us = <20000>;
+		enable-active-high;
+	};
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 1000000 0>;
+                brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+                                     10 11 12 13 14 15 16 17 18 19
+                                     20 21 22 23 24 25 26 27 28 29
+                                     30 31 32 33 34 35 36 37 38 39
+                                     40 41 42 43 44 45 46 47 48 49
+                                     50 51 52 53 54 55 56 57 58 59
+                                     60 61 62 63 64 65 66 67 68 69
+                                     70 71 72 73 74 75 76 77 78 79
+                                     80 81 82 83 84 85 86 87 88 89
+                                     90 91 92 93 94 95 96 97 98 99
+                                    100>;
+                default-brightness-level = <80>;
+                status = "disabled";
+        };
+
+	dsi_host: dsi-host {
+		compatible = "samsung,sec-mipi-dsi";
+		status = "okay";
+	};
+
+	reg_3p3v: 3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_5p0v: 5p0v {
+		compatible = "regulator-fixed";
+		regulator-name = "5P0V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+        /* external oscillator of mcp2515 on SPI1.2 and SPI1.3 */
+        clk25m: clock-25m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency  = <25000000>;
+                clock-output-names = "clk25m";
+        };
+};
+
+&A53_0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <6>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+
+	pmic@4b {
+		compatible = "rohm,bd71847";
+		reg = <0x4b>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 GPIO_ACTIVE_LOW>;
+		rohm,reset-snvs-powered;
+
+		regulators {
+			buck1_reg: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3_reg: BUCK3 {
+				// BUCK5 in datasheet
+				regulator-name = "BUCK3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				// BUCK6 in datasheet
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: BUCK5 {
+				// BUCK7 in datasheet
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				// BUCK8 in datasheet
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <1900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo6_reg: LDO6 {
+				regulator-name = "LDO6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c4 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default", "gpio";
+        pinctrl-0 = <&pinctrl_i2c4>;
+        pinctrl-1 = <&pinctrl_i2c4_gpio>;
+        scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
+        sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+/* SER0 */
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+        assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+/* SER1 */
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "okay";
+};
+
+/* SER2 */
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        assigned-clocks = <&clk IMX8MM_CLK_UART3>;
+        assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+/* SER3 */
+&uart2 { /* console */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&pwm1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&ecspi2 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi2>;
+        cs-gpios = <&gpio5 13 0>, <&gpio1 0 0>;
+        fsl,spi-num-chipselects = <2>;
+        status = "okay";
+
+        spidev@0 {
+                compatible = "rohm,dh2228fv";
+                reg = <0>;
+                spi-max-frequency = <24000000>;
+                };
+
+        spidev@1 {
+                compatible = "rohm,dh2228fv";
+                reg = <1>;
+                spi-max-frequency = <24000000>;
+                };
+};
+
+&ecspi3 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi3>;
+        cs-gpios = <&gpio5 25 0>, <&gpio3 2 0>, <&gpio3 15 0>, <&gpio3 17 0>;
+        fsl,spi-num-chipselects = <4>;
+        status = "okay";
+
+        spidev@0 {
+                compatible = "rohm,dh2228fv";
+                reg = <0>;
+                spi-max-frequency = <24000000>;
+                };
+
+        spidev@1 {
+                compatible = "rohm,dh2228fv";
+                reg = <1>;
+                spi-max-frequency = <24000000>;
+                };
+
+        can1: can@2 {
+                compatible = "microchip,mcp2515";
+                reg = <2>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                spi-max-frequency = <10000000>;
+                clocks = <&clk25m>;
+                vdd-supply = <&reg_3p3v>;
+                xceiver-supply = <&reg_5p0v>;
+        };
+
+        can2: can@3 {
+                compatible = "microchip,mcp2515";
+                reg = <3>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+                spi-max-frequency = <10000000>;
+                clocks = <&clk25m>;
+                vdd-supply = <&reg_3p3v>;
+                xceiver-supply = <&reg_5p0v>;
+  	};
+};
+
+&usbotg1 {
+        status = "okay";
+        dr_mode = "peripheral";
+};
+
+&usbotg2 {
+        status = "okay";
+        dr_mode = "host";
+};
+
+&usdhc1 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc1>;
+        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+        pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+        pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_usdhc2_vmmc>;
+        status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4               0x41
+		>;
+	};
+
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
+			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
+			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
+			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
+			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
+			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
+		>;
+	};
+
+	pinctrl_gpio_led: gpioledgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
+		>;
+	};
+
+	pinctrl_gpio_wlf: gpiowlfgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT     0x06
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1grp-gpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        0x1c3
+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        0x1c3
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2grp-gpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        0x1c3
+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        0x1c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3grp-gpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        0x1c3
+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        0x1c3
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4grp-gpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x1c3
+			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x1c3
+		>;
+	};
+
+	pinctrl_pmic: pmicirq {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+		>;
+	};
+
+	pinctrl_typec1: typec1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
+		>;
+	};
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX	0x140
+                        MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX	0x140
+                        MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
+                        MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
+                >;
+        };
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
+			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
+			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140
+			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x140
+			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
+ 			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d0
+ 			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d0
+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d0
+ 			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d0
+ 			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x190
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d4
+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d4
+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d4
+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d4
+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x194
+		>;
+	};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
+			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d6
+			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d6
+			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d6
+			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d6
+			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x196
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x1c4
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
+		>;
+	};
+
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+                	MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x13
+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x13
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x13
+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x13
+			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0       0x13
+		>;
+	};
+
+pinctrl_ecspi3: ecspi3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK      0x13
+			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI      0x13
+			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO      0x13
+			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25       0x13
+			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2       0x13
+			MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15       0x13
+			MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17       0x13
+		>;
+	};
+
+	pinctrl_mipi_dsi_en: mipi_dsi_en {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x19
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index 0b2b589..121bb29 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -133,7 +133,7 @@
 
 		opp-1600000000 {
 			opp-hz = /bits/ 64 <1600000000>;
-			opp-microvolt = <900000>;
+			opp-microvolt = <950000>;
 			opp-supported-hw = <0xc>, <0x7>;
 			clock-latency-ns = <150000>;
 			opp-suspend;
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 2871428..5fefabe 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -86,6 +86,12 @@ config TARGET_IMX8MM_EVK
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
 
+config TARGET_SMARCIMX8MM
+        bool "smarcimx8mm CPU modules"
+        select IMX8MM
+        select SUPPORT_SPL
+        select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_DDR4_EVK
 	bool "imx8mm DDR4 EVK board"
 	select IMX8MM
@@ -141,6 +147,7 @@ source "board/embedian/smarcimx8mq/Kconfig"
 source "board/freescale/imx8mq_val/Kconfig"
 source "board/freescale/imx8mm_ab2/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
+source "board/embedian/smarcimx8mm/Kconfig"
 source "board/freescale/imx8mm_val/Kconfig"
 source "board/freescale/imx8mn_evk/Kconfig"
 source "board/freescale/imx8mp_evk/Kconfig"
diff --git a/board/embedian/smarcimx8mm/Kconfig b/board/embedian/smarcimx8mm/Kconfig
new file mode 100644
index 0000000..df71ea5f
--- /dev/null
+++ b/board/embedian/smarcimx8mm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMARCIMX8MM
+
+config SYS_BOARD
+	default "smarcimx8mm"
+
+config SYS_VENDOR
+	default "embedian"
+
+config SYS_CONFIG_NAME
+	default "smarcimx8mm"
+
+endif
diff --git a/board/embedian/smarcimx8mm/MAINTAINERS b/board/embedian/smarcimx8mm/MAINTAINERS
new file mode 100644
index 0000000..c82b074
--- /dev/null
+++ b/board/embedian/smarcimx8mm/MAINTAINERS
@@ -0,0 +1,7 @@
+SMARC-iMX8MQ CPU Module
+M:	Eric Lee <eric.lee@embedian.com>
+S:	Maintained
+F:	board/embedian/smarcimx8mm/
+F:	include/configs/smarcimx8mm.h
+F:	configs/smarcimx8mm_*_defconfig
+F:	arch/arm/dts/imx8mm-smarc.dts
diff --git a/board/embedian/smarcimx8mm/Makefile b/board/embedian/smarcimx8mm/Makefile
new file mode 100644
index 0000000..0f2d088
--- /dev/null
+++ b/board/embedian/smarcimx8mm/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ../../freescale/common/mmc.o smarcimx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/embedian/smarcimx8mm/README b/board/embedian/smarcimx8mm/README
new file mode 100644
index 0000000..ecea3f3
--- /dev/null
+++ b/board/embedian/smarcimx8mm/README
@@ -0,0 +1,38 @@
+U-Boot for the Embdian SMARC-iMX8MQ CPU board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi fimware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.24_2.1.0
+$ make PLAT=imx8mm bl31
+$ cp build/imx8mm/release/bl31.bin $(builddir)
+
+Get the ddr and hdmi firmware
+=============================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.8.bin
+$ chmod +x firmware-imx-8.8.bin
+$ ./firmware-imx-8.8.bin
+$ cp firmware-imx-8.8/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+============
+$ wget -c https://developer.arm.com/-/media/Files/downloads/gnu-a/8.3-2019.03/binrel/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu.tar.xz 
+$ sudo tar -C /opt -xJf gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu.tar.xz
+$ export CC=/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu/bin/aarch64-linux-gnu-
+$ make ARCH=arm CROSS_COMPILE=${CC} smarcimx8mm_2/4g_ser1/2/3_defconfig
+$ make ARCH=arm CROSS_COMPILE=${CC}
+
+Burn the flash.bin to MicroSD card offset 33KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+====
+Shunt cross TEST# pin to GND and Set BOOT_SEL to ON OFF OFF to boot from SD.
diff --git a/board/embedian/smarcimx8mm/lpddr4_timing.c b/board/embedian/smarcimx8mm/lpddr4_timing.c
new file mode 100644
index 0000000..8ffaef0
--- /dev/null
+++ b/board/embedian/smarcimx8mm/lpddr4_timing.c
@@ -0,0 +1,3691 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <common.h>
+#if defined(CONFIG_2GB_LPDDR4)
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa1080020},
+	{0x3d400020,0x203},
+	{0x3d400024,0x3a980},
+	{0x3d400064,0x5b00d2},
+	{0x3d4000d0,0xc00305ba},
+	{0x3d4000d4,0x940000},
+	{0x3d4000dc,0xd4002d},
+	{0x3d4000e0,0x310000},
+	{0x3d4000e8,0x66004d},
+	{0x3d4000ec,0x16004d},
+	{0x3d400100,0x191e1920},
+	{0x3d400104,0x60630},
+	{0x3d40010c,0xb0b000},
+	{0x3d400110,0xe04080e},
+	{0x3d400114,0x2040c0c},
+	{0x3d400118,0x1010007},
+	{0x3d40011c,0x401},
+	{0x3d400130,0x20600},
+	{0x3d400134,0xc100002},
+	{0x3d400138,0xd8},
+	{0x3d400144,0x96004b},
+	{0x3d400180,0x2ee0017},
+	{0x3d400184,0x2605b8e},
+	{0x3d400188,0x0},
+	{0x3d400190,0x497820a},
+	{0x3d400194,0x80303},
+	{0x3d4001b4,0x170a},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x1},
+	{0x3d4000f4,0xc99},
+	{0x3d400108,0x70e1617},
+	{0x3d400200,0x1f},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0x7070707},
+	{0x3d400250,0x29001701},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x4000030},
+	{0x3d400264,0x900093e7},
+	{0x3d40026c,0x2005574},
+	{0x3d400400,0x111},
+	{0x3d400408,0x72ff},
+	{0x3d400494,0x2100e07},
+	{0x3d400498,0x620096},
+	{0x3d40049c,0x1100e07},
+	{0x3d4004a0,0xc8012c},
+	{0x3d402020,0x1},
+	{0x3d402024,0x7d00},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0xc001c},
+	{0x3d4020dc,0x840000},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004d},
+	{0x3d4020ec,0x16004d},
+	{0x3d402100,0xa040305},
+	{0x3d402104,0x30407},
+	{0x3d402108,0x203060b},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x2040202},
+	{0x3d402114,0x2030202},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x1d},
+	{0x3d402144,0x14000a},
+	{0x3d402180,0x640004},
+	{0x3d402190,0x3818200},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x100},
+	{0x3d4020f4,0xc99},
+	{0x3d403020,0x1},
+	{0x3d403024,0x1f40},
+	{0x3d403050,0x20d040},
+	{0x3d403064,0x30007},
+	{0x3d4030dc,0x840000},
+	{0x3d4030e0,0x310000},
+	{0x3d4030e8,0x66004d},
+	{0x3d4030ec,0x16004d},
+	{0x3d403100,0xa010102},
+	{0x3d403104,0x30404},
+	{0x3d403108,0x203060b},
+	{0x3d40310c,0x505000},
+	{0x3d403110,0x2040202},
+	{0x3d403114,0x2030202},
+	{0x3d403118,0x1010004},
+	{0x3d40311c,0x301},
+	{0x3d403130,0x20300},
+	{0x3d403134,0xa100002},
+	{0x3d403138,0x8},
+	{0x3d403144,0x50003},
+	{0x3d403180,0x190004},
+	{0x3d403190,0x3818200},
+	{0x3d403194,0x80303},
+	{0x3d4031b4,0x100},
+	{0x3d4030f4,0xc99},
+	{0x3d400028,0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x2},
+	{0x110a3,0x3},
+	{0x110a4,0x4},
+	{0x110a5,0x5},
+	{0x110a6,0x6},
+	{0x110a7,0x7},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x2},
+	{0x120a3,0x3},
+	{0x120a4,0x4},
+	{0x120a5,0x5},
+	{0x120a6,0x6},
+	{0x120a7,0x7},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x21005f,0x1ff},
+	{0x21015f,0x1ff},
+	{0x21105f,0x1ff},
+	{0x21115f,0x1ff},
+	{0x21205f,0x1ff},
+	{0x21215f,0x1ff},
+	{0x21305f,0x1ff},
+	{0x21315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0x19},
+	{0x1200c5,0x7},
+	{0x2200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x2},
+	{0x22002e,0x2},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x290204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x220024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x3},
+	{0x120056,0xa},
+	{0x220056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x21004d,0xe00},
+	{0x21014d,0xe00},
+	{0x21104d,0xe00},
+	{0x21114d,0xe00},
+	{0x21204d,0xe00},
+	{0x21214d,0xe00},
+	{0x21304d,0xe00},
+	{0x21314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x210049,0xeba},
+	{0x210149,0xeba},
+	{0x211049,0xeba},
+	{0x211149,0xeba},
+	{0x212049,0xeba},
+	{0x212149,0xeba},
+	{0x213049,0xeba},
+	{0x213149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x2ee},
+	{0x120008,0x64},
+	{0x220008,0x19},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x2200b2,0xdc},
+	{0x210043,0x5a1},
+	{0x210143,0x5a1},
+	{0x211043,0x5a1},
+	{0x211143,0x5a1},
+	{0x212043,0x5a1},
+	{0x212143,0x5a1},
+	{0x213043,0x5a1},
+	{0x213143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x2200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x220019,0x1},
+	{0x200f0,0x660},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5665},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x22002d,0x0},
+	{0x200c7,0x21},
+	{0x1200c7,0x21},
+	{0x2200c7,0x21},
+	{0x200ca,0x24},
+	{0x1200ca,0x24},
+	{0x2200ca,0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },  
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },  
+	{ 0x10043, 0x0 },  
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },  
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },  
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },  
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },  
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },  
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },  
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },  
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },       
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },    
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },    
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },    
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },    
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },    
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },    
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },    
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },    
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },    
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },  
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },  
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },  
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },  
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },  
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },  
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },  
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },  
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },  
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },  
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },  
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },  
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },  
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },  
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },  
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },  
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },  
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },  
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },  
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },  
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },  
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },  
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },  
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },  
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },  
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 }, 
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 }, 
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 }, 
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 }, 
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 }, 
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 }, 
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 }, 
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 }, 
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 }, 
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 }, 
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 }, 
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 }, 
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 }, 
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 }, 
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 }, 
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 }, 
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 }, 
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 }, 
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 }, 
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 }, 
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 }, 
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 }, 
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 }, 
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 }, 
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 }, 
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 }, 
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 }, 
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 }, 
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 }, 
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 }, 
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 }, 
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 }, 
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 }, 
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 }, 
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 }, 
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 }, 
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 }, 
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 }, 
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 }, 
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 }, 
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 }, 
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 }, 
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 }, 
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 }, 
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 }, 
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 }, 
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 }, 
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 }, 
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 }, 
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 }, 
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 }, 
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 }, 
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 }, 
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 }, 
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 }, 
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 }, 
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 }, 
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 }, 
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 }, 
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 }, 
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 }, 
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 }, 
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 }, 
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 }, 
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 }, 
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 }, 
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 }, 
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 }, 
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 }, 
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 }, 
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 }, 
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 }, 
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 }, 
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 }, 
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 }, 
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 }, 
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 }, 
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 }, 
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 }, 
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 }, 
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 }, 
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 }, 
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 }, 
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 }, 
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 }, 
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 }, 
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 }, 
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 }, 
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 }, 
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 }, 
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 }, 
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 }, 
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 }, 
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 }, 
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 }, 
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 }, 
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 }, 
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 }, 
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 }, 
+	{ 0x20073, 0x0 }, 
+	{ 0x20074, 0x0 }, 
+	{ 0x100aa, 0x0 }, 
+	{ 0x110aa, 0x0 }, 
+	{ 0x120aa, 0x0 }, 
+	{ 0x130aa, 0x0 }, 
+	{ 0x20010, 0x0 }, 
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 }, 
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 }, 
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 }, 
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 }, 
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 }, 
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 }, 
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 }, 
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 }, 
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 }, 
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 }, 
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 }, 
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 }, 
+	{ 0x130a5, 0x0 }, 
+	{ 0x130a6, 0x0 }, 
+	{ 0x130a7, 0x0 }, 
+	{ 0x2007c, 0x0 }, 
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 }, 
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 }, 
+	{ 0x400c0, 0x0 }, 
+	{ 0x90201, 0x0 }, 
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 }, 
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 }, 
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 }, 
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 }, 
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 }, 
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 }, 
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 }, 
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 }, 
+	{ 0x10162, 0x0 }, 
+	{ 0x10262, 0x0 }, 
+	{ 0x10362, 0x0 }, 
+	{ 0x10462, 0x0 }, 
+	{ 0x10562, 0x0 }, 
+	{ 0x10662, 0x0 }, 
+	{ 0x10762, 0x0 }, 
+	{ 0x10862, 0x0 }, 
+	{ 0x11062, 0x0 }, 
+	{ 0x11162, 0x0 }, 
+	{ 0x11262, 0x0 }, 
+	{ 0x11362, 0x0 }, 
+	{ 0x11462, 0x0 }, 
+	{ 0x11562, 0x0 }, 
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xbb8},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x101},
+	{0x54003,0x190},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x102},
+	{0x54003,0x64},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xbb8},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x110},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
+	{0x90033,0xe8},
+	{0x90034,0x109},
+	{0x90035,0x2},
+	{0x90036,0x10},
+	{0x90037,0x139},
+	{0x90038,0xf},
+	{0x90039,0x7c0},
+	{0x9003a,0x139},
+	{0x9003b,0x44},
+	{0x9003c,0x630},
+	{0x9003d,0x159},
+	{0x9003e,0x14f},
+	{0x9003f,0x630},
+	{0x90040,0x159},
+	{0x90041,0x47},
+	{0x90042,0x630},
+	{0x90043,0x149},
+	{0x90044,0x4f},
+	{0x90045,0x630},
+	{0x90046,0x179},
+	{0x90047,0x8},
+	{0x90048,0xe0},
+	{0x90049,0x109},
+	{0x9004a,0x0},
+	{0x9004b,0x7c8},
+	{0x9004c,0x109},
+	{0x9004d,0x0},
+	{0x9004e,0x1},
+	{0x9004f,0x8},
+	{0x90050,0x0},
+	{0x90051,0x45a},
+	{0x90052,0x9},
+	{0x90053,0x0},
+	{0x90054,0x448},
+	{0x90055,0x109},
+	{0x90056,0x40},
+	{0x90057,0x630},
+	{0x90058,0x179},
+	{0x90059,0x1},
+	{0x9005a,0x618},
+	{0x9005b,0x109},
+	{0x9005c,0x40c0},
+	{0x9005d,0x630},
+	{0x9005e,0x149},
+	{0x9005f,0x8},
+	{0x90060,0x4},
+	{0x90061,0x48},
+	{0x90062,0x4040},
+	{0x90063,0x630},
+	{0x90064,0x149},
+	{0x90065,0x0},
+	{0x90066,0x4},
+	{0x90067,0x48},
+	{0x90068,0x40},
+	{0x90069,0x630},
+	{0x9006a,0x149},
+	{0x9006b,0x10},
+	{0x9006c,0x4},
+	{0x9006d,0x18},
+	{0x9006e,0x0},
+	{0x9006f,0x4},
+	{0x90070,0x78},
+	{0x90071,0x549},
+	{0x90072,0x630},
+	{0x90073,0x159},
+	{0x90074,0xd49},
+	{0x90075,0x630},
+	{0x90076,0x159},
+	{0x90077,0x94a},
+	{0x90078,0x630},
+	{0x90079,0x159},
+	{0x9007a,0x441},
+	{0x9007b,0x630},
+	{0x9007c,0x149},
+	{0x9007d,0x42},
+	{0x9007e,0x630},
+	{0x9007f,0x149},
+	{0x90080,0x1},
+	{0x90081,0x630},
+	{0x90082,0x149},
+	{0x90083,0x0},
+	{0x90084,0xe0},
+	{0x90085,0x109},
+	{0x90086,0xa},
+	{0x90087,0x10},
+	{0x90088,0x109},
+	{0x90089,0x9},
+	{0x9008a,0x3c0},
+	{0x9008b,0x149},
+	{0x9008c,0x9},
+	{0x9008d,0x3c0},
+	{0x9008e,0x159},
+	{0x9008f,0x18},
+	{0x90090,0x10},
+	{0x90091,0x109},
+	{0x90092,0x0},
+	{0x90093,0x3c0},
+	{0x90094,0x109},
+	{0x90095,0x18},
+	{0x90096,0x4},
+	{0x90097,0x48},
+	{0x90098,0x18},
+	{0x90099,0x4},
+	{0x9009a,0x58},
+	{0x9009b,0xa},
+	{0x9009c,0x10},
+	{0x9009d,0x109},
+	{0x9009e,0x2},
+	{0x9009f,0x10},
+	{0x900a0,0x109},
+	{0x900a1,0x5},
+	{0x900a2,0x7c0},
+	{0x900a3,0x109},
+	{0x900a4,0x10},
+	{0x900a5,0x10},
+	{0x900a6,0x109},
+	{0x40000,0x811},
+	{0x40020,0x880},
+	{0x40040,0x0},
+	{0x40060,0x0},
+	{0x40001,0x4008},
+	{0x40021,0x83},
+	{0x40041,0x4f},
+	{0x40061,0x0},
+	{0x40002,0x4040},
+	{0x40022,0x83},
+	{0x40042,0x51},
+	{0x40062,0x0},
+	{0x40003,0x811},
+	{0x40023,0x880},
+	{0x40043,0x0},
+	{0x40063,0x0},
+	{0x40004,0x720},
+	{0x40024,0xf},
+	{0x40044,0x1740},
+	{0x40064,0x0},
+	{0x40005,0x16},
+	{0x40025,0x83},
+	{0x40045,0x4b},
+	{0x40065,0x0},
+	{0x40006,0x716},
+	{0x40026,0xf},
+	{0x40046,0x2001},
+	{0x40066,0x0},
+	{0x40007,0x716},
+	{0x40027,0xf},
+	{0x40047,0x2800},
+	{0x40067,0x0},
+	{0x40008,0x716},
+	{0x40028,0xf},
+	{0x40048,0xf00},
+	{0x40068,0x0},
+	{0x40009,0x720},
+	{0x40029,0xf},
+	{0x40049,0x1400},
+	{0x40069,0x0},
+	{0x4000a,0xe08},
+	{0x4002a,0xc15},
+	{0x4004a,0x0},
+	{0x4006a,0x0},
+	{0x4000b,0x623},
+	{0x4002b,0x15},
+	{0x4004b,0x0},
+	{0x4006b,0x0},
+	{0x4000c,0x4028},
+	{0x4002c,0x80},
+	{0x4004c,0x0},
+	{0x4006c,0x0},
+	{0x4000d,0xe08},
+	{0x4002d,0xc1a},
+	{0x4004d,0x0},
+	{0x4006d,0x0},
+	{0x4000e,0x623},
+	{0x4002e,0x1a},
+	{0x4004e,0x0},
+	{0x4006e,0x0},
+	{0x4000f,0x4040},
+	{0x4002f,0x80},
+	{0x4004f,0x0},
+	{0x4006f,0x0},
+	{0x40010,0x2604},
+	{0x40030,0x15},
+	{0x40050,0x0},
+	{0x40070,0x0},
+	{0x40011,0x708},
+	{0x40031,0x5},
+	{0x40051,0x0},
+	{0x40071,0x2002},
+	{0x40012,0x8},
+	{0x40032,0x80},
+	{0x40052,0x0},
+	{0x40072,0x0},
+	{0x40013,0x2604},
+	{0x40033,0x1a},
+	{0x40053,0x0},
+	{0x40073,0x0},
+	{0x40014,0x708},
+	{0x40034,0xa},
+	{0x40054,0x0},
+	{0x40074,0x2002},
+	{0x40015,0x4040},
+	{0x40035,0x80},
+	{0x40055,0x0},
+	{0x40075,0x0},
+	{0x40016,0x60a},
+	{0x40036,0x15},
+	{0x40056,0x1200},
+	{0x40076,0x0},
+	{0x40017,0x61a},
+	{0x40037,0x15},
+	{0x40057,0x1300},
+	{0x40077,0x0},
+	{0x40018,0x60a},
+	{0x40038,0x1a},
+	{0x40058,0x1200},
+	{0x40078,0x0},
+	{0x40019,0x642},
+	{0x40039,0x1a},
+	{0x40059,0x1300},
+	{0x40079,0x0},
+	{0x4001a,0x4808},
+	{0x4003a,0x880},
+	{0x4005a,0x0},
+	{0x4007a,0x0},
+	{0x900a7,0x0},
+	{0x900a8,0x790},
+	{0x900a9,0x11a},
+	{0x900aa,0x8},
+	{0x900ab,0x7aa},
+	{0x900ac,0x2a},
+	{0x900ad,0x10},
+	{0x900ae,0x7b2},
+	{0x900af,0x2a},
+	{0x900b0,0x0},
+	{0x900b1,0x7c8},
+	{0x900b2,0x109},
+	{0x900b3,0x10},
+	{0x900b4,0x2a8},
+	{0x900b5,0x129},
+	{0x900b6,0x8},
+	{0x900b7,0x370},
+	{0x900b8,0x129},
+	{0x900b9,0xa},
+	{0x900ba,0x3c8},
+	{0x900bb,0x1a9},
+	{0x900bc,0xc},
+	{0x900bd,0x408},
+	{0x900be,0x199},
+	{0x900bf,0x14},
+	{0x900c0,0x790},
+	{0x900c1,0x11a},
+	{0x900c2,0x8},
+	{0x900c3,0x4},
+	{0x900c4,0x18},
+	{0x900c5,0xe},
+	{0x900c6,0x408},
+	{0x900c7,0x199},
+	{0x900c8,0x8},
+	{0x900c9,0x8568},
+	{0x900ca,0x108},
+	{0x900cb,0x18},
+	{0x900cc,0x790},
+	{0x900cd,0x16a},
+	{0x900ce,0x8},
+	{0x900cf,0x1d8},
+	{0x900d0,0x169},
+	{0x900d1,0x10},
+	{0x900d2,0x8558},
+	{0x900d3,0x168},
+	{0x900d4,0x70},
+	{0x900d5,0x788},
+	{0x900d6,0x16a},
+	{0x900d7,0x1ff8},
+	{0x900d8,0x85a8},
+	{0x900d9,0x1e8},
+	{0x900da,0x50},
+	{0x900db,0x798},
+	{0x900dc,0x16a},
+	{0x900dd,0x60},
+	{0x900de,0x7a0},
+	{0x900df,0x16a},
+	{0x900e0,0x8},
+	{0x900e1,0x8310},
+	{0x900e2,0x168},
+	{0x900e3,0x8},
+	{0x900e4,0xa310},
+	{0x900e5,0x168},
+	{0x900e6,0xa},
+	{0x900e7,0x408},
+	{0x900e8,0x169},
+	{0x900e9,0x6e},
+	{0x900ea,0x0},
+	{0x900eb,0x68},
+	{0x900ec,0x0},
+	{0x900ed,0x408},
+	{0x900ee,0x169},
+	{0x900ef,0x0},
+	{0x900f0,0x8310},
+	{0x900f1,0x168},
+	{0x900f2,0x0},
+	{0x900f3,0xa310},
+	{0x900f4,0x168},
+	{0x900f5,0x1ff8},
+	{0x900f6,0x85a8},
+	{0x900f7,0x1e8},
+	{0x900f8,0x68},
+	{0x900f9,0x798},
+	{0x900fa,0x16a},
+	{0x900fb,0x78},
+	{0x900fc,0x7a0},
+	{0x900fd,0x16a},
+	{0x900fe,0x68},
+	{0x900ff,0x790},
+	{0x90100,0x16a},
+	{0x90101,0x8},
+	{0x90102,0x8b10},
+	{0x90103,0x168},
+	{0x90104,0x8},
+	{0x90105,0xab10},
+	{0x90106,0x168},
+	{0x90107,0xa},
+	{0x90108,0x408},
+	{0x90109,0x169},
+	{0x9010a,0x58},
+	{0x9010b,0x0},
+	{0x9010c,0x68},
+	{0x9010d,0x0},
+	{0x9010e,0x408},
+	{0x9010f,0x169},
+	{0x90110,0x0},
+	{0x90111,0x8b10},
+	{0x90112,0x168},
+	{0x90113,0x0},
+	{0x90114,0xab10},
+	{0x90115,0x168},
+	{0x90116,0x0},
+	{0x90117,0x1d8},
+	{0x90118,0x169},
+	{0x90119,0x80},
+	{0x9011a,0x790},
+	{0x9011b,0x16a},
+	{0x9011c,0x18},
+	{0x9011d,0x7aa},
+	{0x9011e,0x6a},
+	{0x9011f,0xa},
+	{0x90120,0x0},
+	{0x90121,0x1e9},
+	{0x90122,0x8},
+	{0x90123,0x8080},
+	{0x90124,0x108},
+	{0x90125,0xf},
+	{0x90126,0x408},
+	{0x90127,0x169},
+	{0x90128,0xc},
+	{0x90129,0x0},
+	{0x9012a,0x68},
+	{0x9012b,0x9},
+	{0x9012c,0x0},
+	{0x9012d,0x1a9},
+	{0x9012e,0x0},
+	{0x9012f,0x408},
+	{0x90130,0x169},
+	{0x90131,0x0},
+	{0x90132,0x8080},
+	{0x90133,0x108},
+	{0x90134,0x8},
+	{0x90135,0x7aa},
+	{0x90136,0x6a},
+	{0x90137,0x0},
+	{0x90138,0x8568},
+	{0x90139,0x108},
+	{0x9013a,0xb7},
+	{0x9013b,0x790},
+	{0x9013c,0x16a},
+	{0x9013d,0x1f},
+	{0x9013e,0x0},
+	{0x9013f,0x68},
+	{0x90140,0x8},
+	{0x90141,0x8558},
+	{0x90142,0x168},
+	{0x90143,0xf},
+	{0x90144,0x408},
+	{0x90145,0x169},
+	{0x90146,0xc},
+	{0x90147,0x0},
+	{0x90148,0x68},
+	{0x90149,0x0},
+	{0x9014a,0x408},
+	{0x9014b,0x169},
+	{0x9014c,0x0},
+	{0x9014d,0x8558},
+	{0x9014e,0x168},
+	{0x9014f,0x8},
+	{0x90150,0x3c8},
+	{0x90151,0x1a9},
+	{0x90152,0x3},
+	{0x90153,0x370},
+	{0x90154,0x129},
+	{0x90155,0x20},
+	{0x90156,0x2aa},
+	{0x90157,0x9},
+	{0x90158,0x0},
+	{0x90159,0x400},
+	{0x9015a,0x10e},
+	{0x9015b,0x8},
+	{0x9015c,0xe8},
+	{0x9015d,0x109},
+	{0x9015e,0x0},
+	{0x9015f,0x8140},
+	{0x90160,0x10c},
+	{0x90161,0x10},
+	{0x90162,0x8138},
+	{0x90163,0x10c},
+	{0x90164,0x8},
+	{0x90165,0x7c8},
+	{0x90166,0x101},
+	{0x90167,0x8},
+	{0x90168,0x0},
+	{0x90169,0x8},
+	{0x9016a,0x8},
+	{0x9016b,0x448},
+	{0x9016c,0x109},
+	{0x9016d,0xf},
+	{0x9016e,0x7c0},
+	{0x9016f,0x109},
+	{0x90170,0x0},
+	{0x90171,0xe8},
+	{0x90172,0x109},
+	{0x90173,0x47},
+	{0x90174,0x630},
+	{0x90175,0x109},
+	{0x90176,0x8},
+	{0x90177,0x618},
+	{0x90178,0x109},
+	{0x90179,0x8},
+	{0x9017a,0xe0},
+	{0x9017b,0x109},
+	{0x9017c,0x0},
+	{0x9017d,0x7c8},
+	{0x9017e,0x109},
+	{0x9017f,0x8},
+	{0x90180,0x8140},
+	{0x90181,0x10c},
+	{0x90182,0x0},
+	{0x90183,0x1},
+	{0x90184,0x8},
+	{0x90185,0x8},
+	{0x90186,0x4},
+	{0x90187,0x8},
+	{0x90188,0x8},
+	{0x90189,0x7c8},
+	{0x9018a,0x101},
+	{0x90006,0x0},
+	{0x90007,0x0},
+	{0x90008,0x8},
+	{0x90009,0x0},
+	{0x9000a,0x0},
+	{0x9000b,0x0},
+	{0xd00e7,0x400},
+	{0x90017,0x0},
+	{0x9001f,0x2a},
+	{0x90026,0x6a},
+	{0x400d0,0x0},
+	{0x400d1,0x101},
+	{0x400d2,0x105},
+	{0x400d3,0x107},
+	{0x400d4,0x10f},
+	{0x400d5,0x202},
+	{0x400d6,0x20a},
+	{0x400d7,0x20b},
+	{0x2003a,0x2},
+	{0x2000b,0x5d},
+	{0x2000c,0xbb},
+	{0x2000d,0x753},
+	{0x2000e,0x2c},
+	{0x12000b,0xc},
+	{0x12000c,0x19},
+	{0x12000d,0xfa},
+	{0x12000e,0x10},
+	{0x22000b,0x3},
+	{0x22000c,0x6},
+	{0x22000d,0x3e},
+	{0x22000e,0x10},
+	{0x9000c,0x0},
+	{0x9000d,0x173},
+	{0x9000e,0x60},
+	{0x9000f,0x6110},
+	{0x90010,0x2152},
+	{0x90011,0xdfbd},
+	{0x90012,0x60},
+	{0x90013,0x6152},
+	{0x20010,0x5a},
+	{0x20011,0x3},
+	{0x120010,0x5a},
+	{0x120011,0x3},
+	{0x220010,0x5a},
+	{0x220011,0x3},
+	{0x40080,0xe0},
+	{0x40081,0x12},
+	{0x40082,0xe0},
+	{0x40083,0x12},
+	{0x40084,0xe0},
+	{0x40085,0x12},
+	{0x140080,0xe0},
+	{0x140081,0x12},
+	{0x140082,0xe0},
+	{0x140083,0x12},
+	{0x140084,0xe0},
+	{0x140085,0x12},
+	{0x240080,0xe0},
+	{0x240081,0x12},
+	{0x240082,0xe0},
+	{0x240083,0x12},
+	{0x240084,0xe0},
+	{0x240085,0x12},
+	{0x400fd,0xf},
+	{0x10011,0x1},
+	{0x10012,0x1},
+	{0x10013,0x180},
+	{0x10018,0x1},
+	{0x10002,0x6209},
+	{0x100b2,0x1},
+	{0x101b4,0x1},
+	{0x102b4,0x1},
+	{0x103b4,0x1},
+	{0x104b4,0x1},
+	{0x105b4,0x1},
+	{0x106b4,0x1},
+	{0x107b4,0x1},
+	{0x108b4,0x1},
+	{0x11011,0x1},
+	{0x11012,0x1},
+	{0x11013,0x180},
+	{0x11018,0x1},
+	{0x11002,0x6209},
+	{0x110b2,0x1},
+	{0x111b4,0x1},
+	{0x112b4,0x1},
+	{0x113b4,0x1},
+	{0x114b4,0x1},
+	{0x115b4,0x1},
+	{0x116b4,0x1},
+	{0x117b4,0x1},
+	{0x118b4,0x1},
+	{0x12011,0x1},
+	{0x12012,0x1},
+	{0x12013,0x180},
+	{0x12018,0x1},
+	{0x12002,0x6209},
+	{0x120b2,0x1},
+	{0x121b4,0x1},
+	{0x122b4,0x1},
+	{0x123b4,0x1},
+	{0x124b4,0x1},
+	{0x125b4,0x1},
+	{0x126b4,0x1},
+	{0x127b4,0x1},
+	{0x128b4,0x1},
+	{0x13011,0x1},
+	{0x13012,0x1},
+	{0x13013,0x180},
+	{0x13018,0x1},
+	{0x13002,0x6209},
+	{0x130b2,0x1},
+	{0x131b4,0x1},
+	{0x132b4,0x1},
+	{0x133b4,0x1},
+	{0x134b4,0x1},
+	{0x135b4,0x1},
+	{0x136b4,0x1},
+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
+#elif defined(CONFIG_4GB_LPDDR4) || defined(CONFIG_IMX8M_4G_LPDDR4)
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x203 },
+	{ 0x3d400024, 0x3a980 },
+	{ 0x3d400064, 0x5b00d2 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xd8 },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x17 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x2 },
+	{ 0x120a3, 0x3 },
+	{ 0x120a4, 0x4 },
+	{ 0x120a5, 0x5 },
+	{ 0x120a6, 0x6 },
+	{ 0x120a7, 0x7 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x1200c7, 0x21 },
+	{ 0x2200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
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+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
+#else
+#error "not a valid lpddr4 configuration for this board"
+#endif
diff --git a/board/embedian/smarcimx8mm/smarcimx8mm.c b/board/embedian/smarcimx8mm/smarcimx8mm.c
new file mode 100644
index 0000000..e4cd6d3
--- /dev/null
+++ b/board/embedian/smarcimx8mm/smarcimx8mm.c
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2020 EMBEDIAN
+ */
+#include <common.h>
+#include <hang.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include "../../freescale/common/tcpc.h"
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define WEAK_PULLUP     (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define I2C_PAD_CTRL    (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+
+#ifdef CONFIG_CONSOLE_SER0
+static iomux_v3_cfg_t const uart1_pads[] = {
+        IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_UART3_TXD_UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_UART3_RXD_UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER1
+static iomux_v3_cfg_t const uart4_pads[] = {
+        IMX8MM_PAD_UART4_RXD_UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_UART4_TXD_UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER2
+static iomux_v3_cfg_t const uart3_pads[] = {
+        IMX8MM_PAD_ECSPI1_SCLK_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_ECSPI1_MOSI_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER3
+static iomux_v3_cfg_t const uart2_pads[] = {
+        IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_NAND_MXS
+#ifdef CONFIG_SPL_BUILD
+#define NAND_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+#endif
+
+static void setup_gpmi_nand(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+#endif
+
+	init_nand_clk();
+}
+#endif
+
+/* MISC PINs */
+static iomux_v3_cfg_t const misc_pads[] = {
+        IMX8MM_PAD_NAND_CLE_GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP),              /*S146, PCIE_WAKE*/
+        IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP),            /*S148, LID#*/
+        IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),           /*S149, SLEEP#*/
+        IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP),            /*S151, CHARGING#*/
+        IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),           /*S152, CHARGER_PRSNT#*/
+        IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),             /*S153, CARRIER_STBY#*/
+        IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP),            /*S156, BATLOW#*/
+        IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),            /*CAN0_INT#*/
+        IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),         /*CAN1_INT#*/
+        IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),          /*LVDS_EN*/
+};
+
+static void setup_iomux_misc(void)
+{
+        imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
+        /* Set LID# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 9), "LID#");
+        gpio_direction_input(IMX_GPIO_NR(1, 9));
+        /* Set SLEEP# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 13), "SLEEP#");
+        gpio_direction_input(IMX_GPIO_NR(1, 13));
+        /* Set CHARGING# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#");
+        gpio_direction_input(IMX_GPIO_NR(1, 01));
+        /* Set CARRIER_CHARGER_PRSNT# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 12), "CHARGER_PRSNT#");
+        gpio_direction_input(IMX_GPIO_NR(1, 12));
+        /* Set CARRIER_STBY# as Output High*/
+        gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#");
+        gpio_direction_output(IMX_GPIO_NR(5, 02) , 1);
+        /* Set BATLOW# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 8), "BATLOW#");
+        gpio_direction_input(IMX_GPIO_NR(1, 8));
+        /* Set PCIE_WAKE# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#");
+        gpio_direction_input(IMX_GPIO_NR(3, 5));
+        /* Set CAN0_INT# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#");
+        gpio_direction_input(IMX_GPIO_NR(3, 18));
+        /* Set CAN1_INT# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#");
+        gpio_direction_input(IMX_GPIO_NR(3, 16));
+        /* Set LVDS_EN Output High*/
+        gpio_request(IMX_GPIO_NR(3, 13), "LVDS_EN");
+        gpio_direction_input(IMX_GPIO_NR(3, 13));
+}
+
+/* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/
+static iomux_v3_cfg_t const gpio_pads[] = {
+        IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P108, GPIO0*/
+        IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P109, GPIO1*/
+        IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),            /*P110, GPIO2*/
+        IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P111, GPIO3*/
+        IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P112, GPIO4*/
+        IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP),             /*P113, GPIO5*/
+        IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),             /*P114, GPIO6*/
+        IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P115, GPIO7*/
+        IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P116, GPIO8*/
+        IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),            /*P114, GPIO9*/
+        IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P115, GPIO10*/
+        IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P116, GPIO11*/
+};
+
+static void setup_iomux_gpio(void)
+{
+        imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+
+        /* Set GPIO0 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 25), "GPIO0");
+        gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
+        /* Set GPIO1 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 19), "GPIO1");
+        gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
+        /* Set GPIO2 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 20), "GPIO2");
+        gpio_direction_output(IMX_GPIO_NR(3, 20), 0);
+        /* Set GPIO3 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 21), "GPIO3");
+        gpio_direction_output(IMX_GPIO_NR(3, 21), 0);
+        /* Set GPIO4 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 22), "GPIO4");
+        gpio_direction_output(IMX_GPIO_NR(3, 22), 0);
+        /* Set GPIO5 as Output Low*/
+        gpio_request(IMX_GPIO_NR(5, 3), "GPIO5");
+        gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
+        /* Set GPIO6 as Input*/
+        gpio_request(IMX_GPIO_NR(5, 4), "GPIO6");
+        gpio_direction_input(IMX_GPIO_NR(5, 4));
+        /* Set GPIO7 as Input*/
+        gpio_request(IMX_GPIO_NR(3, 23), "GPIO7");
+        gpio_direction_input(IMX_GPIO_NR(3, 23));
+        /* Set GPIO8 as Input*/
+        gpio_request(IMX_GPIO_NR(3, 24), "GPIO8");
+        gpio_direction_input(IMX_GPIO_NR(3, 24));
+        /* Set GPIO9 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 11), "GPIO9");
+        gpio_direction_input(IMX_GPIO_NR(4, 11));
+        /* Set GPIO10 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 10), "GPIO10");
+        gpio_direction_input(IMX_GPIO_NR(4, 10));
+        /* Set GPIO11 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 20), "GPIO11");
+        gpio_direction_input(IMX_GPIO_NR(4, 20));
+}
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+#ifdef CONFIG_CONSOLE_SER0
+        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+        init_uart_clk(0);
+#endif
+#ifdef CONFIG_CONSOLE_SER1
+        imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+        init_uart_clk(3);
+#endif
+#ifdef CONFIG_CONSOLE_SER2
+        imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+        init_uart_clk(2);
+#endif
+#ifdef CONFIG_CONSOLE_SER3
+        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+        init_uart_clk(1);
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C
+/*I2C2, I2C_CAM0 and I2C_LCD*/
+struct i2c_pads_info i2c_pad_info2 = {
+        .scl = {
+                .i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 16),
+        },
+        .sda = {
+                .i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 17),
+        },
+};
+
+/*I2C3, I2C_GP*/
+struct i2c_pads_info i2c_pad_info3 = {
+        .scl = {
+                .i2c_mode = IMX8MM_PAD_I2C3_SCL_I2C3_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 18),
+        },
+        .sda = {
+                .i2c_mode = IMX8MM_PAD_I2C3_SDA_I2C3_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 19),
+        },
+};
+
+/*I2C4, I2C_CAM1*/
+struct i2c_pads_info i2c_pad_info4 = {
+        .scl = {
+                .i2c_mode = IMX8MM_PAD_I2C4_SCL_I2C4_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 20),
+        },
+        .sda = {
+                .i2c_mode = IMX8MM_PAD_I2C4_SDA_I2C4_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 21),
+        },
+};
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#define FEC_IRQ_PAD IMX_GPIO_NR(3, 04)
+static iomux_v3_cfg_t const fec1_irq_pads[] = {
+        IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_fec(void)
+{
+        imx_iomux_v3_setup_multiple_pads(fec1_irq_pads,
+                                         ARRAY_SIZE(fec1_irq_pads));
+
+        gpio_request(IMX_GPIO_NR(3, 04), "fec1_irq");
+        gpio_direction_input(IMX_GPIO_NR(3, 04));
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+        setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+/*USB Enable Over-Current and ID Pin Setting*/
+static iomux_v3_cfg_t const usb_en_oc_pads[] = {
+        IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
+        IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
+        IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+        IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_usb_en_oc(void)
+{
+        imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads,
+                                         ARRAY_SIZE(usb_en_oc_pads));
+
+        gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 10));
+        gpio_request(IMX_GPIO_NR(3, 11), "usb1_hub_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 11));
+        gpio_request(IMX_GPIO_NR(1, 10), "usb0_id");
+        gpio_direction_input(IMX_GPIO_NR(1, 10));
+        gpio_request(IMX_GPIO_NR(1, 11), "usb1_id");
+        gpio_direction_input(IMX_GPIO_NR(1, 11));
+}
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	uint8_t valb;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return -ENODEV;
+	}
+
+	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Set OVP threshold to 23V */
+	valb = 0x6;
+	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pd_switch_snk_enable(struct tcpc_port *port)
+{
+	if (port == &port1) {
+		debug("Setup pd switch on port 1\n");
+		return setup_pd_switch(1, 0x72);
+	} else if (port == &port2) {
+		debug("Setup pd switch on port 2\n");
+		return setup_pd_switch(1, 0x73);
+	} else
+		return -EINVAL;
+}
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+struct tcpc_port_config port2_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x52,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 9000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	debug("tcpc_init port 2\n");
+	ret = tcpc_init(&port2, port2_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port2 init failed, err=%d\n",
+		       __func__, ret);
+	} else if (tcpc_pd_sink_check_charging(&port2)) {
+		/* Disable PD for USB1, since USB2 has priority */
+		port1_config.disable_pd = true;
+		printf("Power supply on USB2\n");
+	}
+
+	debug("tcpc_init port 1\n");
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n",
+		       __func__, ret);
+	} else {
+		if (!port1_config.disable_pd)
+			printf("Power supply on USB1\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	struct tcpc_port *port_ptr;
+
+	debug("board_usb_init %d, type %d\n", index, init);
+
+	if (index == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	imx8m_usb_power(index, true);
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(port_ptr);
+	else
+		tcpc_setup_ufp_mode(port_ptr);
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	debug("board_usb_cleanup %d, type %d\n", index, init);
+
+	if (init == USB_INIT_HOST) {
+		if (index == 0)
+			ret = tcpc_disable_src_vbus(&port1);
+		else
+			ret = tcpc_disable_src_vbus(&port2);
+	}
+
+	imx8m_usb_power(index, false);
+	return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	int ret = 0;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	struct tcpc_port *port_ptr;
+
+	if (dev->req_seq == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	tcpc_setup_ufp_mode(port_ptr);
+
+	ret = tcpc_get_cc_status(port_ptr, &pol, &state);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_DEVICE;
+}
+
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+
+        setup_iomux_usb_en_oc();
+        setup_iomux_misc();
+        setup_iomux_gpio();
+
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+        /* Read Module Information from on module EEPROM and pass
+         * mac address to kernel
+        */
+        struct udevice *dev;
+        int ret;
+        u8 name[8];
+        u8 serial[12];
+        u8 revision[4];
+        u8 mac[6];
+
+        ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev);
+        if (ret) {
+                debug("failed to get eeprom\n");
+                return 0;
+        }
+        /* Board ID */
+        ret = dm_i2c_read(dev, 0x4, name, 8);
+        if (ret) {
+                debug("failed to read board ID from EEPROM\n");
+                return 0;
+        }
+        puts("---------Embedian SMARC-iMX8M------------\n");
+        printf("  Board ID:             %c%c%c%c%c%c%c%c\n",
+               name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]);
+
+        /* Board Hardware Revision */
+        ret = dm_i2c_read(dev, 0xc, revision, 4);
+        if (ret) {
+                debug("failed to read hardware revison from EEPROM\n");
+                return 0;
+        }
+        printf("  Hardware Revision:    %c%c%c%c\n",
+               revision[0], revision[1], revision[2], revision[3]);
+
+        /* Serial number */
+        ret = dm_i2c_read(dev, 0x10, serial, 12);
+        if (ret) {
+                debug("failed to read srial number from EEPROM\n");
+                return 0;
+        }
+        printf("  Serial Number#:       %c%c%c%c%c%c%c%c%c%c%c%c\n",
+               serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]);
+
+        /*MAC address */
+        ret = dm_i2c_read(dev, 0x3c, mac, 6);
+        if (ret) {
+                debug("failed to read eth0 mac address from EEPROM\n");
+                return 0;
+        }
+
+        if (is_valid_ethaddr(mac))
+        printf("  MAC Address:          %02x:%02x:%02x:%02x:%02x:%02x\n",
+               mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+                eth_env_set_enetaddr("ethaddr", mac);
+        puts("-----------------------------------------\n");
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+/* SMARC BOOT_SEL*/
+        gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_1");
+        gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_2");
+        gpio_request(IMX_GPIO_NR(1, 7), "BOOT_SEL_3");
+        if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
+                puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
+                puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n");
+                env_set_ulong("usb dev", 1);
+                env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
+                puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
+                puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n");
+                env_set_ulong("mmcdev", 1);
+                env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
+                puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n");
+                env_set_ulong("mmcdev", 0);
+                env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
+                puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
+                env_set("bootcmd", "run netboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) {
+                puts("Carrier SPI Boot is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) {
+                puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n");
+                hang();
+        } else {
+                puts("unsupported boot devices\n");
+                hang();
+        }
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "SMARC");
+	env_set("board_rev", "iMX8MM");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+#define LID_KEY IMX_GPIO_NR(1, 9)
+#define LID_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const lid_pads[] = {
+        IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL),
+};
+
+int is_recovery_key_pressing(void)
+{
+        imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads));
+        gpio_request(LID_KEY, "LID");
+        gpio_direction_input(LID_KEY);
+        if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */
+                printf("Recovery key pressed\n");
+                return 1;
+        }
+        return 0; /*TODO*/
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
+}
+#endif
diff --git a/board/embedian/smarcimx8mm/spl.c b/board/embedian/smarcimx8mm/spl.c
new file mode 100644
index 0000000..43b1289
--- /dev/null
+++ b/board/embedian/smarcimx8mm/spl.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+#define WEAK_PULLUP     (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+        IMX8MM_PAD_SD1_CLK_USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_CMD_USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+        IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_cd_pad =
+        IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL);
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                        gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+                        gpio_direction_output(USDHC2_PWR_GPIO, 0);
+                        udelay(500);
+                        gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		imx_iomux_v3_setup_pad(usdhc2_cd_pad);
+		gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+		gpio_direction_input(USDHC2_CD_GPIO);
+                ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+/* RESET_OUT */
+static iomux_v3_cfg_t const reset_out_pads[] = {
+        IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_reset_out(void)
+{
+        imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
+
+        /* Set CPU RESET_OUT as Output */
+        gpio_request(IMX_GPIO_NR(3, 12), "CPU_RESET");
+        gpio_direction_output(IMX_GPIO_NR(3, 12) , 0);
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_bd71837_init(I2C_PMIC);
+	if (ret)
+		printf("power init failed");
+
+	p = pmic_get("BD71837");
+	pmic_probe(p);
+
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(p, BD71837_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);
+
+#ifndef CONFIG_IMX8M_LPDDR4
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
+#endif
+
+	/* lock the PMIC regs */
+	pmic_reg_write(p, BD71837_REGLOCK, 0x11);
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+	puts("Normal Boot\n");
+        setup_iomux_reset_out();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	puts ("resetting ...\n");
+
+	reset_cpu(WDOG1_BASE_ADDR);
+
+	return 0;
+}
diff --git a/configs/smarcimx8mm_2g_ser0_defconfig b/configs/smarcimx8mm_2g_ser0_defconfig
new file mode 100644
index 0000000..873c09d
--- /dev/null
+++ b/configs/smarcimx8mm_2g_ser0_defconfig
@@ -0,0 +1,130 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER0=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/configs/smarcimx8mm_2g_ser1_defconfig b/configs/smarcimx8mm_2g_ser1_defconfig
new file mode 100644
index 0000000..8027514
--- /dev/null
+++ b/configs/smarcimx8mm_2g_ser1_defconfig
@@ -0,0 +1,130 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER1=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/configs/smarcimx8mm_2g_ser2_defconfig b/configs/smarcimx8mm_2g_ser2_defconfig
new file mode 100644
index 0000000..08d89c9
--- /dev/null
+++ b/configs/smarcimx8mm_2g_ser2_defconfig
@@ -0,0 +1,130 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER2=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/configs/smarcimx8mm_2g_ser3_defconfig b/configs/smarcimx8mm_2g_ser3_defconfig
new file mode 100644
index 0000000..4622029
--- /dev/null
+++ b/configs/smarcimx8mm_2g_ser3_defconfig
@@ -0,0 +1,130 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER3=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/configs/smarcimx8mm_4g_ser0_defconfig b/configs/smarcimx8mm_4g_ser0_defconfig
new file mode 100644
index 0000000..0441aa9
--- /dev/null
+++ b/configs/smarcimx8mm_4g_ser0_defconfig
@@ -0,0 +1,128 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER0=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/configs/smarcimx8mm_4g_ser1_defconfig b/configs/smarcimx8mm_4g_ser1_defconfig
new file mode 100644
index 0000000..e68bfc1
--- /dev/null
+++ b/configs/smarcimx8mm_4g_ser1_defconfig
@@ -0,0 +1,128 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER1=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/configs/smarcimx8mm_4g_ser2_defconfig b/configs/smarcimx8mm_4g_ser2_defconfig
new file mode 100644
index 0000000..b0b1c36
--- /dev/null
+++ b/configs/smarcimx8mm_4g_ser2_defconfig
@@ -0,0 +1,128 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER2=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/configs/smarcimx8mm_4g_ser3_defconfig b/configs/smarcimx8mm_4g_ser3_defconfig
new file mode 100644
index 0000000..5df1a16
--- /dev/null
+++ b/configs/smarcimx8mm_4g_ser3_defconfig
@@ -0,0 +1,128 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MM=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER3=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot$ "
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_IMPORTENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-smarc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-smarc.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 1fd2ade..ed72773 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -153,7 +153,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx25u2033e",  0xc22532, 0, 64 * 1024,   4, SECT_4K) },
 	{ INFO("mx25u1635e",  0xc22535, 0, 64 * 1024,  32, SECT_4K) },
 	{ INFO("mx25u3235f",  0xc22536, 0, 4 * 1024,  1024, SECT_4K) },
-	{ INFO("mx25u6435f",  0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+	{ INFO("mx25u6473f",  0xc22537, 0, 64 * 1024, 128, RD_FULL | WR_QPP) },
 	{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
 	{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
 	{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/include/configs/smarcimx8mm.h b/include/configs/smarcimx8mm.h
new file mode 100644
index 0000000..8176f0d
--- /dev/null
+++ b/include/configs/smarcimx8mm.h
@@ -0,0 +1,379 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __SMARCIMX8MM_H
+#define __SMARCIMX8MM_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	(0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET)
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x920000
+#define CONFIG_SPL_BSS_START_ADDR	0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x912000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_BD71837
+
+#define CONFIG_SYS_I2C
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DMA
+#define CONFIG_SPL_NAND_MXS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+#endif
+
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          6
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE			0x30BE0000
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
+#endif
+
+/*
+ * Another approach is add the clocks for inmates into clks_init_on
+ * in clk-imx8mm.c, then clk_ingore_unused could be removed.
+ */
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-evk-root.dtb;" \
+		"setenv jh_clk clk_ignore_unused; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
+
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=1\0"\
+	"sd_dev=2\0" \
+
+/* Initial environment variables */
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"splashimage=0x50000000\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
+	"console=ttymxc2,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
+		"nand read ${fdt_addr} 0x7000000 0x100000;"\
+		"booti ${loadaddr} - ${fdt_addr}"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	JAILHOUSE_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+        "m4_bin=hello_world.bin\0" \
+        "use_m4=no\0" \
+	"splashimage=0x50000000\0" \
+	"console=ttymxc1,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+        "m4_addr=0x7e0000\0" \
+        "m4_addr_tmp=0x48000000\0"      \
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fit=no\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+       	"usbroot=/dev/sda2 rootwait ro\0" \
+       	"mmcrootfstype=ext4 rootwait\0" \
+       	"loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
+       	"loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \
+	"mmcautodetect=yes\0" \
+       	"importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
+               	"env import -t $loadaddr $filesize\0" \
+       	"importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \
+                "env import -t $loadaddr $filesize\0" \
+       	"mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
+               	"rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \
+       	"usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
+               	"rootfstype=${mmcrootfstype} root=${usbroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+        "loadm4bin=load mmc ${mmcdev}:${mmcpart} ${m4_addr_tmp} ${m4_bin}\0" \
+       	"loadusbimage=fatload usb 0:1 ${loadaddr} ${image}\0" \
+       	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
+       	"loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \
+        "cpm4mem=cp.b ${m4_addr_tmp} ${m4_addr} 20000\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+        "m4boot=" \
+                "if test ${m4_addr} = 0x7e0000; then " \
+                        "echo Booting M4 from TCM; " \
+                "else " \
+                        "echo Booting M4 from DRAM; " \
+                        "dcache flush; " \
+                "fi; " \
+                "bootaux ${m4_addr};\0" \
+       	"usbboot=echo Booting from USB ...; " \
+               	"run usbargs; " \
+               	"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       	"if run loadusbfdt; then " \
+                               	"booti ${loadaddr} - ${fdt_addr}; " \
+                       	"else " \
+                               	"echo WARN: Cannot load the DT; " \
+                       	"fi; " \
+               	"else " \
+                       	"echo wait for boot; " \
+               	"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+   	"mmc dev ${mmcdev}; if mmc rescan; then " \
+                   "if test ${use_m4} = yes && run loadm4bin; then " \
+                           "run cpm4mem; " \
+                           "run m4boot; " \
+                   "fi; " \
+               	"echo Checking for: uEnv.txt ...; " \
+                      	"if test -e mmc ${bootpart} /uEnv.txt; then " \
+                               	"if run loadbootenv; then " \
+                                       	"echo Loaded environment from uEnv.txt;" \
+                                       	"run importbootenv;" \
+                               	"fi;" \
+                               	"echo Checking if uenvcmd is set ...;" \
+                               	"if test -n ${uenvcmd}; then " \
+                                       	"echo Running uenvcmd ...;" \
+                                       	"run uenvcmd;" \
+                               	"fi;" \
+                       	"fi; " \
+                       	"if run loadimage; then " \
+                               	"run mmcboot; " \
+                       	"else run netboot; " \
+                       	"fi; " \
+		"fi;"
+#endif
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
+#define CONFIG_SYS_MMC_ENV_DEV		2   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#ifdef CONFIG_2GB_LPDDR4
+#define PHYS_SDRAM_SIZE                 0x80000000 /* 2GB DDR */
+#elif defined(CONFIG_IMX8M_4G_LPDDR4) || defined(CONFIG_4GB_LPDDR4)
+#undef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE                 0xC0000000 /* 3GB */
+#define PHYS_SDRAM_2                    0x100000000
+#define PHYS_SDRAM_2_SIZE               0x40000000 /* 1GB */
+#else
+#undef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE                 0xC0000000 /* 3GB */
+#define PHYS_SDRAM_2                    0x100000000
+#define PHYS_SDRAM_2_SIZE               0x40000000 /* 1GB */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#ifdef CONFIG_CONSOLE_SER0
+#define CONFIG_MXC_UART_BASE            UART1_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc0"
+#endif
+
+#ifdef CONFIG_CONSOLE_SER1
+#define CONFIG_MXC_UART_BASE            UART4_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc3"
+#endif
+
+#ifdef CONFIG_CONSOLE_SER2
+#define CONFIG_MXC_UART_BASE            UART3_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc2"
+#endif
+
+#ifdef CONFIG_CONSOLE_SER3
+#define CONFIG_MXC_UART_BASE            UART2_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc1"
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+#define CONFIG_FSL_USDHC
+
+#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_FS_GENERIC
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#ifdef CONFIG_FSL_FSPI
+#define FSL_FSPI_FLASH_SIZE		SZ_32M
+#define FSL_FSPI_FLASH_NUM		1
+#define FSPI0_BASE_ADDR			0x30bb0000
+#define FSPI0_AMBA_BASE			0x0
+#define CONFIG_FSPI_QUAD_SUPPORT
+
+#define CONFIG_SYS_FSL_FSPI_AHB
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USBD_HS
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#endif
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#if defined(CONFIG_ANDROID_SUPPORT)
+#include "smarcimx8mm_android.h"
+#endif
+
+#endif
diff --git a/include/configs/smarcimx8mm_android.h b/include/configs/smarcimx8mm_android.h
new file mode 100644
index 0000000..93ee153
--- /dev/null
+++ b/include/configs/smarcimx8mm_android.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef SMARCIMX8MM_ANDROID_H
+#define SMARCIMX8MM_ANDROID_H
+
+#define CONFIG_ANDROID_AB_SUPPORT
+#ifdef CONFIG_ANDROID_AB_SUPPORT
+#define CONFIG_SYSTEM_RAMDISK_SUPPORT
+#endif
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#ifdef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN           (64 * SZ_1M)
+#endif
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"splashimage=0x50000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+
+/* Enable mcu firmware flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
+#define ANDROID_MCU_FIRMWARE_START 0x500000
+#define ANDROID_MCU_FIRMWARE_SIZE  0x40000
+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
+#endif
+
+#if !defined(CONFIG_IMX_TRUSTY_OS) || !defined(CONFIG_DUAL_BOOTLOADER)
+#undef CONFIG_FSL_CAAM_KB
+#endif
+
+#ifdef CONFIG_DUAL_BOOTLOADER
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define AVB_RPMB
+#define KEYSLOT_HWPARTITION_ID 2
+#define KEYSLOT_BLKS             0x1FFF
+#define NS_ARCH_ARM64 1
+#endif
+
+/* Enable CONFIG_ANDROID_LOW_MEMORY to config 1GB ddr */
+#ifdef  CONFIG_ANDROID_LOW_MEMORY
+#undef  PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
+#endif
+
+#ifdef CONFIG_IMX8M_4G_LPDDR4
+#undef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE          0xC0000000 /* 3GB */
+#define PHYS_SDRAM_2             0x100000000
+#define PHYS_SDRAM_2_SIZE        0x40000000 /* 1GB */
+#endif
+
+#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED
+
+#endif /* SMARCIMX8MM_ANDROID_H */
-- 
1.9.1