Eric Lee / smarc-uboot | Embedian Git Server

Commit 32dbaafa5a1fda97dbf99e6627309e7570dc14ca

Authored by Alison Wang 2012-03-27 05:49:04 +0800

Committed by Jason 2012-09-20 20:39:26 +0800

Exists in master and in 55 other branches

ColdFire: Clean up checkpatch warnings for MCF52x2

Signed-off-by: Alison Wang <b18965@freescale.com>

Showing 9 changed files with 310 additions and 262 deletions Inline Diff

arch/m68k/cpu/mcf52x2/cpu.c
arch/m68k/cpu/mcf52x2/cpu_init.c
arch/m68k/cpu/mcf52x2/interrupts.c
arch/m68k/cpu/mcf52x2/speed.c
board/freescale/m5208evbe/m5208evbe.c
board/freescale/m5253demo/m5253demo.c
board/freescale/m5253evbe/m5253evbe.c
board/freescale/m5272c3/m5272c3.c
board/freescale/m5275evb/m5275evb.c

arch/m68k/cpu/mcf52x2/cpu.c

Diff comments View file @ 32dbaaf

1	/*	1	/*
2	* (C) Copyright 2003	2	* (C) Copyright 2003
3	* Josef Baumgartner <josef.baumgartner@telex.de>	3	* Josef Baumgartner <josef.baumgartner@telex.de>
4	*	4	*
5	* MCF5282 additionals	5	* MCF5282 additionals
6	* (C) Copyright 2005	6	* (C) Copyright 2005
7	* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>	7	* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
8	*	8	*
9	* MCF5275 additions	9	* MCF5275 additions
10	* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)	10	* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
11	*	11	*
		12	* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
		13	*
12	* See file CREDITS for list of people who contributed to this	14	* See file CREDITS for list of people who contributed to this
13	* project.	15	* project.
14	*	16	*
15	* This program is free software; you can redistribute it and/or	17	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License as	18	* modify it under the terms of the GNU General Public License as
17	* published by the Free Software Foundation; either version 2 of	19	* published by the Free Software Foundation; either version 2 of
18	* the License, or (at your option) any later version.	20	* the License, or (at your option) any later version.
19	*	21	*
20	* This program is distributed in the hope that it will be useful,	22	* This program is distributed in the hope that it will be useful,
21	* but WITHOUT ANY WARRANTY; without even the implied warranty of	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23	* GNU General Public License for more details.	25	* GNU General Public License for more details.
24	*	26	*
25	* You should have received a copy of the GNU General Public License	27	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, write to the Free Software	28	* along with this program; if not, write to the Free Software
27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28	* MA 02111-1307 USA	30	* MA 02111-1307 USA
29	*/	31	*/
30		32
31	#include <common.h>	33	#include <common.h>
32	#include <watchdog.h>	34	#include <watchdog.h>
33	#include <command.h>	35	#include <command.h>
34	#include <asm/immap.h>	36	#include <asm/immap.h>
		37	#include <asm/io.h>
35	#include <netdev.h>	38	#include <netdev.h>
36	#include "cpu.h"	39	#include "cpu.h"
37		40
38	DECLARE_GLOBAL_DATA_PTR;	41	DECLARE_GLOBAL_DATA_PTR;
39		42
40	#ifdef CONFIG_M5208	43	#ifdef CONFIG_M5208
41	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	44	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
42	{	45	{
43	volatile rcm_t rcm = (rcm_t )(MMAP_RCM);	46	rcm_t rcm = (rcm_t )(MMAP_RCM);
44		47
45	udelay(1000);	48	udelay(1000);
46		49
47	rcm->rcr = RCM_RCR_SOFTRST;	50	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
48		51
49	/* we don't return! */	52	/* we don't return! */
50	return 0;	53	return 0;
51	};	54	};
52		55
53	int checkcpu(void)	56	int checkcpu(void)
54	{	57	{
55	char buf1[32], buf2[32];	58	char buf1[32], buf2[32];
56		59
57	printf("CPU: Freescale Coldfire MCF5208\n"	60	printf("CPU: Freescale Coldfire MCF5208\n"
58	" CPU CLK %s MHz BUS CLK %s MHz\n",	61	" CPU CLK %s MHz BUS CLK %s MHz\n",
59	strmhz(buf1, gd->cpu_clk),	62	strmhz(buf1, gd->cpu_clk),
60	strmhz(buf2, gd->bus_clk));	63	strmhz(buf2, gd->bus_clk));
61	return 0;	64	return 0;
62	};	65	};
63		66
64	#if defined(CONFIG_WATCHDOG)	67	#if defined(CONFIG_WATCHDOG)
65	/* Called by macro WATCHDOG_RESET */	68	/* Called by macro WATCHDOG_RESET */
66	void watchdog_reset(void)	69	void watchdog_reset(void)
67	{	70	{
68	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	71	wdog_t wdt = (wdog_t )(MMAP_WDOG);
69	wdt->sr = 0x5555;	72
70	wdt->sr = 0xAAAA;	73	out_be16(&wdt->sr, 0x5555);
		74	out_be16(&wdt->sr, 0xaaaa);
71	}	75	}
72		76
73	int watchdog_disable(void)	77	int watchdog_disable(void)
74	{	78	{
75	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	79	wdog_t wdt = (wdog_t )(MMAP_WDOG);
76		80
77	wdt->sr = 0x5555; /* reset watchdog counter */	81	/* reset watchdog counter */
78	wdt->sr = 0xAAAA;	82	out_be16(&wdt->sr, 0x5555);
79	wdt->cr = 0; /* disable watchdog timer */	83	out_be16(&wdt->sr, 0xaaaa);
		84	/* disable watchdog timer */
		85	out_be16(&wdt->cr, 0);
80		86
81	puts("WATCHDOG:disabled\n");	87	puts("WATCHDOG:disabled\n");
82	return (0);	88	return (0);
83	}	89	}
84		90
85	int watchdog_init(void)	91	int watchdog_init(void)
86	{	92	{
87	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	93	wdog_t wdt = (wdog_t )(MMAP_WDOG);
88		94
89	wdt->cr = 0; /* disable watchdog */	95	/* disable watchdog */
		96	out_be16(&wdt->cr, 0);
90		97
91	/* set timeout and enable watchdog */	98	/* set timeout and enable watchdog */
92	wdt->mr =	99	out_be16(&wdt->mr,
93	((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;	100	(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
94	wdt->sr = 0x5555; /* reset watchdog counter */
95	wdt->sr = 0xAAAA;
96		101
		102	/* reset watchdog counter */
		103	out_be16(&wdt->sr, 0x5555);
		104	out_be16(&wdt->sr, 0xaaaa);
		105
97	puts("WATCHDOG:enabled\n");	106	puts("WATCHDOG:enabled\n");
98	return (0);	107	return (0);
99	}	108	}
100	#endif /* #ifdef CONFIG_WATCHDOG */	109	#endif /* #ifdef CONFIG_WATCHDOG */
101	#endif /* #ifdef CONFIG_M5208 */	110	#endif /* #ifdef CONFIG_M5208 */
102		111
103	#ifdef CONFIG_M5271	112	#ifdef CONFIG_M5271
104	/*	113	/*
105	* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to	114	* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
106	* determine which one we are running on, based on the Chip Identification	115	* determine which one we are running on, based on the Chip Identification
107	* Register (CIR).	116	* Register (CIR).
108	*/	117	*/
109	int checkcpu(void)	118	int checkcpu(void)
110	{	119	{
111	char buf[32];	120	char buf[32];
112	unsigned short cir; /* Chip Identification Register */	121	unsigned short cir; /* Chip Identification Register */
113	unsigned short pin; /* Part identification number */	122	unsigned short pin; /* Part identification number */
114	unsigned char prn; /* Part revision number */	123	unsigned char prn; /* Part revision number */
115	char *cpu_model;	124	char *cpu_model;
116		125
117	cir = mbar_readShort(MCF_CCM_CIR);	126	cir = mbar_readShort(MCF_CCM_CIR);
118	pin = cir >> MCF_CCM_CIR_PIN_LEN;	127	pin = cir >> MCF_CCM_CIR_PIN_LEN;
119	prn = cir & MCF_CCM_CIR_PRN_MASK;	128	prn = cir & MCF_CCM_CIR_PRN_MASK;
120		129
121	switch (pin) {	130	switch (pin) {
122	case MCF_CCM_CIR_PIN_MCF5270:	131	case MCF_CCM_CIR_PIN_MCF5270:
123	cpu_model = "5270";	132	cpu_model = "5270";
124	break;	133	break;
125	case MCF_CCM_CIR_PIN_MCF5271:	134	case MCF_CCM_CIR_PIN_MCF5271:
126	cpu_model = "5271";	135	cpu_model = "5271";
127	break;	136	break;
128	default:	137	default:
129	cpu_model = NULL;	138	cpu_model = NULL;
130	break;	139	break;
131	}	140	}
132		141
133	if (cpu_model)	142	if (cpu_model)
134	printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",	143	printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
135	cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));	144	cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
136	else	145	else
137	printf("CPU: Unknown - Freescale ColdFire MCF5271 family"	146	printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
138	" (PIN: 0x%x) rev. %hu, at %s MHz\n",	147	" (PIN: 0x%x) rev. %hu, at %s MHz\n",
139	pin, prn, strmhz(buf, CONFIG_SYS_CLK));	148	pin, prn, strmhz(buf, CONFIG_SYS_CLK));
140		149
141	return 0;	150	return 0;
142	}	151	}
143		152
144	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	153	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
145	{	154	{
146	/* Call the board specific reset actions first. */	155	/* Call the board specific reset actions first. */
147	if(board_reset) {	156	if(board_reset) {
148	board_reset();	157	board_reset();
149	}	158	}
150		159
151	mbar_writeByte(MCF_RCM_RCR,	160	mbar_writeByte(MCF_RCM_RCR,
152	MCF_RCM_RCR_SOFTRST \| MCF_RCM_RCR_FRCRSTOUT);	161	MCF_RCM_RCR_SOFTRST \| MCF_RCM_RCR_FRCRSTOUT);
153	return 0;	162	return 0;
154	};	163	};
155		164
156	#if defined(CONFIG_WATCHDOG)	165	#if defined(CONFIG_WATCHDOG)
157	void watchdog_reset(void)	166	void watchdog_reset(void)
158	{	167	{
159	mbar_writeShort(MCF_WTM_WSR, 0x5555);	168	mbar_writeShort(MCF_WTM_WSR, 0x5555);
160	mbar_writeShort(MCF_WTM_WSR, 0xAAAA);	169	mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
161	}	170	}
162		171
163	int watchdog_disable(void)	172	int watchdog_disable(void)
164	{	173	{
165	mbar_writeShort(MCF_WTM_WCR, 0);	174	mbar_writeShort(MCF_WTM_WCR, 0);
166	return (0);	175	return (0);
167	}	176	}
168		177
169	int watchdog_init(void)	178	int watchdog_init(void)
170	{	179	{
171	mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);	180	mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
172	return (0);	181	return (0);
173	}	182	}
174	#endif /* #ifdef CONFIG_WATCHDOG */	183	#endif /* #ifdef CONFIG_WATCHDOG */
175		184
176	#endif	185	#endif
177		186
178	#ifdef CONFIG_M5272	187	#ifdef CONFIG_M5272
179	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	188	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
180	{	189	{
181	volatile wdog_t wdp = (wdog_t ) (MMAP_WDOG);	190	wdog_t wdp = (wdog_t ) (MMAP_WDOG);
182		191
183	wdp->wdog_wrrr = 0;	192	out_be16(&wdp->wdog_wrrr, 0);
184	udelay(1000);	193	udelay(1000);
185		194
186	/* enable watchdog, set timeout to 0 and wait */	195	/* enable watchdog, set timeout to 0 and wait */
187	wdp->wdog_wrrr = 1;	196	out_be16(&wdp->wdog_wrrr, 1);
188	while (1) ;	197	while (1) ;
189		198
190	/* we don't return! */	199	/* we don't return! */
191	return 0;	200	return 0;
192	};	201	};
193		202
194	int checkcpu(void)	203	int checkcpu(void)
195	{	204	{
196	volatile sysctrl_t sysctrl = (sysctrl_t ) (MMAP_CFG);	205	sysctrl_t sysctrl = (sysctrl_t ) (MMAP_CFG);
197	uchar msk;	206	uchar msk;
198	char *suf;	207	char *suf;
199		208
200	puts("CPU: ");	209	puts("CPU: ");
201	msk = (sysctrl->sc_dir > 28) & 0xf;	210	msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
202	switch (msk) {	211	switch (msk) {
203	case 0x2:	212	case 0x2:
204	suf = "1K75N";	213	suf = "1K75N";
205	break;	214	break;
206	case 0x4:	215	case 0x4:
207	suf = "3K75N";	216	suf = "3K75N";
208	break;	217	break;
209	default:	218	default:
210	suf = NULL;	219	suf = NULL;
211	printf("Freescale MCF5272 (Mask:%01x)\n", msk);	220	printf("Freescale MCF5272 (Mask:%01x)\n", msk);
212	break;	221	break;
213	}	222	}
214		223
215	if (suf)	224	if (suf)
216	printf("Freescale MCF5272 %s\n", suf);	225	printf("Freescale MCF5272 %s\n", suf);
217	return 0;	226	return 0;
218	};	227	};
219		228
220	#if defined(CONFIG_WATCHDOG)	229	#if defined(CONFIG_WATCHDOG)
221	/* Called by macro WATCHDOG_RESET */	230	/* Called by macro WATCHDOG_RESET */
222	void watchdog_reset(void)	231	void watchdog_reset(void)
223	{	232	{
224	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	233	wdog_t wdt = (wdog_t )(MMAP_WDOG);
225	wdt->wdog_wcr = 0;	234
		235	out_be16(&wdt->wdog_wcr, 0);
226	}	236	}
227		237
228	int watchdog_disable(void)	238	int watchdog_disable(void)
229	{	239	{
230	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	240	wdog_t wdt = (wdog_t )(MMAP_WDOG);
231		241
232	wdt->wdog_wcr = 0; /* reset watchdog counter */	242	/* reset watchdog counter */
233	wdt->wdog_wirr = 0; /* disable watchdog interrupt */	243	out_be16(&wdt->wdog_wcr, 0);
234	wdt->wdog_wrrr = 0; /* disable watchdog timer */	244	/* disable watchdog interrupt */
		245	out_be16(&wdt->wdog_wirr, 0);
		246	/* disable watchdog timer */
		247	out_be16(&wdt->wdog_wrrr, 0);
235		248
236	puts("WATCHDOG:disabled\n");	249	puts("WATCHDOG:disabled\n");
237	return (0);	250	return (0);
238	}	251	}
239		252
240	int watchdog_init(void)	253	int watchdog_init(void)
241	{	254	{
242	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	255	wdog_t wdt = (wdog_t )(MMAP_WDOG);
243		256
244	wdt->wdog_wirr = 0; /* disable watchdog interrupt */	257	/* disable watchdog interrupt */
		258	out_be16(&wdt->wdog_wirr, 0);
245		259
246	/* set timeout and enable watchdog */	260	/* set timeout and enable watchdog */
247	wdt->wdog_wrrr =	261	out_be16(&wdt->wdog_wrrr,
248	((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;	262	(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
249	wdt->wdog_wcr = 0; /* reset watchdog counter */
250		263
		264	/* reset watchdog counter */
		265	out_be16(&wdt->wdog_wcr, 0);
		266
251	puts("WATCHDOG:enabled\n");	267	puts("WATCHDOG:enabled\n");
252	return (0);	268	return (0);
253	}	269	}
254	#endif /* #ifdef CONFIG_WATCHDOG */	270	#endif /* #ifdef CONFIG_WATCHDOG */
255		271
256	#endif /* #ifdef CONFIG_M5272 */	272	#endif /* #ifdef CONFIG_M5272 */
257		273
258	#ifdef CONFIG_M5275	274	#ifdef CONFIG_M5275
259	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	275	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
260	{	276	{
261	volatile rcm_t rcm = (rcm_t )(MMAP_RCM);	277	rcm_t rcm = (rcm_t )(MMAP_RCM);
262		278
263	udelay(1000);	279	udelay(1000);
264		280
265	rcm->rcr = RCM_RCR_SOFTRST;	281	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
266		282
267	/* we don't return! */	283	/* we don't return! */
268	return 0;	284	return 0;
269	};	285	};
270		286
271	int checkcpu(void)	287	int checkcpu(void)
272	{	288	{
273	char buf[32];	289	char buf[32];
274		290
275	printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",	291	printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
276	strmhz(buf, CONFIG_SYS_CLK));	292	strmhz(buf, CONFIG_SYS_CLK));
277	return 0;	293	return 0;
278	};	294	};
279		295
280		296
281	#if defined(CONFIG_WATCHDOG)	297	#if defined(CONFIG_WATCHDOG)
282	/* Called by macro WATCHDOG_RESET */	298	/* Called by macro WATCHDOG_RESET */
283	void watchdog_reset(void)	299	void watchdog_reset(void)
284	{	300	{
285	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	301	wdog_t wdt = (wdog_t )(MMAP_WDOG);
286	wdt->wsr = 0x5555;	302
287	wdt->wsr = 0xAAAA;	303	out_be16(&wdt->wsr, 0x5555);
		304	out_be16(&wdt->wsr, 0xaaaa);
288	}	305	}
289		306
290	int watchdog_disable(void)	307	int watchdog_disable(void)
291	{	308	{
292	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	309	wdog_t wdt = (wdog_t )(MMAP_WDOG);
293		310
294	wdt->wsr = 0x5555; /* reset watchdog counter */	311	/* reset watchdog counter */
295	wdt->wsr = 0xAAAA;	312	out_be16(&wdt->wsr, 0x5555);
296	wdt->wcr = 0; /* disable watchdog timer */	313	out_be16(&wdt->wsr, 0xaaaa);
297		314
		315	/* disable watchdog timer */
		316	out_be16(&wdt->wcr, 0);
		317
298	puts("WATCHDOG:disabled\n");	318	puts("WATCHDOG:disabled\n");
299	return (0);	319	return (0);
300	}	320	}
301		321
302	int watchdog_init(void)	322	int watchdog_init(void)
303	{	323	{
304	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);	324	wdog_t wdt = (wdog_t )(MMAP_WDOG);
305		325
306	wdt->wcr = 0; /* disable watchdog */	326	/* disable watchdog */
		327	out_be16(&wdt->wcr, 0);
307		328
308	/* set timeout and enable watchdog */	329	/* set timeout and enable watchdog */
309	wdt->wmr =	330	out_be16(&wdt->wmr,
310	((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;	331	(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
311	wdt->wsr = 0x5555; /* reset watchdog counter */	332
312	wdt->wsr = 0xAAAA;	333	/* reset watchdog counter */
		334	out_be16(&wdt->wsr, 0x5555);
		335	out_be16(&wdt->wsr, 0xaaaa);
313		336
314	puts("WATCHDOG:enabled\n");	337	puts("WATCHDOG:enabled\n");
315	return (0);	338	return (0);
316	}	339	}
317	#endif /* #ifdef CONFIG_WATCHDOG */	340	#endif /* #ifdef CONFIG_WATCHDOG */
318		341
319	#endif /* #ifdef CONFIG_M5275 */	342	#endif /* #ifdef CONFIG_M5275 */
320		343
321	#ifdef CONFIG_M5282	344	#ifdef CONFIG_M5282
322	int checkcpu(void)	345	int checkcpu(void)
323	{	346	{
324	unsigned char resetsource = MCFRESET_RSR;	347	unsigned char resetsource = MCFRESET_RSR;
325		348
326	printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",	349	printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
327	MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);	350	MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
328	printf("Reset:%s%s%s%s%s%s%s\n",	351	printf("Reset:%s%s%s%s%s%s%s\n",
329	(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",	352	(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
330	(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",	353	(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
331	(resetsource & MCFRESET_RSR_EXT) ? " External" : "",	354	(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
332	(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",	355	(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
333	(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",	356	(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
334	(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",	357	(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
335	(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");	358	(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
336	return 0;	359	return 0;
337	}	360	}
338		361
339	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	362	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
340	{	363	{
341	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;	364	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
342	return 0;	365	return 0;
343	};	366	};
344	#endif	367	#endif
345		368
346	#ifdef CONFIG_M5249	369	#ifdef CONFIG_M5249
347	int checkcpu(void)	370	int checkcpu(void)
348	{	371	{
349	char buf[32];	372	char buf[32];
350		373
351	printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",	374	printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
352	strmhz(buf, CONFIG_SYS_CLK));	375	strmhz(buf, CONFIG_SYS_CLK));
353	return 0;	376	return 0;
354	}	377	}
355		378
356	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	379	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
357	{	380	{
358	/* enable watchdog, set timeout to 0 and wait */	381	/* enable watchdog, set timeout to 0 and wait */
359	mbar_writeByte(MCFSIM_SYPCR, 0xc0);	382	mbar_writeByte(MCFSIM_SYPCR, 0xc0);
360	while (1) ;	383	while (1) ;
361		384
362	/* we don't return! */	385	/* we don't return! */
363	return 0;	386	return 0;
364	};	387	};
365	#endif	388	#endif
366		389
367	#ifdef CONFIG_M5253	390	#ifdef CONFIG_M5253
368	int checkcpu(void)	391	int checkcpu(void)
369	{	392	{
370	char buf[32];	393	char buf[32];
371		394
372	unsigned char resetsource = mbar_readLong(SIM_RSR);	395	unsigned char resetsource = mbar_readLong(SIM_RSR);
373	printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",	396	printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
374	strmhz(buf, CONFIG_SYS_CLK));	397	strmhz(buf, CONFIG_SYS_CLK));
375		398
376	if ((resetsource & SIM_RSR_HRST) \|\| (resetsource & SIM_RSR_SWTR)) {	399	if ((resetsource & SIM_RSR_HRST) \|\| (resetsource & SIM_RSR_SWTR)) {
377	printf("Reset:%s%s\n",	400	printf("Reset:%s%s\n",
378	(resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"	401	(resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
379	: "",	402	: "",
380	(resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :	403	(resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
381	"");	404	"");
382	}	405	}
383	return 0;	406	return 0;
384	}	407	}
385		408
386	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])	409	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
387	{	410	{
388	/* enable watchdog, set timeout to 0 and wait */	411	/* enable watchdog, set timeout to 0 and wait */
389	mbar_writeByte(SIM_SYPCR, 0xc0);	412	mbar_writeByte(SIM_SYPCR, 0xc0);
390	while (1) ;	413	while (1) ;
391		414
392	/* we don't return! */	415	/* we don't return! */
393	return 0;	416	return 0;
394	};	417	};
395	#endif	418	#endif
396		419
397	#if defined(CONFIG_MCFFEC)	420	#if defined(CONFIG_MCFFEC)
398	/* Default initializations for MCFFEC controllers. To override,	421	/* Default initializations for MCFFEC controllers. To override,
399	* create a board-specific function called:	422	* create a board-specific function called:
400	* int board_eth_init(bd_t *bis)	423	* int board_eth_init(bd_t *bis)
401	*/	424	*/
402		425
403	int cpu_eth_init(bd_t *bis)	426	int cpu_eth_init(bd_t *bis)
404	{	427	{
405	return mcffec_initialize(bis);	428	return mcffec_initialize(bis);

arch/m68k/cpu/mcf52x2/cpu_init.c

Diff comments View file @ 32dbaaf

 /*
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
  * MCF5282 additionals
  * (C) Copyright 2005
  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  * (c) Copyright 2010
  * Arcturus Networks Inc. <www.arcturusnetworks.com>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * MCF5275 additions
  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
 #include <net.h>
 #include <asm/fec.h>
 #endif
 #ifndef CONFIG_M5272
 /* Only 5272 Flexbus chipselect is different from the rest */
 void init_fbcs(void)
 {
-	volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+	fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
      && defined(CONFIG_SYS_CS6_CTRL))
-	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
+	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
-	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
+	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
-	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
      && defined(CONFIG_SYS_CS7_CTRL))
-	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
+	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
-	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
+	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
-	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif
 }
 #endif
 #if defined(CONFIG_M5208)
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 #ifndef CONFIG_WATCHDOG
-	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+	wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 	/* Disable the watchdog if we aren't using it */
-	wdg->cr = 0;
+	out_be16(&wdg->cr, 0);
 #endif
-	scm1->mpr = 0x77777777;
+	out_be32(&scm1->mpr, 0x77777777);
-	scm1->pacra = 0;
+	out_be32(&scm1->pacra, 0);
-	scm1->pacrb = 0;
+	out_be32(&scm1->pacrb, 0);
-	scm1->pacrc = 0;
+	out_be32(&scm1->pacrc, 0);
-	scm1->pacrd = 0;
+	out_be32(&scm1->pacrd, 0);
-	scm1->pacre = 0;
+	out_be32(&scm1->pacre, 0);
-	scm1->pacrf = 0;
+	out_be32(&scm1->pacrf, 0);
 	/* FlexBus Chipselect */
 	init_fbcs();
 	icache_enable();
 }
 /* initialize higher level parts of CPU like timers */
 int cpu_init_r(void)
 {
 	return (0);
 }
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
-		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 		break;
 	case 1:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
-		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-		gpio->par_timer &=
+		clrbits_8(&gpio->par_timer,
-		    (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
+			~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
-		gpio->par_timer |=
+		setbits_8(&gpio->par_timer,
-		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+			GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
+		clrbits_8(&gpio->par_feci2c,
-		    (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
+			~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
-		gpio->par_feci2c |=
+		setbits_8(&gpio->par_feci2c,
-		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+			GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
+		clrbits_8(&gpio->par_feci2c,
-		    (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
+			~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
-		gpio->par_feci2c |=
+		setbits_8(&gpio->par_feci2c,
-		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+			GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
 		break;
 	}
 }
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	if (setclear) {
-		gpio->par_fec |=
+		setbits_8(&gpio->par_fec,
-		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
-		gpio->par_feci2c |=
+		setbits_8(&gpio->par_feci2c,
-		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+			GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
 	} else {
-		gpio->par_fec &=
+		clrbits_8(&gpio->par_fec,
-		    (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
+			~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
-		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
+		clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
 	}
 	return 0;
 }
 #endif				/* CONFIG_CMD_NET */
 #endif				/* CONFIG_M5208 */
 #if defined(CONFIG_M5253)
 /*
  * Breath some life into the CPU...
  *
  * Set up the memory map,
  * initialize a bunch of registers,
  * initialize the UPM's
  */
 void cpu_init_f(void)
 {
 	mbar_writeByte(MCFSIM_MPARK, 0x40);	/* 5249 Internal Core takes priority over DMA */
 	mbar_writeByte(MCFSIM_SYPCR, 0x00);
 	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 	mbar_writeByte(MCFSIM_SWSR, 0x00);
 	mbar_writeByte(MCFSIM_SWDICR, 0x00);
 	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 	mbar_writeByte(MCFSIM_I2CICR, 0x00);
 	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 	mbar_writeByte(MCFSIM_ICR6, 0x00);
 	mbar_writeByte(MCFSIM_ICR7, 0x00);
 	mbar_writeByte(MCFSIM_ICR8, 0x00);
 	mbar_writeByte(MCFSIM_ICR9, 0x00);
 	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
 	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
 	/* FlexBus Chipselect */
 	init_fbcs();
 #ifdef CONFIG_FSL_I2C
 	CONFIG_SYS_I2C_PINMUX_REG =
 	    CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
 	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 #ifdef CONFIG_SYS_I2C2_OFFSET
 	CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
 	CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
 #endif
 #endif
 	/* enable instruction cache now */
 	icache_enable();
 }
 /*initialize higher level parts of CPU like timers */
 int cpu_init_r(void)
 {
 	return (0);
 }
 void uart_port_conf(int port)
 {
-	volatile u32 *par = (u32 *) MMAP_PAR;
+	u32 *par = (u32 *) MMAP_PAR;
 	/* Setup Ports: */
 	switch (port) {
 	case 1:
-		*par &= 0xFFE7FFFF;
+		clrbits_be32(par, 0x00180000);
-		*par |= 0x00180000;
+		setbits_be32(par, 0x00180000);
 		break;
 	case 2:
-		*par &= 0xFFFFFFFC;
+		clrbits_be32(par, 0x00000003);
-		*par &= 0x00000003;
+		clrbits_be32(par, 0xFFFFFFFC);
 		break;
 	}
 }
 #endif				/* #if defined(CONFIG_M5253) */
 #if defined(CONFIG_M5271)
 void cpu_init_f(void)
 {
 #ifndef CONFIG_WATCHDOG
 	/* Disable the watchdog if we aren't using it */
 	mbar_writeShort(MCF_WTM_WCR, 0);
 #endif
 	/* FlexBus Chipselect */
 	init_fbcs();
 #ifdef CONFIG_SYS_MCF_SYNCR
 	/* Set clockspeed according to board header file */
 	mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
 #else
 	/* Set clockspeed to 100MHz */
 	mbar_writeLong(MCF_FMPLL_SYNCR,
 			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
 #endif
 	while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
 }
 /*
  * initialize higher level parts of CPU like timers
  */
 int cpu_init_r(void)
 {
 	return (0);
 }
 void uart_port_conf(int port)
 {
 	u16 temp;
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
 		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
 		temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
 		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 		break;
 	case 1:
 		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
 		temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
 		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 		break;
 	case 2:
 		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
 		temp |= (0x3000);
 		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 		break;
 	}
 }
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	if (setclear) {
 		/* Enable Ethernet pins */
 		mbar_writeByte(MCF_GPIO_PAR_FECI2C,
 			       (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
 	} else {
 	}
 	return 0;
 }
 #endif				/* CONFIG_CMD_NET */
 #endif
 #if defined(CONFIG_M5272)
 /*
  * Breath some life into the CPU...
  *
  * Set up the memory map,
  * initialize a bunch of registers,
  * initialize the UPM's
  */
 void cpu_init_f(void)
 {
 	/* if we come from RAM we assume the CPU is
 	 * already initialized.
 	 */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+	sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
-	volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+	gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
-	volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
+	csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
-	sysctrl->sc_scr = CONFIG_SYS_SCR;
+	out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
-	sysctrl->sc_spr = CONFIG_SYS_SPR;
+	out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
 	/* Setup Ports: */
-	gpio->gpio_pacnt = CONFIG_SYS_PACNT;
+	out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
-	gpio->gpio_paddr = CONFIG_SYS_PADDR;
+	out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
-	gpio->gpio_padat = CONFIG_SYS_PADAT;
+	out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
-	gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
+	out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
-	gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
+	out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
-	gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
+	out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
-	gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
+	out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
 	/* Memory Controller: */
-	csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
+	out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
-	csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
+	out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
-	csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
+	out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
-	csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
+	out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
 #endif
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-	csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
+	out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
-	csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
+	out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
 #endif
 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
-	csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
+	out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
-	csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
+	out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
 #endif
 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
-	csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
+	out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
-	csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
+	out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
 #endif
 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
-	csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
+	out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
-	csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
+	out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
 #endif
 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
-	csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
+	out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
-	csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
+	out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
 #endif
 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
-	csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
+	out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
-	csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
+	out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
 #endif
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 	/* enable instruction cache now */
 	icache_enable();
 }
 /*
  * initialize higher level parts of CPU like timers
  */
 int cpu_init_r(void)
 {
 	return (0);
 }
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+		clrbits_be32(&gpio->gpio_pbcnt,
-		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+			GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 		break;
 	case 1:
-		gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+		clrbits_be32(&gpio->gpio_pdcnt,
-		gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+			GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+		setbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 		break;
 	}
 }
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	if (setclear) {
-		gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+		setbits_be32(&gpio->gpio_pbcnt,
-				    GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+			GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
-				    GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+			GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
-				    GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+			GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+			GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
 	} else {
 	}
 	return 0;
 }
 #endif				/* CONFIG_CMD_NET */
 #endif				/* #if defined(CONFIG_M5272) */
 #if defined(CONFIG_M5275)
 /*
  * Breathe some life into the CPU...
  *
  * Set up the memory map,
  * initialize a bunch of registers,
  * initialize the UPM's
  */
 void cpu_init_f(void)
 {
 	/*
 	 * if we come from RAM we assume the CPU is
 	 * already initialized.
 	 */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
-	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+	gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 	/* Kill watchdog so we can initialize the PLL */
-	wdog_reg->wcr = 0;
+	out_be16(&wdog_reg->wcr, 0);
 	/* FlexBus Chipselect */
 	init_fbcs();
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 #ifdef CONFIG_FSL_I2C
 	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
 	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 #endif
 	/* enable instruction cache now */
 	icache_enable();
 }
 /*
  * initialize higher level parts of CPU like timers
  */
 int cpu_init_r(void)
 {
 	return (0);
 }
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= ~UART0_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
-		gpio->par_uart |= UART0_ENABLE_MASK;
+		setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
 		break;
 	case 1:
-		gpio->par_uart &= ~UART1_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
-		gpio->par_uart |= UART1_ENABLE_MASK;
+		setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
 		break;
 	case 2:
-		gpio->par_uart &= ~UART2_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
-		gpio->par_uart |= UART2_ENABLE_MASK;
+		setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
 		break;
 	}
 }
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
-	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 	if (setclear) {
 		/* Enable Ethernet pins */
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c |= 0x0F00;
+			setbits_be16(&gpio->par_feci2c, 0x0f00);
-			gpio->par_fec0hl |= 0xC0;
+			setbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c |= 0x00A0;
+			setbits_be16(&gpio->par_feci2c, 0x00a0);
-			gpio->par_fec1hl |= 0xC0;
+			setbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	} else {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c &= ~0x0F00;
+			clrbits_be16(&gpio->par_feci2c, 0x0f00);
-			gpio->par_fec0hl &= ~0xC0;
+			clrbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c &= ~0x00A0;
+			clrbits_be16(&gpio->par_feci2c, 0x00a0);
-			gpio->par_fec1hl &= ~0xC0;
+			clrbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	}
 	return 0;
 }
 #endif				/* CONFIG_CMD_NET */
 #endif				/* #if defined(CONFIG_M5275) */
 #if defined(CONFIG_M5282)
 /*
  * Breath some life into the CPU...
  *
  * Set up the memory map,
  * initialize a bunch of registers,
  * initialize the UPM's
  */
 void cpu_init_f(void)
 {
 #ifndef CONFIG_WATCHDOG
 	/* disable watchdog if we aren't using it */
 	MCFWTM_WCR = 0;
 #endif
 #ifndef CONFIG_MONITOR_IS_IN_RAM
 	/* Set speed /PLL */
 	MCFCLOCK_SYNCR =
 	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
 	    MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
 	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 	MCFGPIO_PBCDPAR = 0xc0;
 	/* Set up the GPIO ports */
 #ifdef CONFIG_SYS_PEPAR
 	MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
 #endif
 #ifdef	CONFIG_SYS_PFPAR
 	MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
 #endif
 #ifdef CONFIG_SYS_PJPAR
 	MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
 #endif
 #ifdef CONFIG_SYS_PSDPAR
 	MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
 #endif
 #ifdef CONFIG_SYS_PASPAR
 	MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
 #endif
 #ifdef CONFIG_SYS_PEHLPAR
 	MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 #endif
 #ifdef CONFIG_SYS_PQSPAR
 	MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
 #endif
 #ifdef CONFIG_SYS_PTCPAR
 	MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
 #endif
 #if defined(CONFIG_SYS_PORTTC)
 	MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
 #endif
 #if defined(CONFIG_SYS_DDRTC)
 	MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
 #endif
 #ifdef CONFIG_SYS_PTDPAR
 	MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 #endif
 #ifdef CONFIG_SYS_PUAPAR
 	MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
 #endif
 #if defined(CONFIG_SYS_DDRD)
 	MCFGPIO_DDRD = CONFIG_SYS_DDRD;
 #endif
 #ifdef CONFIG_SYS_DDRUA
 	MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 #endif
 	/* FlexBus Chipselect */
 	init_fbcs();
 #endif				/* CONFIG_MONITOR_IS_IN_RAM */
 	/* defer enabling cache until boot (see do_go) */
 	/* icache_enable(); */
 }
 /*
  * initialize higher level parts of CPU like timers
  */
 int cpu_init_r(void)
 {
 	return (0);
 }
 void uart_port_conf(int port)
 {
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
 		MCFGPIO_PUAPAR &= 0xFc;
 		MCFGPIO_PUAPAR |= 0x03;
 		break;
 	case 1:
 		MCFGPIO_PUAPAR &= 0xF3;
 		MCFGPIO_PUAPAR |= 0x0C;
 		break;
 	case 2:
 		MCFGPIO_PASPAR &= 0xFF0F;
 		MCFGPIO_PASPAR |= 0x00A0;
 		break;
 	}
 }
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	if (setclear) {
 		MCFGPIO_PASPAR |= 0x0F00;
 		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 	} else {
 		MCFGPIO_PASPAR &= 0xF0FF;
 		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
 	}
 	return 0;
 }
 #endif			/* CONFIG_CMD_NET */
 #endif
 #if defined(CONFIG_M5249)
 /*
  * Breath some life into the CPU...
  *
  * Set up the memory map,
  * initialize a bunch of registers,
  * initialize the UPM's
  */
 void cpu_init_f(void)
 {
 	/*
 	 *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
 	 *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
 	 *        which is their primary function.
 	 *        ~Jeremy
 	 */
 	mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
 	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
 	mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
 	mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
 	mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
 	mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
 	/*
 	 *  dBug Compliance:
 	 *    You can verify these values by using dBug's 'ird'
 	 *    (Internal Register Display) command
 	 *    ~Jeremy
 	 *
 	 */
 	mbar_writeByte(MCFSIM_MPARK, 0x30);	/* 5249 Internal Core takes priority over DMA */
 	mbar_writeByte(MCFSIM_SYPCR, 0x00);
 	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 	mbar_writeByte(MCFSIM_SWSR, 0x00);
 	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
 	mbar_writeByte(MCFSIM_SWDICR, 0x00);
 	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 	mbar_writeByte(MCFSIM_I2CICR, 0x00);
 	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 	mbar_writeByte(MCFSIM_ICR6, 0x00);
 	mbar_writeByte(MCFSIM_ICR7, 0x00);
 	mbar_writeByte(MCFSIM_ICR8, 0x00);
 	mbar_writeByte(MCFSIM_ICR9, 0x00);
 	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
 	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);	/* Enable a 1 cycle pre-drive cycle on CS1 */
 	/* Setup interrupt priorities for gpio7 */
 	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
 	/* IDE Config registers */
 	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
 	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
 	/* FlexBus Chipselect */
 	init_fbcs();
 	/* enable instruction cache now */
 	icache_enable();
 }
 /*
  * initialize higher level parts of CPU like timers
  */
 int cpu_init_r(void)
 {
 	return (0);
 }
 void uart_port_conf(int port)
 {
 }
 #endif				/* #if defined(CONFIG_M5249) */

arch/m68k/cpu/mcf52x2/interrupts.c

Diff comments View file @ 32dbaaf

 /*
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 #ifdef	CONFIG_M5272
 int interrupt_init(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+	intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
 	/* disable all external interrupts */
-	intp->int_icr1 = 0x88888888;
+	out_be32(&intp->int_icr1, 0x88888888);
-	intp->int_icr2 = 0x88888888;
+	out_be32(&intp->int_icr2, 0x88888888);
-	intp->int_icr3 = 0x88888888;
+	out_be32(&intp->int_icr3, 0x88888888);
-	intp->int_icr4 = 0x88888888;
+	out_be32(&intp->int_icr4, 0x88888888);
-	intp->int_pitr = 0x00000000;
+	out_be32(&intp->int_pitr, 0x00000000);
 	/* initialize vector register */
-	intp->int_pivr = 0x40;
+	out_8(&intp->int_pivr, 0x40);
 	enable_interrupts();
 	return 0;
 }
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+	intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
-	intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
+	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
-	intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
+	setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 	/* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
-	intp->imrl0 = 0xFFFFFFFF;
+	out_be32(&intp->imrl0, 0xffffffff);
-	intp->imrh0 = 0xFFFFFFFF;
+	out_be32(&intp->imrh0, 0xffffffff);
 #else
-	intp->imrl0 |= 0x1;
+	setbits_be32(&intp->imrl0, 0x1);
 #endif
 	enable_interrupts();
 	return 0;
 }
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
-	intp->imrl0 &= 0xFFFFFFFE;
+	clrbits_be32(&intp->imrl0, 0x00000001);
-	intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 int interrupt_init(void)
 {
 	enable_interrupts();
 	return 0;
 }
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
 	mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */

arch/m68k/cpu/mcf52x2/speed.c

Diff comments View file @ 32dbaaf

 /*
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 DECLARE_GLOBAL_DATA_PTR;
 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks (void)
 {
 #if defined(CONFIG_M5208)
-	volatile pll_t *pll = (pll_t *) MMAP_PLL;
+	pll_t *pll = (pll_t *) MMAP_PLL;
-	pll->odr = CONFIG_SYS_PLL_ODR;
+	out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
-	pll->fdr = CONFIG_SYS_PLL_FDR;
+	out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
 #endif
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
 	unsigned long pllcr;
 #ifndef CONFIG_SYS_PLL_BYPASS
 #ifdef CONFIG_M5249
 	/* Setup the PLL to run at the specified speed */
 #ifdef CONFIG_SYS_FAST_CLK
 	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
 #else
 	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
 #endif
 #endif				/* CONFIG_M5249 */
 #ifdef CONFIG_M5253
 	pllcr = CONFIG_SYS_PLLCR;
 #endif				/* CONFIG_M5253 */
 	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
 	mbar2_writeLong(MCFSIM_PLLCR, cpll);	/* Set the PLL to bypass mode (PSTCLK = crystal) */
 	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* set the clock speed */
 	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
 	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
 	udelay(0x20);		/* Wait for a lock ... */
 #endif				/* #ifndef CONFIG_SYS_PLL_BYPASS */
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
 #if defined(CONFIG_M5275)
-	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
 	/* Setup PLL */
-	pll->syncr = 0x01080000;
+	out_be32(&pll->syncr, 0x01080000);
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
 		;
-	pll->syncr = 0x01000000;
+	out_be32(&pll->syncr, 0x01000000);
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
 		;
 #endif
 	gd->cpu_clk = CONFIG_SYS_CLK;
 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
 	gd->bus_clk = gd->cpu_clk;
 #endif
 #ifdef CONFIG_FSL_I2C
 	gd->i2c1_clk = gd->bus_clk;
 #ifdef CONFIG_SYS_I2C2_OFFSET
 	gd->i2c2_clk = gd->bus_clk;
 #endif
 #endif
 	return (0);
 }

board/freescale/m5208evbe/m5208evbe.c

Diff comments View file @ 32dbaaf

 /*
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <config.h>
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
 	puts("Board: ");
 	puts("Freescale M5208EVBe\n");
 	return 0;
 };
 phys_size_t initdram(int board_type)
 {
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
 	}
 	i--;
-	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
 #ifdef CONFIG_SYS_SDRAM_BASE1
-	sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
 #endif
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 	udelay(500);
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 	asm("nop");
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 	asm("nop");
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
 	asm("nop");
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
 	asm("nop");
 	udelay(100);
 	return dramsize;
 };
 int testdram(void)
 {
 	/* TODO: XXX XXX XXX */
 	printf("DRAM test not implemented!\n");
 	return (0);
 }

board/freescale/m5253demo/m5253demo.c

Diff comments View file @ 32dbaaf

 /*
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <asm/immap.h>
 #include <netdev.h>
 #include <asm/io.h>
 int checkboard(void)
 {
 	puts("Board: ");
 	puts("Freescale MCF5253 DEMO\n");
 	return 0;
 };
 phys_size_t initdram(int board_type)
 {
 	u32 dramsize = 0;
 	/*
 	 * Check to see if the SDRAM has already been initialized
 	 * by a run control tool
 	 */
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
 		u32 RC, temp;
 		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
 		/* Initialize DRAM Control Register: DCR */
 		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
 		__asm__("nop");
 		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
 		__asm__("nop");
 		/* Initialize DMR0 */
 		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
 		temp = (dramsize - 1) & 0xFFFC0000;
 		mbar_writeLong(MCFSIM_DMR0, temp | 1);
 		__asm__("nop");
 		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
 		mb();
 		__asm__("nop");
 		/* Write to this block to initiate precharge */
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
 		mb();
 		__asm__("nop");
 		/* Set RE bit in DACR */
 		mbar_writeLong(MCFSIM_DACR0,
 			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
 		__asm__("nop");
 		/* Wait for at least 8 auto refresh cycles to occur */
 		udelay(500);
 		/* Finish the configuration by issuing the MRS */
 		mbar_writeLong(MCFSIM_DACR0,
 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
 		__asm__("nop");
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 		mb();
 	}
 	return dramsize;
 }
 int testdram(void)
 {
 	/* TODO: XXX XXX XXX */
 	printf("DRAM test not implemented!\n");
 	return (0);
 }
 #ifdef CONFIG_CMD_IDE
 #include <ata.h>
 int ide_preinit(void)
 {
 	return (0);
 }
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
 	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
 	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
 	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
 	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
 	};
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(100);
 	} else {
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 #define CALC_TIMING(t) (t + period - 1) / period
 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
-		ata->t2w = CALC_TIMING(piotms[2][1]);
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
-		ata->t2r = CALC_TIMING(piotms[2][1]);
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
-		ata->ta = CALC_TIMING(piotms[2][8]);
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
-		ata->trd = CALC_TIMING(piotms[2][7]);
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
-		ata->t4 = CALC_TIMING(piotms[2][3]);
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
-		ata->t9 = CALC_TIMING(piotms[2][6]);
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
-		ata->cr = 0x40;	/* IORDY enable */
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(2000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif				/* CONFIG_CMD_IDE */
 #ifdef CONFIG_DRIVER_DM9000
 int board_eth_init(bd_t *bis)
 {
 	return dm9000_initialize(bis);
 }
 #endif

board/freescale/m5253evbe/m5253evbe.c

Diff comments View file @ 32dbaaf

 /*
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 int checkboard(void)
 {
 	puts("Board: ");
 	puts("Freescale MCF5253 EVBE\n");
 	return 0;
 };
 phys_size_t initdram(int board_type)
 {
 	/*
 	 * Check to see if the SDRAM has already been initialized
 	 * by a run control tool
 	 */
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
 		u32 RC, dramsize;
 		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
 		/* Initialize DRAM Control Register: DCR */
 		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
 		asm("nop");
 		mbar_writeLong(MCFSIM_DACR0, 0x00002320);
 		asm("nop");
 		/* Initialize DMR0 */
 		dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
 		mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
 		asm("nop");
 		mbar_writeLong(MCFSIM_DACR0, 0x00002328);
 		asm("nop");
 		/* Write to this block to initiate precharge */
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
 		asm("nop");
 		/* Set RE bit in DACR */
 		mbar_writeLong(MCFSIM_DACR0,
 			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
 		asm("nop");
 		/* Wait for at least 8 auto refresh cycles to occur */
 		udelay(500);
 		/* Finish the configuration by issuing the MRS */
 		mbar_writeLong(MCFSIM_DACR0,
 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
 		asm("nop");
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 	}
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 int testdram(void)
 {
 	/* TODO: XXX XXX XXX */
 	printf("DRAM test not implemented!\n");
 	return (0);
 }
 #ifdef CONFIG_CMD_IDE
 #include <ata.h>
 int ide_preinit(void)
 {
 	return (0);
 }
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
 	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
 	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
 	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
 	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
 	};
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(100);
 	} else {
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 #define CALC_TIMING(t) (t + period - 1) / period
 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
-		ata->t2w = CALC_TIMING(piotms[2][1]);
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
-		ata->t2r = CALC_TIMING(piotms[2][1]);
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
-		ata->ta = CALC_TIMING(piotms[2][8]);
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
-		ata->trd = CALC_TIMING(piotms[2][7]);
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
-		ata->t4 = CALC_TIMING(piotms[2][3]);
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
-		ata->t9 = CALC_TIMING(piotms[2][6]);
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
-		ata->cr = 0x40;	/* IORDY enable */
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(2000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif				/* CONFIG_CMD_IDE */

board/freescale/m5272c3/m5272c3.c

Diff comments View file @ 32dbaaf

 /*
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 int checkboard (void) {
 	puts ("Board: ");
 	puts ("Freescale MCF5272C3 EVB\n");
 	return 0;
 	};
 phys_size_t initdram (int board_type) {
-	volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
-	sdp->sdram_sdtr = 0xf539;
+	out_be16(&sdp->sdram_sdtr, 0xf539);
-	sdp->sdram_sdcr = 0x4211;
+	out_be16(&sdp->sdram_sdcr, 0x4211);
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 	};
 int testdram (void) {
 	/* TODO: XXX XXX XXX */
 	printf ("DRAM test not implemented!\n");
 	return (0);
 }

board/freescale/m5275evb/m5275evb.c

Diff comments View file @ 32dbaaf

1	/*	1	/*
2	* (C) Copyright 2000-2003	2	* (C) Copyright 2000-2003
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)	5	* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
6	*	6	*
		7	* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
		8	*
7	* See file CREDITS for list of people who contributed to this	9	* See file CREDITS for list of people who contributed to this
8	* project.	10	* project.
9	*	11	*
10	* This program is free software; you can redistribute it and/or	12	* This program is free software; you can redistribute it and/or
11	* modify it under the terms of the GNU General Public License as	13	* modify it under the terms of the GNU General Public License as
12	* published by the Free Software Foundation; either version 2 of	14	* published by the Free Software Foundation; either version 2 of
13	* the License, or (at your option) any later version.	15	* the License, or (at your option) any later version.
14	*	16	*
15	* This program is distributed in the hope that it will be useful,	17	* This program is distributed in the hope that it will be useful,
16	* but WITHOUT ANY WARRANTY; without even the implied warranty of	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18	* GNU General Public License for more details.	20	* GNU General Public License for more details.
19	*	21	*
20	* You should have received a copy of the GNU General Public License	22	* You should have received a copy of the GNU General Public License
21	* along with this program; if not, write to the Free Software	23	* along with this program; if not, write to the Free Software
22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23	* MA 02111-1307 USA	25	* MA 02111-1307 USA
24	*/	26	*/
25		27
26	#include <common.h>	28	#include <common.h>
27	#include <asm/immap.h>	29	#include <asm/immap.h>
		30	#include <asm/io.h>
28		31
29	#define PERIOD 13 /* system bus period in ns */	32	#define PERIOD 13 /* system bus period in ns */
30	#define SDRAM_TREFI 7800 /* in ns */	33	#define SDRAM_TREFI 7800 /* in ns */
31		34
32	int checkboard(void)	35	int checkboard(void)
33	{	36	{
34	puts("Board: ");	37	puts("Board: ");
35	puts("Freescale MCF5275 EVB\n");	38	puts("Freescale MCF5275 EVB\n");
36	return 0;	39	return 0;
37	};	40	};
38		41
39	phys_size_t initdram(int board_type)	42	phys_size_t initdram(int board_type)
40	{	43	{
41	volatile sdramctrl_t sdp = (sdramctrl_t )(MMAP_SDRAM);	44	sdramctrl_t sdp = (sdramctrl_t )(MMAP_SDRAM);
42	volatile gpio_t gpio_reg = (gpio_t )(MMAP_GPIO);	45	gpio_t gpio_reg = (gpio_t )(MMAP_GPIO);
43		46
44	gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */	47	/* Enable SDRAM */
		48	out_be16(&gpio_reg->par_sdram, 0x3FF);
45		49
46	/* Set up chip select */	50	/* Set up chip select */
47	sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;	51	out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
48	sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M \| MCF_SDRAMC_SDMRn_V;	52	out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M \| MCF_SDRAMC_SDMRn_V);
49		53
50	/* Set up timing */	54	/* Set up timing */
51	sdp->sdcfg1 = 0x83711630;	55	out_be32(&sdp->sdcfg1, 0x83711630);
52	sdp->sdcfg2 = 0x46770000;	56	out_be32(&sdp->sdcfg2, 0x46770000);
53		57
54	/* Enable clock */	58	/* Enable clock */
55	sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN \| MCF_SDRAMC_SDCR_CKE;	59	out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN \| MCF_SDRAMC_SDCR_CKE);
56		60
57	/* Set precharge */	61	/* Set precharge */
58	sdp->sdcr \|= MCF_SDRAMC_SDCR_IPALL;	62	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
59		63
60	/* Dummy write to start SDRAM */	64	/* Dummy write to start SDRAM */
61	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;	65	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
62		66
63	/* Send LEMR */	67	/* Send LEMR */
64	sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR	68	setbits_be32(&sdp->sdmr,
65	\| MCF_SDRAMC_SDMR_AD(0x0)	69	MCF_SDRAMC_SDMR_BNKAD_LEMR \| MCF_SDRAMC_SDMR_AD(0x0) \|
66	\| MCF_SDRAMC_SDMR_CMD;	70	MCF_SDRAMC_SDMR_CMD);
67	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;	71	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
68		72
69	/* Send LMR */	73	/* Send LMR */
70	sdp->sdmr = 0x058d0000;	74	out_be32(&sdp->sdmr, 0x058d0000);
71	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;	75	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
72		76
73	/* Stop sending commands */	77	/* Stop sending commands */
74	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);	78	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
75		79
76	/* Set precharge */	80	/* Set precharge */
77	sdp->sdcr \|= MCF_SDRAMC_SDCR_IPALL;	81	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
78	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;	82	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
79		83
80	/* Stop manual precharge, send 2 IREF */	84	/* Stop manual precharge, send 2 IREF */
81	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);	85	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
82	sdp->sdcr \|= MCF_SDRAMC_SDCR_IREF;	86	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
83	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;	87	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
84	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;	88	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
85		89
86	/* Write mode register, clear reset DLL */	90
87	sdp->sdmr = 0x018d0000;	91	out_be32(&sdp->sdmr, 0x018d0000);
88	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;	92	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
89		93
90	/* Stop sending commands */	94	/* Stop sending commands */
91	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);	95	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
92	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);	96	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
93		97
94	/* Turn on auto refresh, lock SDMR */	98	/* Turn on auto refresh, lock SDMR */
95	sdp->sdcr =	99	out_be32(&sdp->sdcr,
96	MCF_SDRAMC_SDCR_CKE	100	MCF_SDRAMC_SDCR_CKE
97	\| MCF_SDRAMC_SDCR_REF	101	\| MCF_SDRAMC_SDCR_REF
98	\| MCF_SDRAMC_SDCR_MUX(1)	102	\| MCF_SDRAMC_SDCR_MUX(1)
99	/* 1 added to round up */	103	/* 1 added to round up */
100	\| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)	104	\| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
101	\| MCF_SDRAMC_SDCR_DQS_OE(0x3);	105	\| MCF_SDRAMC_SDCR_DQS_OE(0x3));
102		106
103	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;	107	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
104	};	108	};
105		109
106	int testdram(void)	110	int testdram(void)
107	{	111	{
108	/* TODO: XXX XXX XXX */	112	/* TODO: XXX XXX XXX */
109	printf("DRAM test not implemented!\n");	113	printf("DRAM test not implemented!\n");
110		114
111	return (0);	115	return (0);
112	}	116	}
113		117