Eric Lee / smarc-uboot

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Commit 353f36d96e49f3ad34ffc4a16dea7398c6f90f65

Authored by Yuantian Tang
Committed by Prabhakar Kushwaha
1 parent d4ad111dc4
Exists in smarc_8mq_lf_v2020.04 and in 10 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls1028ardb: Add support for LS1028ARDB 

LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Showing 13 changed files with 776 additions and 0 deletions Side-by-side Diff

... ... @@ -1262,6 +1262,17 @@
1262 1262 development platform that supports the QorIQ LS1012A
1263 1263 Layerscape Architecture processor.
1264 1264  
  1265 +config TARGET_LS1028ARDB
  1266 + bool "Support ls1028ardb"
  1267 + select ARCH_LS1028A
  1268 + select ARM64
  1269 + select ARMV8_MULTIENTRY
  1270 + help
  1271 + Support for Freescale LS1028ARDB platform
  1272 + The LS1028A Development System (RDB) is a high-performance
  1273 + development platform that supports the QorIQ LS1028A
  1274 + Layerscape Architecture processor.
  1275 +
1265 1276 config TARGET_LS1088ARDB
1266 1277 bool "Support ls1088ardb"
1267 1278 select ARCH_LS1088A
... ... @@ -1666,6 +1677,7 @@
1666 1677 source "board/freescale/ls2080aqds/Kconfig"
1667 1678 source "board/freescale/ls2080ardb/Kconfig"
1668 1679 source "board/freescale/ls1088a/Kconfig"
  1680 +source "board/freescale/ls1028a/Kconfig"
1669 1681 source "board/freescale/ls1021aqds/Kconfig"
1670 1682 source "board/freescale/ls1043aqds/Kconfig"
1671 1683 source "board/freescale/ls1021atwr/Kconfig"
arch/arm/cpu/armv8/Kconfig
Diff comments   View file @ 353f36d
... ... @@ -104,6 +104,7 @@
104 104 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
105 105 !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
106 106 !TARGET_LS1012AFRWY && \
  107 + !TARGET_LS1028ARDB && \
107 108 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
108 109 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
109 110 !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
arch/arm/dts/Makefile
Diff comments   View file @ 353f36d
... ... @@ -329,6 +329,7 @@
329 329 fsl-ls2088a-rdb-qspi.dtb \
330 330 fsl-ls1088a-rdb.dtb \
331 331 fsl-ls1088a-qds.dtb \
  332 + fsl-ls1028a-rdb.dtb \
332 333 fsl-lx2160a-rdb.dtb \
333 334 fsl-lx2160a-qds.dtb
334 335 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
arch/arm/dts/fsl-ls1028a-rdb.dts
Diff comments   View file @ 353f36d
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP ls1028ARDB device tree source
  4 + *
  5 + * Copyright 2019 NXP
  6 + *
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include "fsl-ls1028a.dtsi"
  12 +
  13 +/ {
  14 + model = "NXP Layerscape 1028a RDB Board";
  15 + compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
  16 +};
  17 +
  18 +&dspi0 {
  19 + status = "okay";
  20 +};
  21 +
  22 +&dspi1 {
  23 + status = "okay";
  24 +};
  25 +
  26 +&dspi2 {
  27 + status = "okay";
  28 +};
  29 +
  30 +&esdhc0 {
  31 + status = "okay";
  32 +};
  33 +
  34 +&esdhc1 {
  35 + status = "okay";
  36 +};
  37 +
  38 +&i2c0 {
  39 + status = "okay";
  40 +};
  41 +
  42 +&i2c1 {
  43 + status = "okay";
  44 +};
  45 +
  46 +&i2c2 {
  47 + status = "okay";
  48 +};
  49 +
  50 +&i2c3 {
  51 + status = "okay";
  52 +};
  53 +
  54 +&i2c4 {
  55 + status = "okay";
  56 +};
  57 +
  58 +&i2c5 {
  59 + status = "okay";
  60 +};
  61 +
  62 +&i2c6 {
  63 + status = "okay";
  64 +};
  65 +
  66 +&i2c7 {
  67 + status = "okay";
  68 +};
  69 +
  70 +&sata {
  71 + status = "okay";
  72 +};
  73 +
  74 +&serial0 {
  75 + status = "okay";
  76 +};
  77 +
  78 +&serial1 {
  79 + status = "okay";
  80 +};
  81 +
  82 +&usb1 {
  83 + status = "okay";
  84 +};
  85 +
  86 +&usb2 {
  87 + status = "okay";
  88 +};
board/freescale/ls1028a/Kconfig
Diff comments   View file @ 353f36d
  1 +if TARGET_LS1028ARDB
  2 +
  3 +config SYS_BOARD
  4 + default "ls1028a"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_SOC
  10 + default "fsl-layerscape"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "ls1028ardb"
  14 +
  15 +config EMMC_BOOT
  16 + bool "Support for booting from EMMC"
  17 + default n
  18 +
  19 +config SYS_TEXT_BASE
  20 + default 0x96000000 if SD_BOOT || EMMC_BOOT
  21 + default 0x82000000 if TFABOOT
  22 + default 0x20100000
  23 +
  24 +source "board/freescale/common/Kconfig"
  25 +
  26 +endif
board/freescale/ls1028a/MAINTAINERS
Diff comments   View file @ 353f36d
  1 +LS1028ARDB BOARD
  2 +M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
  3 +M: Rai Harninder <harninder.rai@nxp.com>
  4 +M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
  5 +M: Tang Yuantian <andy.tang@nxp.com>
  6 +S: Maintained
  7 +F: board/freescale/ls1028a/
  8 +F: include/configs/ls1028a_common.h
  9 +F: include/configs/ls1028ardb.h
  10 +F: configs/ls1028ardb_tfa_defconfig
board/freescale/ls1028a/Makefile
Diff comments   View file @ 353f36d
  1 +#
  2 +# Copyright 2019 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += ls1028a.o
  8 +obj-y += ddr.o
board/freescale/ls1028a/README
Diff comments   View file @ 353f36d
  1 +Overview
  2 +--------
  3 +The LS1028A Reference Design (RDB) is a high-performance computing,
  4 +evaluation, and development platform that supports ARM SoC LS1028A and its
  5 +derivatives.
  6 +
  7 +LS1028A SoC Overview
  8 +--------------------------------------
  9 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
  10 +
  11 +RDB Default Switch Settings (1: ON; 0: OFF)
  12 +-------------------------------------------
  13 +For XSPI NOR boot (default)
  14 +SW2: 1111_1000
  15 +SW3: 1111_0000
  16 +SW5: 0011_1001
  17 +
  18 +For SD Boot
  19 +SW2: 1000_1000
  20 +SW3: 1111_0000
  21 +SW5: 0011_1001
  22 +
  23 +For eMMC Boot
  24 +SW2: 1001_1000
  25 +SW3: 1111_0000
  26 +SW5: 0011_1001
  27 +
  28 +LS1028ARDB board Overview
  29 +-------------------------
  30 +Processor
  31 + Two Arm Cortex- A72 processor cores:
  32 + - Based on 64-bit ARMv8 architecture
  33 + - Up to 1.3 GHz operation
  34 + - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
  35 + data cache
  36 + - Arranged as a single cluster of two cores sharing a single 1 MB L2
  37 + cache
  38 +DDR memory
  39 + - Five onboard 1G x8 discrete memory modules (Four data byte lanes
  40 + ECC)
  41 + - 32-bit data and 4-bit ECC
  42 + - One chip select
  43 + - Data transfer rates of up to 1.6 GT/s
  44 + - Single-bit error correction and double-bit error detection ECC (4-bit
  45 + check word across 32-bit data)
  46 +High-speed serial ports(SerDes)
  47 + - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
  48 + Qualcomm AR8033 PHY
  49 + - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
  50 + through the NXP F104S8A PHY
  51 + - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
  52 + (8 Gbit/s) cards
  53 + - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
  54 + slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
  55 + SATA Gen 3 cards (6 Gbit/s) at a time
  56 +eSDHC
  57 + - eSDHC1, eSDHC2
  58 +SPI
  59 + - Connects to two mikroBUS sockets to support mikro-click modules,
  60 + such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
  61 + field communications (NFC) controller
  62 +Octal SPI (XSPI)
  63 + - One 256 MB onboard XSPI serial NOR flash memory
  64 + - One 512 MB onboard XSPI serial NAND flash memory
  65 + - Supports a QSPI emulator for offboard QSPI emulation
  66 +I2C
  67 + - All system devices are accessed via I2C1, which is multiplexed on
  68 + I2C multiplexer PCA9848 to isolate address conflicts and reduce
  69 + capacitive load
  70 + - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
  71 + thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
  72 + 1 and 2
  73 +CAN
  74 + - The two CAN DB9 ports can support CAN FD fast phase at data rates of
  75 + up to 5 Mbit/s
  76 +Serial audio interface(SAI)
  77 + - Audio codec SGTL5000 provides headphone and audio LINEOUT for
  78 + stereo speakers
  79 + - IEEE1588 interface to support audio on SAI4
board/freescale/ls1028a/ddr.c
Diff comments   View file @ 353f36d
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2019 NXP
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <fsl_ddr_sdram.h>
  8 +#include <fsl_ddr_dimm_params.h>
  9 +
  10 +DECLARE_GLOBAL_DATA_PTR;
  11 +
  12 +int fsl_initdram(void)
  13 +{
  14 + gd->ram_size = tfa_get_dram_size();
  15 +
  16 + if (!gd->ram_size)
  17 + gd->ram_size = fsl_ddr_sdram_size();
  18 +
  19 + return 0;
  20 +}
board/freescale/ls1028a/ls1028a.c
Diff comments   View file @ 353f36d
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2019 NXP
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <malloc.h>
  8 +#include <errno.h>
  9 +#include <fsl_ddr.h>
  10 +#include <asm/io.h>
  11 +#include <hwconfig.h>
  12 +#include <fdt_support.h>
  13 +#include <linux/libfdt.h>
  14 +#include <environment.h>
  15 +#include <asm/arch-fsl-layerscape/soc.h>
  16 +#include <i2c.h>
  17 +#include <asm/arch/soc.h>
  18 +#ifdef CONFIG_FSL_LS_PPA
  19 +#include <asm/arch/ppa.h>
  20 +#endif
  21 +#include <fsl_immap.h>
  22 +#include <netdev.h>
  23 +
  24 +#include <fdtdec.h>
  25 +#include <miiphy.h>
  26 +#include "../common/qixis.h"
  27 +
  28 +DECLARE_GLOBAL_DATA_PTR;
  29 +
  30 +int board_init(void)
  31 +{
  32 +#ifdef CONFIG_ENV_IS_NOWHERE
  33 + gd->env_addr = (ulong)&default_environment[0];
  34 +#endif
  35 +
  36 +#ifdef CONFIG_FSL_LS_PPA
  37 + ppa_init();
  38 +#endif
  39 +
  40 +#ifndef CONFIG_SYS_EARLY_PCI_INIT
  41 + pci_init();
  42 +#endif
  43 +
  44 +#if defined(CONFIG_TARGET_LS1028ARDB)
  45 + u8 val = I2C_MUX_CH_DEFAULT;
  46 +
  47 + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  48 +#endif
  49 + return 0;
  50 +}
  51 +
  52 +int board_eth_init(bd_t *bis)
  53 +{
  54 + return pci_eth_init(bis);
  55 +}
  56 +
  57 +int board_early_init_f(void)
  58 +{
  59 +#ifdef CONFIG_SYS_I2C_EARLY_INIT
  60 + i2c_early_init_f();
  61 +#endif
  62 +
  63 + fsl_lsch3_early_init_f();
  64 + return 0;
  65 +}
  66 +
  67 +void detail_board_ddr_info(void)
  68 +{
  69 + puts("\nDDR ");
  70 + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  71 + print_ddr_info(0);
  72 +}
  73 +
  74 +#ifdef CONFIG_OF_BOARD_SETUP
  75 +int ft_board_setup(void *blob, bd_t *bd)
  76 +{
  77 + u64 base[CONFIG_NR_DRAM_BANKS];
  78 + u64 size[CONFIG_NR_DRAM_BANKS];
  79 +
  80 + ft_cpu_setup(blob, bd);
  81 +
  82 + /* fixup DT for the two GPP DDR banks */
  83 + base[0] = gd->bd->bi_dram[0].start;
  84 + size[0] = gd->bd->bi_dram[0].size;
  85 + base[1] = gd->bd->bi_dram[1].start;
  86 + size[1] = gd->bd->bi_dram[1].size;
  87 +
  88 +#ifdef CONFIG_RESV_RAM
  89 + /* reduce size if reserved memory is within this bank */
  90 + if (gd->arch.resv_ram >= base[0] &&
  91 + gd->arch.resv_ram < base[0] + size[0])
  92 + size[0] = gd->arch.resv_ram - base[0];
  93 + else if (gd->arch.resv_ram >= base[1] &&
  94 + gd->arch.resv_ram < base[1] + size[1])
  95 + size[1] = gd->arch.resv_ram - base[1];
  96 +#endif
  97 +
  98 + fdt_fixup_memory_banks(blob, base, size, 2);
  99 +
  100 + return 0;
  101 +}
  102 +#endif
  103 +
  104 +#ifdef CONFIG_FSL_QIXIS
  105 +int checkboard(void)
  106 +{
  107 +#ifdef CONFIG_TFABOOT
  108 + enum boot_src src = get_boot_src();
  109 +#endif
  110 + u8 sw;
  111 +
  112 + int clock;
  113 + char *board;
  114 + char buf[64] = {0};
  115 + static const char *freq[6] = {"100.00", "125.00", "156.25",
  116 + "161.13", "322.26", "100.00 SS"};
  117 +
  118 + cpu_name(buf);
  119 + /* find the board details */
  120 + sw = QIXIS_READ(id);
  121 +
  122 + switch (sw) {
  123 + case 0x46:
  124 + board = "QDS";
  125 + break;
  126 + case 0x47:
  127 + board = "RDB";
  128 + break;
  129 + case 0x49:
  130 + board = "HSSI";
  131 + break;
  132 + default:
  133 + board = "unknown";
  134 + break;
  135 + }
  136 +
  137 + sw = QIXIS_READ(arch);
  138 + printf("Board: %s-%s, Version: %c, boot from ",
  139 + buf, board, (sw & 0xf) + 'A' - 1);
  140 +
  141 + sw = QIXIS_READ(brdcfg[0]);
  142 + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  143 +
  144 +#ifdef CONFIG_TFABOOT
  145 + if (src == BOOT_SOURCE_SD_MMC) {
  146 + puts("SD\n");
  147 + } else if (src == BOOT_SOURCE_SD_MMC2) {
  148 + puts("eMMC\n");
  149 + } else {
  150 +#endif
  151 +#ifdef CONFIG_SD_BOOT
  152 + puts("SD\n");
  153 +#elif defined(CONFIG_EMMC_BOOT)
  154 + puts("eMMC\n");
  155 +#else
  156 + switch (sw) {
  157 + case 0:
  158 + case 4:
  159 + printf("NOR\n");
  160 + break;
  161 + case 1:
  162 + printf("NAND\n");
  163 + break;
  164 + default:
  165 + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  166 + break;
  167 + }
  168 +#endif
  169 +#ifdef CONFIG_TFABOOT
  170 + }
  171 +#endif
  172 +
  173 + printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
  174 + puts("SERDES1 Reference : ");
  175 +
  176 + sw = QIXIS_READ(brdcfg[2]);
  177 +#ifdef CONFIG_TARGET_LS1028ARDB
  178 + clock = (sw >> 6) & 3;
  179 +#else
  180 + clock = (sw >> 4) & 0xf;
  181 +#endif
  182 +
  183 + printf("Clock1 = %sMHz ", freq[clock]);
  184 +#ifdef CONFIG_TARGET_LS1028ARDB
  185 + clock = (sw >> 4) & 3;
  186 +#else
  187 + clock = sw & 0xf;
  188 +#endif
  189 + printf("Clock2 = %sMHz\n", freq[clock]);
  190 +
  191 + return 0;
  192 +}
  193 +#endif
configs/ls1028ardb_tfa_defconfig
Diff comments   View file @ 353f36d
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1028ARDB=y
  3 +CONFIG_SYS_FSL_SDHC_CLK_DIV=1
  4 +CONFIG_TFABOOT=y
  5 +CONFIG_NR_DRAM_BANKS=2
  6 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
  7 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
  8 +CONFIG_AHCI=y
  9 +CONFIG_DISTRO_DEFAULTS=y
  10 +# CONFIG_SYS_MALLOC_F is not set
  11 +CONFIG_FIT_VERBOSE=y
  12 +CONFIG_OF_BOARD_SETUP=y
  13 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  14 +CONFIG_BOOTDELAY=10
  15 +CONFIG_USE_BOOTARGS=y
  16 +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
  17 +CONFIG_CMD_GREPENV=y
  18 +CONFIG_CMD_GPT=y
  19 +CONFIG_CMD_I2C=y
  20 +CONFIG_CMD_MMC=y
  21 +CONFIG_CMD_PCI=y
  22 +CONFIG_CMD_SF=y
  23 +CONFIG_CMD_USB=y
  24 +# CONFIG_CMD_SETEXPR is not set
  25 +CONFIG_CMD_CACHE=y
  26 +CONFIG_OF_CONTROL=y
  27 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
  28 +CONFIG_ENV_IS_IN_MMC=y
  29 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  30 +CONFIG_NET_RANDOM_ETHADDR=y
  31 +CONFIG_NETCONSOLE=y
  32 +CONFIG_DM=y
  33 +CONFIG_SCSI_AHCI=y
  34 +CONFIG_SATA_CEVA=y
  35 +CONFIG_FSL_CAAM=y
  36 +CONFIG_DM_MMC=y
  37 +CONFIG_DM_SPI_FLASH=y
  38 +CONFIG_SPI_FLASH=y
  39 +CONFIG_SPI_FLASH_SPANSION=y
  40 +CONFIG_SPI_FLASH_STMICRO=y
  41 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  42 +CONFIG_PHYLIB=y
  43 +CONFIG_PHY_ATHEROS=y
  44 +CONFIG_DM_ETH=y
  45 +CONFIG_PHY_GIGE=y
  46 +CONFIG_E1000=y
  47 +CONFIG_PCI=y
  48 +CONFIG_DM_PCI=y
  49 +CONFIG_DM_PCI_COMPAT=y
  50 +CONFIG_PCIE_LAYERSCAPE=y
  51 +CONFIG_SCSI=y
  52 +CONFIG_DM_SCSI=y
  53 +CONFIG_SYS_NS16550=y
  54 +CONFIG_SPI=y
  55 +CONFIG_DM_SPI=y
  56 +CONFIG_FSL_DSPI=y
  57 +CONFIG_USB=y
  58 +CONFIG_DM_USB=y
  59 +CONFIG_USB_XHCI_HCD=y
  60 +CONFIG_USB_XHCI_DWC3=y
  61 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
include/configs/ls1028a_common.h
Diff comments   View file @ 353f36d
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2019 NXP
  4 + */
  5 +
  6 +#ifndef __L1028A_COMMON_H
  7 +#define __L1028A_COMMON_H
  8 +
  9 +#define CONFIG_REMAKE_ELF
  10 +#define CONFIG_FSL_LAYERSCAPE
  11 +#define CONFIG_MP
  12 +
  13 +#include <asm/arch/stream_id_lsch3.h>
  14 +#include <asm/arch/config.h>
  15 +#include <asm/arch/soc.h>
  16 +
  17 +/* Link Definitions */
  18 +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  19 +
  20 +#define CONFIG_SKIP_LOWLEVEL_INIT
  21 +
  22 +#define CONFIG_VERY_BIG_RAM
  23 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  24 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  25 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  26 +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
  27 +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
  28 +
  29 +#define CONFIG_CMD_MEMTEST
  30 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  31 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
  32 +
  33 +/*
  34 + * SMP Definitinos
  35 + */
  36 +#define CPU_RELEASE_ADDR secondary_boot_func
  37 +
  38 +/* Generic Timer Definitions */
  39 +#define COUNTER_FREQUENCY 25000000 /* 25MHz */
  40 +
  41 +/* Size of malloc() pool */
  42 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  43 +
  44 +/* I2C */
  45 +#define CONFIG_SYS_I2C
  46 +
  47 +/* Serial Port */
  48 +#define CONFIG_CONS_INDEX 1
  49 +#define CONFIG_SYS_NS16550_SERIAL
  50 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  51 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  52 +
  53 +#define CONFIG_BAUDRATE 115200
  54 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  55 +
  56 +/* Miscellaneous configurable options */
  57 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  58 +
  59 +/* Physical Memory Map */
  60 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4
  61 +
  62 +#define CONFIG_HWCONFIG
  63 +#define HWCONFIG_BUFFER_SIZE 128
  64 +
  65 +/* Allow to overwrite serial and ethaddr */
  66 +#define CONFIG_ENV_OVERWRITE
  67 +
  68 +#define BOOT_TARGET_DEVICES(func) \
  69 + func(MMC, mmc, 0) \
  70 + func(USB, usb, 0)
  71 +#include <config_distro_bootcmd.h>
  72 +
  73 +/* Initial environment variables */
  74 +#define CONFIG_EXTRA_ENV_SETTINGS \
  75 + "board=ls1028ardb\0" \
  76 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  77 + "ramdisk_addr=0x800000\0" \
  78 + "ramdisk_size=0x2000000\0" \
  79 + "fdt_high=0xffffffffffffffff\0" \
  80 + "initrd_high=0xffffffffffffffff\0" \
  81 + "fdt_addr=0x00f00000\0" \
  82 + "kernel_addr=0x01000000\0" \
  83 + "scriptaddr=0x80000000\0" \
  84 + "scripthdraddr=0x80080000\0" \
  85 + "fdtheader_addr_r=0x80100000\0" \
  86 + "kernelheader_addr_r=0x80200000\0" \
  87 + "load_addr=0xa0000000\0" \
  88 + "kernel_addr_r=0x81000000\0" \
  89 + "fdt_addr_r=0x90000000\0" \
  90 + "ramdisk_addr_r=0xa0000000\0" \
  91 + "kernel_start=0x1000000\0" \
  92 + "kernelheader_start=0x800000\0" \
  93 + "kernel_load=0xa0000000\0" \
  94 + "kernel_size=0x2800000\0" \
  95 + "kernelheader_size=0x40000\0" \
  96 + "kernel_addr_sd=0x8000\0" \
  97 + "kernel_size_sd=0x14000\0" \
  98 + "kernelhdr_addr_sd=0x4000\0" \
  99 + "kernelhdr_size_sd=0x10\0" \
  100 + "console=ttyS0,115200\0" \
  101 + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  102 + BOOTENV \
  103 + "boot_scripts=ls1028ardb_boot.scr\0" \
  104 + "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \
  105 + "scan_dev_for_boot_part=" \
  106 + "part list ${devtype} ${devnum} devplist; " \
  107 + "env exists devplist || setenv devplist 1; " \
  108 + "for distro_bootpart in ${devplist}; do " \
  109 + "if fstype ${devtype} " \
  110 + "${devnum}:${distro_bootpart} " \
  111 + "bootfstype; then " \
  112 + "run scan_dev_for_boot; " \
  113 + "fi; " \
  114 + "done\0" \
  115 + "scan_dev_for_boot=" \
  116 + "echo Scanning ${devtype} " \
  117 + "${devnum}:${distro_bootpart}...; " \
  118 + "for prefix in ${boot_prefixes}; do " \
  119 + "run scan_dev_for_scripts; " \
  120 + "done;" \
  121 + "\0" \
  122 + "boot_a_script=" \
  123 + "load ${devtype} ${devnum}:${distro_bootpart} " \
  124 + "${scriptaddr} ${prefix}${script}; " \
  125 + "env exists secureboot && load ${devtype} " \
  126 + "${devnum}:${distro_bootpart} " \
  127 + "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  128 + "&& esbc_validate ${scripthdraddr};" \
  129 + "source ${scriptaddr}\0" \
  130 + "sd_bootcmd=echo Trying load from SD ..;" \
  131 + "mmcinfo; mmc read $load_addr " \
  132 + "$kernel_addr_sd $kernel_size_sd && " \
  133 + "env exists secureboot && mmc read $kernelheader_addr_r " \
  134 + "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  135 + " && esbc_validate ${kernelheader_addr_r};" \
  136 + "bootm $load_addr#$board\0" \
  137 + "emmc_bootcmd=echo Trying load from EMMC ..;" \
  138 + "mmcinfo; mmc dev 1; mmc read $load_addr " \
  139 + "$kernel_addr_sd $kernel_size_sd && " \
  140 + "env exists secureboot && mmc read $kernelheader_addr_r " \
  141 + "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  142 + " && esbc_validate ${kernelheader_addr_r};" \
  143 + "bootm $load_addr#$board\0"
  144 +
  145 +#undef CONFIG_BOOTCOMMAND
  146 +
  147 +#define SD_BOOTCOMMAND \
  148 + "run distro_bootcmd;run sd_bootcmd; " \
  149 + "env exists secureboot && esbc_halt;"
  150 +
  151 +/* Monitor Command Prompt */
  152 +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  153 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  154 + sizeof(CONFIG_SYS_PROMPT) + 16)
  155 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  156 +
  157 +#ifndef CONFIG_CMDLINE_EDITING
  158 +#define CONFIG_CMDLINE_EDITING 1
  159 +#endif
  160 +
  161 +#define CONFIG_SYS_MAXARGS 64 /* max command args */
  162 +
  163 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  164 +
  165 +/* MMC */
  166 +#ifdef CONFIG_MMC
  167 +#define CONFIG_FSL_ESDHC
  168 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  169 +#endif
  170 +
  171 +#define CONFIG_SYS_MMC_ENV_DEV 0
  172 +#define OCRAM_NONSECURE_SIZE 0x00010000
  173 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
  174 +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
  175 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET
  176 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  177 +#define CONFIG_ENV_SECT_SIZE 0x40000
  178 +
  179 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  180 +
  181 +/* MMC */
  182 +#ifdef CONFIG_MMC
  183 +#define CONFIG_FSL_ESDHC
  184 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  185 +#endif
  186 +
  187 +/* I2C bus multiplexer */
  188 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  189 +#define I2C_MUX_CH_DEFAULT 0x8
  190 +
  191 +/* EEPROM */
  192 +#define CONFIG_ID_EEPROM
  193 +#define CONFIG_SYS_I2C_EEPROM_NXID
  194 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
  195 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  196 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  197 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  198 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  199 +
  200 +#endif /* __L1028A_COMMON_H */
include/configs/ls1028ardb.h
Diff comments   View file @ 353f36d
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2019 NXP
  4 + */
  5 +
  6 +#ifndef __LS1028A_RDB_H
  7 +#define __LS1028A_RDB_H
  8 +
  9 +#include "ls1028a_common.h"
  10 +
  11 +#define CONFIG_SYS_CLK_FREQ 100000000
  12 +#define CONFIG_DDR_CLK_FREQ 100000000
  13 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
  14 +
  15 +#define CONFIG_SYS_RTC_BUS_NUM 0
  16 +
  17 +/* Store environment at top of flash */
  18 +#define CONFIG_ENV_SIZE 0x2000
  19 +
  20 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  21 +
  22 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  23 +
  24 +#define CONFIG_QIXIS_I2C_ACCESS
  25 +#define CONFIG_SYS_I2C_EARLY_INIT
  26 +
  27 +/*
  28 + * QIXIS Definitions
  29 + */
  30 +#define CONFIG_FSL_QIXIS
  31 +
  32 +#ifdef CONFIG_FSL_QIXIS
  33 +#define QIXIS_BASE 0x7fb00000
  34 +#define QIXIS_BASE_PHYS QIXIS_BASE
  35 +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  36 +#define QIXIS_LBMAP_SWITCH 2
  37 +#define QIXIS_LBMAP_MASK 0xe0
  38 +#define QIXIS_LBMAP_SHIFT 0x5
  39 +#define QIXIS_LBMAP_DFLTBANK 0x00
  40 +#define QIXIS_LBMAP_ALTBANK 0x00
  41 +#define QIXIS_LBMAP_SD 0x00
  42 +#define QIXIS_LBMAP_EMMC 0x00
  43 +#define QIXIS_LBMAP_QSPI 0x00
  44 +#define QIXIS_RCW_SRC_SD 0xf8
  45 +#define QIXIS_RCW_SRC_EMMC 0xf9
  46 +#define QIXIS_RCW_SRC_QSPI 0xff
  47 +#define QIXIS_RST_CTL_RESET 0x31
  48 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10
  49 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x11
  50 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  51 +#define QIXIS_RST_FORCE_MEM 0x01
  52 +
  53 +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  54 +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  55 + CSPR_PORT_SIZE_8 | \
  56 + CSPR_MSEL_GPCM | \
  57 + CSPR_V)
  58 +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  59 + CSOR_NOR_NOR_MODE_AVD_NOR | \
  60 + CSOR_NOR_TRHZ_80)
  61 +#endif
  62 +
  63 +/* SATA */
  64 +#ifndef CONFIG_CMD_EXT2
  65 +#define CONFIG_CMD_EXT2
  66 +#endif
  67 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  68 +#define CONFIG_SYS_SCSI_MAX_LUN 1
  69 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  70 + CONFIG_SYS_SCSI_MAX_LUN)
  71 +#define SCSI_VEND_ID 0x1b4b
  72 +#define SCSI_DEV_ID 0x9170
  73 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
  74 +#define CONFIG_SCSI_AHCI_PLAT
  75 +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  76 +
  77 +#endif /* __LS1028A_RDB_H */