diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
index 77b46f3b..7671a09 100644
--- a/arch/arm/dts/fsl-imx8mq-evk.dts
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -37,6 +37,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			u-boot,off-on-delay-us = <20000>;
 			enable-active-high;
 		};
 	};
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 9578f4e..b6175d8 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -471,15 +471,13 @@ void init_clk_usdhc(u32 index)
 	case 0:
 		clock_enable(CCGR_USDHC1, 0);
 		clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
-				     CLK_ROOT_SOURCE_SEL(1) |
-				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+				     CLK_ROOT_SOURCE_SEL(1));
 		clock_enable(CCGR_USDHC1, 1);
 		return;
 	case 1:
 		clock_enable(CCGR_USDHC2, 0);
 		clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
-				     CLK_ROOT_SOURCE_SEL(1) |
-				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+				     CLK_ROOT_SOURCE_SEL(1));
 		clock_enable(CCGR_USDHC2, 1);
 		return;
 	default:
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 263ee8d..2c832fe 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -30,6 +30,9 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y