diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0d24acd..47a60f3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ + fsl-smarcimx8qm.dtb \ fsl-imx8qm-ddr4-val.dtb \ fsl-imx8qm-lpddr4-val.dtb \ fsl-imx8qm-mek-xen.dtb \ diff --git a/arch/arm/dts/fsl-imx8qm-device.dtsi b/arch/arm/dts/fsl-imx8qm-device.dtsi index 2f5929b..74b4108 100644 --- a/arch/arm/dts/fsl-imx8qm-device.dtsi +++ b/arch/arm/dts/fsl-imx8qm-device.dtsi @@ -583,6 +583,24 @@ reg = ; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan2: PD_LPSPI1_RX { + reg = ; + power-domains =<&pd_dma_lpspi1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan3: PD_LPSPI1_TX { + reg = ; + power-domains =<&pd_dma0_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpspi2: PD_DMA_SPI_2 { reg = ; @@ -1584,6 +1602,22 @@ status = "disabled"; }; + lpspi1: lpspi@5a100000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a100000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_SPI1_CLK>, + <&clk IMX8QM_SPI1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_SPI1_CLK>; + assigned-clock-rates = <20000000>; + power-domains = <&pd_dma0_chan3>; + dma-names = "tx","rx"; + dmas = <&edma0 3 0 0>, <&edma0 2 0 1>; + status = "disabled"; + }; + lpspi3: lpspi@5a030000 { compatible = "fsl,imx7ulp-spi"; reg = <0x0 0x5a030000 0x0 0x10000>; @@ -1676,9 +1710,9 @@ assigned-clocks = <&clk IMX8QM_UART4_CLK>; assigned-clock-rates = <80000000>; power-domains = <&pd_dma0_chan21>; - dma-names = "tx","rx"; + /*dma-names = "tx","rx"; dmas = <&edma0 21 0 0>, - <&edma0 20 0 1>; + <&edma0 20 0 1>;*/ status = "disabled"; }; diff --git a/arch/arm/dts/fsl-imx8qm-mek-auto.dts b/arch/arm/dts/fsl-imx8qm-mek-auto.dts index 461ee46..6d757d0 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-auto.dts +++ b/arch/arm/dts/fsl-imx8qm-mek-auto.dts @@ -95,6 +95,7 @@ /delete-node/ &irqsteer_lvds1; /delete-node/ &i2c1_lvds1; /delete-node/ &lpspi0; +/delete-node/ &lpspi1; /delete-node/ &lpspi3; /delete-node/ &lpuart1; /delete-node/ &lpuart2; diff --git a/arch/arm/dts/fsl-smarcimx8qm-u-boot.dtsi b/arch/arm/dts/fsl-smarcimx8qm-u-boot.dtsi new file mode 100644 index 0000000..9bbd26f --- /dev/null +++ b/arch/arm/dts/fsl-smarcimx8qm-u-boot.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2021 Embedian Inc. + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/smarcimx8qm} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart1 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart3 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart4 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_dma_lpuart1 { + u-boot,dm-spl; +}; + +&pd_dma_lpuart3 { + u-boot,dm-spl; +}; + +&pd_dma_lpuart4 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&lpuart3 { + u-boot,dm-spl; +}; + +&lpuart4 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-smarcimx8qm.dts b/arch/arm/dts/fsl-smarcimx8qm.dts new file mode 100644 index 0000000..100d1ed --- /dev/null +++ b/arch/arm/dts/fsl-smarcimx8qm.dts @@ -0,0 +1,743 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Embedian, Inc. + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Embedian SMARC-iMX8QM CPU Module"; + compatible = "embedian,smarc-imx8qm", "fsl,imx8qm"; + + /* SER0 */ + /*chosen { + stdout-path = &lpuart0; + };*/ + /* SER1 */ + /*chosen { + stdout-path = &lpuart3; + };*/ + /* SER2 */ + /*chosen { + stdout-path = &lpuart1; + };*/ + /* SER3 */ + chosen { + stdout-path = &lpuart4; + }; + + aliases { + ethernet1 = &fec2; /* Let eth1addr mac address pass from U-Boot EEPROM */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_hdmisel>, <&pinctrl_lvds0_gpio>, <&pinctrl_lvds1_gpio>, <&pinctrl_edp0_gpio>, <&pinctrl_edp1_gpio>, <&pinctrl_hog>; + + smarcimx8qm { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000040 /* GPIO0 */ + SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0x06000040 /* GPIO1 */ + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0x06000040 /* GPIO2 */ + SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x06000040 /* GPIO3 */ + SC_P_GPT0_CLK_LSIO_GPIO0_IO14 0x06000040 /* GPIO4 */ + SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 0x06000040 /* GPIO5 */ + SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 0x06000040 /* GPIO6 */ + SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 0x06000040 /* GPIO7 */ + SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 0x06000040 /* GPIO8 */ + SC_P_GPT1_CLK_LSIO_GPIO0_IO17 0x06000040 /* GPIO9 */ + SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000040 /* GPIO10 */ + SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000040 /* GPIO11 */ + SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000020 /* LID# */ + SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 0x06000020 /* SLEEP */ + SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x06000020 /* CHARGING */ + SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x06000020 /* CHARGER_PRSNT# */ + SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 0x06000020 /* BATLOW# */ + SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x06000020 /* CARRIER_STBY# */ + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x06000020 /* WDT_TIME_OUT# */ + >; + }; + + pinctrl_hdmisel: hdmiselgrp { + fsl,pins = < + SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x06000020 + >; + }; + + pinctrl_lvds0_gpio: lvds0gpiogrp { + fsl,pins = < + SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x06000020 /* LCD0_VDD_EN */ + >; + }; + + pinctrl_lvds1_gpio: lvds1gpiogrp { + fsl,pins = < + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 /* LCD1_VDD_EN */ + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000020 /* LCD0_BKLT_EN */ + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000020 /* LCD1_BKLT_EN */ + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_edp0_gpio: edp0gpiogrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x06000020 /* eDP0_EN */ + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x06000040 /* eDP0_IRQ */ + >; + }; + + pinctrl_edp1_gpio: edp1gpiogrp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 0x06000020 /* eDP1_EN */ + SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x06000040 /* eDP1_IRQ */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 + /* ETH IRQ */ + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x06000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + /* ETH IRQ */ + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x06000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + >; + }; + + /* SER0 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + /* SER1 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + /* SER2 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + >; + }; + + /* SER3 */ + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + SC_P_M40_GPIO0_00_DMA_UART4_RX 0x06000020 + SC_P_M40_GPIO0_01_DMA_UART4_TX 0x06000020 + >; + }; + + /* SPI1 */ + pinctrl_lpspi1: lpspi1grp { + fsl,pins = < + SC_P_ADC_IN3_DMA_SPI1_SCK 0x0600004c + SC_P_ADC_IN4_DMA_SPI1_SDO 0x0600004c + SC_P_ADC_IN5_DMA_SPI1_SDI 0x0600004c + >; + }; + + pinctrl_lpspi1_cs: lpspi1csgrp { + fsl,pins = < + SC_P_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 + SC_P_ADC_IN7_LSIO_GPIO3_IO25 0x00000021 + >; + }; + + /* SPI3 */ + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + SC_P_SPI3_SCK_DMA_SPI3_SCK 0x0600004c + SC_P_SPI3_SDO_DMA_SPI3_SDO 0x0600004c + SC_P_SPI3_SDI_DMA_SPI3_SDI 0x0600004c + >; + }; + + pinctrl_lpspi3_cs: lpspi3csgrp { + fsl,pins = < + SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x00000021 + SC_P_SPI3_CS1_LSIO_GPIO2_IO21 0x00000021 + >; + }; + + pinctrl_i2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + /* I2C_PM */ + pinctrl_i2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL 0xc600004c + SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA 0xc600004c + >; + }; + + /* I2C_CAM0 */ + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc600004c + SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc600004c + >; + }; + + /* I2C_CAM1 */ + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc600004c + SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc600004c + >; + }; + + /* I2C_GP */ + pinctrl_i2c3: lpi2c3grp { + fsl,pins = < + SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x06000020 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000020 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x06000020 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000020 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000020 + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x06000020 + >; + }; + + pinctrl_usbotg3: usbotg3 { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000020 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + /* I2C_LCD */ + pinctrl_lvds1_lpi2c0: lvds1lpi2c0grp { + fsl,pins = < + SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL 0xc600004c + SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + pinctrl-0 = <&pinctrl_usbotg3>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x6>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x7>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mx25u3235f@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; +}; + +&i2c0_mipi_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <400000>; + status = "okay"; +}; + +/* I2C_PM */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + cape_eeprom0: cape_eeprom@57 { + compatible = "at,24c256"; + reg = <0x57>; + }; +}; + +/* I2C_GP */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +/* SPI0 */ +&lpspi1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>; + cs-gpios = <&gpio3 24 0>, <&gpio3 25 0>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <12000000>; + reg = <0>; + status = "okay"; + }; + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <12000000>; + reg = <1>; + status = "okay"; + }; +}; + +/* eSPI */ +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3 &pinctrl_lpspi3_cs>; + cs-gpios = <&gpio2 20 0>, <&gpio2 21 0>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <12000000>; + reg = <0>; + status = "okay"; + }; + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <12000000>; + reg = <1>; + status = "okay"; + }; +}; + +/* I2C_LCD */ +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sata { + pinctrl-names = "default"; + status = "okay"; +}; + +&tsens { + tsens-num = <6>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 5>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&pmic_alert0>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&dpu1 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + + lvds_backlight_hog { + gpio-hog; + gpios = <1 5>, <1 6>; + output-high; + line-name = "lvds_backlight"; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <33300000>; + hactive = <800>; + vactive = <480>; + hback-porch = <64>; + hfront-porch = <64>; + vback-porch = <12>; + vfront-porch = <4>; + hsync-len = <128>; + vsync-len = <2>; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index f6ead72..7c4846d 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -117,6 +117,11 @@ config TARGET_IMX8QM_MEK select BOARD_LATE_INIT select IMX8QM +config TARGET_SMARCIMX8QM + bool "Support SMARC-iMX8QM CPU Module" + select BOARD_LATE_INIT + select IMX8QM + config TARGET_IMX8QM_LPDDR4_VAL bool "Support i.MX8QM lpddr4 validation board" select BOARD_LATE_INIT @@ -176,6 +181,7 @@ config TARGET_IMX8DXL_DDR3_EVK endchoice +source "board/embedian/smarcimx8qm/Kconfig" source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/freescale/imx8qm_val/Kconfig" diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index a263222..439cad1 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -25,8 +25,22 @@ u32 mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_UART_CLK: +#ifdef CONFIG_CONSOLE_SER0 err = sc_pm_get_clock_rate(-1, SC_R_UART_0, 2, &clkrate); +#elif CONFIG_CONSOLE_SER1 + err = sc_pm_get_clock_rate(-1, + SC_R_UART_3, 2, &clkrate); +#elif CONFIG_CONSOLE_SER2 + err = sc_pm_get_clock_rate(-1, + SC_R_UART_1, 2, &clkrate); +#elif CONFIG_CONSOLE_SER3 + err = sc_pm_get_clock_rate(-1, + SC_R_UART_4, 2, &clkrate); +#else + err = sc_pm_get_clock_rate(-1, + SC_R_UART_0, 2, &clkrate); +#endif if (err != SC_ERR_NONE) { printf("sc get UART clk failed! err=%d\n", err); return 0; diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_smarc.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_smarc.h new file mode 100644 index 0000000..a98df9c --- /dev/null +++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_smarc.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP. + */ + +#ifndef SNVS_SECURITY_SC_CONF_8QM_SMARC_H_ +#define SNVS_SECURITY_SC_CONF_8QM_SMARC_H_ + +#include "snvs_security_sc_conf.h" + +/* Configuration */ + +static __maybe_unused struct snvs_security_sc_conf snvs_default_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x76, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x276, /* ET1 will trig on line at GND + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_active_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0x00800000, /* Enable filtering */ + .tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0x84001111, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0x00010001, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0x1, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000001, /* Pull down ET1 */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000401, /* Pull up ET1 */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static struct tamper_pin_cfg tamper_pin_list_default_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = { +}; + +#endif /* SNVS_SECURITY_SC_CONF_8QM_SMARC_H_ */ diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h index 250952b..fed3885 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h +++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h @@ -8,6 +8,8 @@ #ifdef CONFIG_TARGET_IMX8QM_MEK #include "snvs_security_sc_conf_8qm_mek.h" +#elif CONFIG_TARGET_SMARCIMX8QM +#include "snvs_security_sc_conf_8qm_smarc.h" #elif CONFIG_TARGET_IMX8QXP_MEK #include "snvs_security_sc_conf_8qxp_mek.h" #elif CONFIG_TARGET_IMX8DXL_EVK diff --git a/board/embedian/smarcimx8qm/Kconfig b/board/embedian/smarcimx8qm/Kconfig new file mode 100644 index 0000000..7d0b8ea --- /dev/null +++ b/board/embedian/smarcimx8qm/Kconfig @@ -0,0 +1,14 @@ +if TARGET_SMARCIMX8QM + +config SYS_BOARD + default "smarcimx8qm" + +config SYS_VENDOR + default "embedian" + +config SYS_CONFIG_NAME + default "smarcimx8qm" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/embedian/smarcimx8qm/MAINTAINERS b/board/embedian/smarcimx8qm/MAINTAINERS new file mode 100644 index 0000000..c32f918 --- /dev/null +++ b/board/embedian/smarcimx8qm/MAINTAINERS @@ -0,0 +1,6 @@ +SMARC-iMX8QM CPU Module +M: Eric Lee +S: Maintained +F: board/embedian/smarcimx8qm/ +F: include/configs/smarcimx8qm.h +F: configs/smarcimx8qm_*_defconfig diff --git a/board/embedian/smarcimx8qm/Makefile b/board/embedian/smarcimx8qm/Makefile new file mode 100644 index 0000000..b553e34 --- /dev/null +++ b/board/embedian/smarcimx8qm/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += smarcimx8qm.o ../../freescale/common/mmc.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/embedian/smarcimx8qm/README b/board/embedian/smarcimx8qm/README new file mode 100644 index 0000000..5c38438 --- /dev/null +++ b/board/embedian/smarcimx8qm/README @@ -0,0 +1,54 @@ +U-Boot for the Embedian SMARC-iMX8QM CPU Module + +Quick Start +=========== + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin +$ chmod +x imx-sc-firmware-1.1.bin +$ ./imx-sc-firmware-1.1.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + +Copy the following binaries to U-Boot folder: + +$ cp imx-atf/build/imx8qm/release/bl31.bin . +$ cp u-boot/u-boot.bin . + +Copy the following firmwares U-Boot folder : + +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img . +$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin . + +Build U-Boot +============ +$ make imx8qm_mek_defconfig +$ make flash.bin + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot_SET to ON OFF OFF and shunt TEST# to GND diff --git a/board/embedian/smarcimx8qm/imximage.cfg b/board/embedian/smarcimx8qm/imximage.cfg new file mode 100644 index 0000000..7dc6b93 --- /dev/null +++ b/board/embedian/smarcimx8qm/imximage.cfg @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/embedian/smarcimx8qm/smarcimx8qm.c b/board/embedian/smarcimx8qm/smarcimx8qm.c new file mode 100644 index 0000000..d742764 --- /dev/null +++ b/board/embedian/smarcimx8qm/smarcimx8qm.c @@ -0,0 +1,1265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../freescale/common/tcpc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +/* SER0 */ +#ifdef CONFIG_CONSOLE_SER0 +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#endif + +/* SER1 */ +#ifdef CONFIG_CONSOLE_SER1 +static iomux_cfg_t uart3_pads[] = { + SC_P_M41_GPIO0_00 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ + SC_P_M41_GPIO0_01 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +}; +#endif + +/* SER2 */ +#ifdef CONFIG_CONSOLE_SER2 +static iomux_cfg_t uart1_pads[] = { + SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#endif + +/* SER3 */ +#ifdef CONFIG_CONSOLE_SER3 +static iomux_cfg_t uart4_pads[] = { + SC_P_M40_GPIO0_00 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ + SC_P_M40_GPIO0_01 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +}; +#endif + +#ifdef CONFIG_CONSOLE_SER0 +static void setup_iomux_uart0(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} +#endif + +#ifdef CONFIG_CONSOLE_SER1 +static void setup_iomux_uart3(void) +{ + imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} +#endif + +#ifdef CONFIG_CONSOLE_SER2 +static void setup_iomux_uart1(void) +{ + imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} +#endif + +#ifdef CONFIG_CONSOLE_SER3 +static void setup_iomux_uart4(void) +{ + imx8_iomux_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} +#endif + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + +#ifdef CONFIG_CONSOLE_SER0 + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart0(); +#endif + +#ifdef CONFIG_CONSOLE_SER1 + /* Set UART3 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_3, rate); + if (ret) + return ret; + + setup_iomux_uart3(); +#endif + +#ifdef CONFIG_CONSOLE_SER2 + /* Set UART1 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_1, rate); + if (ret) + return ret; + + setup_iomux_uart1(); +#endif + +#ifdef CONFIG_CONSOLE_SER3 + /* Set UART4 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_4, rate); + if (ret) + return ret; + + setup_iomux_uart4(); +#endif + +/* Dual bootloader feature will require CAAM access, but JR0 and JR1 will be + * assigned to seco for imx8, use JR3 instead. + */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + sc_pm_set_resource_power_mode(-1, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(-1, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON); +#endif + + return 0; +} + + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +#ifndef CONFIG_DM_ETH +static iomux_cfg_t pad_enet1[] = { + SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +static iomux_cfg_t smarc_gpio[] = { + SC_P_MIPI_CSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO0 */ + SC_P_MIPI_CSI1_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO1 */ + SC_P_MIPI_CSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO2 */ + SC_P_MIPI_CSI1_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO3 */ + SC_P_GPT0_CLK | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO4 */ + SC_P_GPT0_COMPARE | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO5 */ + SC_P_GPT0_CAPTURE | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO6 */ + SC_P_GPT1_COMPARE | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO7 */ + SC_P_GPT1_CAPTURE | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO8 */ + SC_P_GPT1_CLK | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO9 */ + SC_P_FLEXCAN2_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO10 */ + SC_P_FLEXCAN2_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* GPIO11 */ + SC_P_SCU_GPIO0_03 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* LID# */ + SC_P_SCU_GPIO0_04 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* SLEEP# */ + SC_P_SCU_GPIO0_05 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* CHARGING# */ + SC_P_SCU_GPIO0_06 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* CHARGER_PRSNT# */ + SC_P_SCU_GPIO0_07 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* BATLOW# */ + SC_P_SCU_GPIO0_02 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* CARRIER_STBY# */ + SC_P_QSPI1A_DATA0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* RGMII0_INT# */ + SC_P_QSPI1A_DATA1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* RGMII1_INT# */ + SC_P_USB_SS3_TC0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + /* USB_OTG1_PWR_EN */ + SC_P_USB_SS3_TC1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* USB_OTG2_PWR_EN */ + SC_P_USB_SS3_TC2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* USB_OTG1_OC */ + SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* USB_OTG2_OC */ + SC_P_SIM0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* HDMI_SEL */ + SC_P_MIPI_DSI1_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* EDP0_EN */ + SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* EDP1_EN */ + SC_P_MIPI_DSI1_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* EDP0_IRQ */ + SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* EDP1_IRQ */ + SC_P_LVDS0_GPIO01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* LCD0_VDD_EN */ + SC_P_LVDS1_GPIO01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* LCD1_VDD_EN */ + SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* LCD0_BKLT_EN */ + SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* LCD1_BKLT_EN */ + SC_P_ADC_IN0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* BOOT_SEL0 */ + SC_P_ADC_IN1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* BOOT_SEL1 */ + SC_P_ADC_IN2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* BOOT_SEL2 */ + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* WDT_TIME_OUT# */ +}; + +/* GPIO0 */ +#define GPIO0 IMX_GPIO_NR(1, 28) /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +/* GPIO1 */ +#define GPIO1 IMX_GPIO_NR(1, 31) /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +/* GPIO2 */ +#define GPIO2 IMX_GPIO_NR(1, 27) /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +/* GPIO3 */ +#define GPIO3 IMX_GPIO_NR(1, 30) /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +/* GPIO4 */ +#define GPIO4 IMX_GPIO_NR(0, 14) /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +/* GPIO5 */ +#define GPIO5 IMX_GPIO_NR(0, 16) /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +/* GPIO6 */ +#define GPIO6 IMX_GPIO_NR(0, 15) /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +/* GPIO7 */ +#define GPIO7 IMX_GPIO_NR(0, 19) /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +/* GPIO8 */ +#define GPIO8 IMX_GPIO_NR(0, 18) /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +/* GPIO9 */ +#define GPIO9 IMX_GPIO_NR(0, 17) /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +/* GPIO10 */ +#define GPIO10 IMX_GPIO_NR(4, 02) /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +/* GPIO11 */ +#define GPIO11 IMX_GPIO_NR(4, 01) /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +/* LID# */ +#define LID IMX_GPIO_NR(0, 31) /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +/* SLEEP# */ +#define SLEEP IMX_GPIO_NR(1, 00) /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +/* CHARGING# */ +#define CHARGING IMX_GPIO_NR(1, 01) /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +/* CHARGER_PRSNT# */ +#define CHARGER_PRSNT IMX_GPIO_NR(1, 02) /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +/* BATLOW# */ +#define BATLOW IMX_GPIO_NR(1, 03) /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +/* CARRIER_STBY# */ +#define CARRIER_STBY IMX_GPIO_NR(0, 30) /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +/* RGMII0_INT# */ +#define RGMII0_INT IMX_GPIO_NR(4, 26) /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +/* RGMII1_INT# */ +#define RGMII1_INT IMX_GPIO_NR(4, 25) /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +/* USB_OTG1_PWR_EN */ +#define USB_OTG1_PWR_EN IMX_GPIO_NR(4, 03) /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +/* USB_OTG2_PWR_EN */ +#define USB_OTG2_PWR_EN IMX_GPIO_NR(4, 04) /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +/* USB_OTG1_OC# */ +#define USB_OTG1_OC IMX_GPIO_NR(4, 05) /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +/* USB_OTG2_OC# */ +#define USB_OTG2_OC IMX_GPIO_NR(4, 06) /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +/* HDMI_SEL */ +#define HDMI_SEL IMX_GPIO_NR(0, 05) /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +/* EDP0_EN */ +#define EDP0_EN IMX_GPIO_NR(1, 22) /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +/* EDP1_EN */ +#define EDP1_EN IMX_GPIO_NR(1, 18) /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +/* EDP0_IRQ */ +#define EDP0_IRQ IMX_GPIO_NR(1, 23) /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +/* EDP1_IRQ */ +#define EDP1_IRQ IMX_GPIO_NR(1, 19) /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +/* LCD0_VDD_EN */ +#define LCD0_VDD_EN IMX_GPIO_NR(1, 05) /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +/* LCD1_VDD_EN */ +#define LCD1_VDD_EN IMX_GPIO_NR(1, 11) /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +/* LCD0_BKLT_EN */ +#define LCD0_BKLT_EN IMX_GPIO_NR(1, 06) /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +/* LCD1_BKLT_EN */ +#define LCD1_BKLT_EN IMX_GPIO_NR(1, 07) /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +/* WDT_TIME_OUT# */ +#define WDT_TIME_OUT IMX_GPIO_NR(2, 15) /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ + +static void board_gpio_init(void) +{ + int ret; + struct gpio_desc desc; + + imx8_iomux_setup_multiple_pads(smarc_gpio, ARRAY_SIZE(smarc_gpio)); + /* By SMARC definition, GPIO0~GPIO5 are set as Outpin Low by default */ + /* GPIO0 */ + ret = dm_gpio_lookup_name("GPIO1_28", &desc); + if (ret) { + printf("%s lookup GPIO@1_28 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio0"); + if (ret) { + printf("%s request gpio0 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + /* GPIO1 */ + ret = dm_gpio_lookup_name("GPIO1_31", &desc); + if (ret) { + printf("%s lookup GPIO@1_31 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio1"); + if (ret) { + printf("%s request gpio1 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + /* GPIO2 */ + ret = dm_gpio_lookup_name("GPIO1_27", &desc); + if (ret) { + printf("%s lookup GPIO@1_27 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio2"); + if (ret) { + printf("%s request gpio2 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + /* GPIO3 */ + ret = dm_gpio_lookup_name("GPIO1_30", &desc); + if (ret) { + printf("%s lookup GPIO@1_30 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio3"); + if (ret) { + printf("%s request gpio3 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + /* GPIO4 */ + ret = dm_gpio_lookup_name("GPIO0_14", &desc); + if (ret) { + printf("%s lookup GPIO@0_14 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio4"); + if (ret) { + printf("%s request gpio4 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + /* GPIO5 */ + ret = dm_gpio_lookup_name("GPIO0_16", &desc); + if (ret) { + printf("%s lookup GPIO@0_16 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio5"); + if (ret) { + printf("%s request gpio5 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + /* GPIO6 */ + ret = dm_gpio_lookup_name("GPIO0_15", &desc); + if (ret) { + printf("%s lookup GPIO@0_15 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio6"); + if (ret) { + printf("%s request gpio6 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* GPIO7 */ + ret = dm_gpio_lookup_name("GPIO0_19", &desc); + if (ret) { + printf("%s lookup GPIO@0_19 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio7"); + if (ret) { + printf("%s request gpio7 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* GPIO8 */ + ret = dm_gpio_lookup_name("GPIO0_18", &desc); + if (ret) { + printf("%s lookup GPIO@0_18 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio8"); + if (ret) { + printf("%s request gpio8 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* GPIO9 */ + ret = dm_gpio_lookup_name("GPIO0_17", &desc); + if (ret) { + printf("%s lookup GPIO@0_17 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio9"); + if (ret) { + printf("%s request gpio9 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* GPIO10 */ + ret = dm_gpio_lookup_name("GPIO4_02", &desc); + if (ret) { + printf("%s lookup GPIO@4_02 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio10"); + if (ret) { + printf("%s request gpio10 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* GPIO11 */ + ret = dm_gpio_lookup_name("GPIO4_01", &desc); + if (ret) { + printf("%s lookup GPIO@4_01 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "gpio11"); + if (ret) { + printf("%s request gpio11 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set LID# pin as Input Pin */ + ret = dm_gpio_lookup_name("GPIO0_31", &desc); + if (ret) { + printf("%s lookup GPIO@0_31 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "lid"); + if (ret) { + printf("%s request lid failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set SLEEP# pin as Input Pin */ + ret = dm_gpio_lookup_name("GPIO1_00", &desc); + if (ret) { + printf("%s lookup GPIO@1_00 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "sleep"); + if (ret) { + printf("%s request sleep failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set CHARGING# pin as Input Pin */ + ret = dm_gpio_lookup_name("GPIO1_01", &desc); + if (ret) { + printf("%s lookup GPIO@1_01 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "charging"); + if (ret) { + printf("%s request charging failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set CHARGER_PRSNT# pin as Input Pin */ + ret = dm_gpio_lookup_name("GPIO1_02", &desc); + if (ret) { + printf("%s lookup GPIO@1_02 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "charger_prsnt"); + if (ret) { + printf("%s request charger_prsnt failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set BATLOW# pin as Input Pin */ + ret = dm_gpio_lookup_name("GPIO1_03", &desc); + if (ret) { + printf("%s lookup GPIO@1_03 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "batlow"); + if (ret) { + printf("%s request batlow failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set CARRIER_STBY# pin as Output High */ + ret = dm_gpio_lookup_name("GPIO0_30", &desc); + if (ret) { + printf("%s lookup GPIO@0_30 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "carrier_stby"); + if (ret) { + printf("%s request carrier_stby failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Set RGMII0_INT# pin as Input pin*/ + ret = dm_gpio_lookup_name("GPIO4_26", &desc); + if (ret) { + printf("%s lookup GPIO@4_26 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "rgmii0_int"); + if (ret) { + printf("%s request rgmii0_int failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set RGMII1_INT# pin as Input pin*/ + ret = dm_gpio_lookup_name("GPIO4_25", &desc); + if (ret) { + printf("%s lookup GPIO@4_25 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "rgmii1_int"); + if (ret) { + printf("%s request rgmii1_int failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Turn on USB0 Power */ + ret = dm_gpio_lookup_name("GPIO4_03", &desc); + if (ret) { + printf("%s lookup GPIO@4_03 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "usb_otg1_pwr_en"); + if (ret) { + printf("%s request usb_otg1_pwr_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Turn on USB2514 Hub Power */ + ret = dm_gpio_lookup_name("GPIO4_04", &desc); + if (ret) { + printf("%s lookup GPIO@4_04 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "usb_otg2_pwr_en"); + if (ret) { + printf("%s request usb_otg2_pwr_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Set USB0 OC# pin as Input pin*/ + ret = dm_gpio_lookup_name("GPIO4_05", &desc); + if (ret) { + printf("%s lookup GPIO@4_05 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "usb_otg1_oc"); + if (ret) { + printf("%s request usb_otg1_oc failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set USB1 OC# pin as Input pin*/ + ret = dm_gpio_lookup_name("GPIO4_06", &desc); + if (ret) { + printf("%s lookup GPIO@4_06 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "usb_otg2_oc"); + if (ret) { + printf("%s request usb_otg2_oc failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set HDMI_SEL pin as Input pin*/ + ret = dm_gpio_lookup_name("GPIO0_05", &desc); + if (ret) { + printf("%s lookup GPIO@0_05 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "hdmi_sel"); + if (ret) { + printf("%s request usb_hdmi_sel failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Turn on eDP0 Power */ + ret = dm_gpio_lookup_name("GPIO1_22", &desc); + if (ret) { + printf("%s lookup GPIO@1_22 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "edp0_en"); + if (ret) { + printf("%s request edp0_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Turn off eDP1 Power */ + ret = dm_gpio_lookup_name("GPIO1_18", &desc); + if (ret) { + printf("%s lookup GPIO@1_18 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "edp1_en"); + if (ret) { + printf("%s request edp1_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + /* Set eDP0_IRQ pin as Input Pin */ + ret = dm_gpio_lookup_name("GPIO1_23", &desc); + if (ret) { + printf("%s lookup GPIO@1_23 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "edp0_irq"); + if (ret) { + printf("%s request edp0_irq failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Set eDP1_IRQ pin as Input Pin */ + ret = dm_gpio_lookup_name("GPIO1_19", &desc); + if (ret) { + printf("%s lookup GPIO@1_19 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "edp1_irq"); + if (ret) { + printf("%s request edp1_irq failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + /* Turn on LVDS0_VDD Power */ + ret = dm_gpio_lookup_name("GPIO1_05", &desc); + if (ret) { + printf("%s lookup GPIO@1_05 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "lcd0_vdd_en"); + if (ret) { + printf("%s request lcd0_vdd_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Turn on LVDS1_VDD Power */ + ret = dm_gpio_lookup_name("GPIO1_11", &desc); + if (ret) { + printf("%s lookup GPIO@1_11 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "lcd1_vdd_en"); + if (ret) { + printf("%s request lcd1_vdd_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Turn on LVDS0 Backlight Power */ + ret = dm_gpio_lookup_name("GPIO1_06", &desc); + if (ret) { + printf("%s lookup GPIO@1_06 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "lcd0_bklt_en"); + if (ret) { + printf("%s request lcd0_bklt_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Turn on LVDS1 Backlight Power */ + ret = dm_gpio_lookup_name("GPIO1_07", &desc); + if (ret) { + printf("%s lookup GPIO@1_07 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "lcd1_bklt_en"); + if (ret) { + printf("%s request lcd1_bklt_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); + + /* Set WDT_TIME_OUT# pin as Output High */ + ret = dm_gpio_lookup_name("GPIO2_15", &desc); + if (ret) { + printf("%s lookup GPIO@2_15 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "wdt_time_out"); + if (ret) { + printf("%s request wdt_time_out failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + dm_gpio_set_value(&desc, 1); +} + +int checkboard(void) +{ + puts("Board: SMARC-iMX8QM CPU Module\n"); + + print_bootinfo(); + + return 0; +} + +#ifdef CONFIG_USB + +#ifdef CONFIG_USB_TCPC +struct gpio_desc type_sel_desc; + +static iomux_cfg_t ss_mux_gpio[] = { + SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +struct tcpc_port port; +struct tcpc_port_config port_config = { + .i2c_bus = 0, + .addr = 0x51, + .port_type = TYPEC_PORT_DFP, +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + dm_gpio_set_value(&type_sel_desc, 0); + else + dm_gpio_set_value(&type_sel_desc, 1); +} + +static void setup_typec(void) +{ + int ret; + struct gpio_desc typec_en_desc; + + imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + ret = dm_gpio_lookup_name("GPIO4_6", &type_sel_desc); + if (ret) { + printf("%s lookup GPIO4_6 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&type_sel_desc, "typec_sel"); + if (ret) { + printf("%s request typec_sel failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT); + + ret = dm_gpio_lookup_name("GPIO4_19", &typec_en_desc); + if (ret) { + printf("%s lookup GPIO4_19 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&typec_en_desc, "typec_en"); + if (ret) { + printf("%s request typec_en failed ret = %d\n", __func__, ret); + return; + } + + /* Enable SS MUX */ + dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + tcpc_init(&port, port_config, &ss_mux_select); +} +#endif + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port); +#endif +#ifdef CONFIG_USB_CDNS3_GADGET + } else { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port); + printf("%d setufp mode %d\n", index, ret); +#endif +#endif + } + } + + return ret; + +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port); +#endif + } + } + + return ret; +} +#endif + +int board_init(void) +{ + board_gpio_init(); + + +#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC) + setup_typec(); +#endif + +#ifdef CONFIG_SNVS_SEC_SC_AUTO + { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } +#endif + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD); + while(1); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +extern uint32_t _end_ofs; +int board_late_init(void) +{ + + puts("---------Embedian SMARC-iMX8QM------------\n"); + /* Read Module Information from on module EEPROM and pass + * mac address to kernel + */ + struct gpio_desc desc; + struct udevice *dev; + char bootmode = 0; + int ret; + u8 name[8]; + u8 serial[12]; + u8 revision[4]; + u8 mac[6]; + u8 mac1[6]; + + ret = i2c_get_chip_for_busnum(3, 0x50, 2, &dev); + if (ret) { + debug("failed to get eeprom\n"); + return 0; + } + + /* Board ID */ + ret = dm_i2c_read(dev, 0x4, name, 8); + if (ret) { + debug("failed to read board ID from EEPROM\n"); + return 0; + } + printf(" Board ID: %c%c%c%c%c%c%c%c\n", + name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); + + /* Board Hardware Revision */ + ret = dm_i2c_read(dev, 0xc, revision, 4); + if (ret) { + debug("failed to read hardware revison from EEPROM\n"); + return 0; + } + printf(" Hardware Revision: %c%c%c%c\n", + revision[0], revision[1], revision[2], revision[3]); + + /* Serial number */ + ret = dm_i2c_read(dev, 0x10, serial, 12); + if (ret) { + debug("failed to read srial number from EEPROM\n"); + return 0; + } + printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", + serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); + + /*MAC1 address*/ + ret = dm_i2c_read(dev, 0x3c, mac, 6); + if (ret) { + debug("failed to read eth0 mac address from EEPROM\n"); + return 0; + } + + if (is_valid_ethaddr(mac)) + printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + eth_env_set_enetaddr("ethaddr", mac); + + /* MAC2 address */ + ret = dm_i2c_read(dev, 0x42, mac1, 6); + if (ret) { + debug("failed to read eth1 mac address from EEPROM\n"); + return 0; + } + + if (is_valid_ethaddr(mac1)) + printf(" MAC1 Address: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac1[0], mac1[1], mac1[2], mac1[3], mac1[4], mac1[5]); + eth_env_set_enetaddr("eth1addr", mac1); + puts("-----------------------------------------\n"); + +#ifndef CONFIG_ANDROID_AUTO_SUPPORT + build_info(); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "SMARC"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#if defined(CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX) || defined(CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX) + char *end_of_uboot; + char command[256]; + end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob)); + end_of_uboot += 9; + + /* load hdmitxfw.bin and hdmirxfw.bin*/ + memcpy((void *)IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, + IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE); + +#ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX + sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR); + run_command(command, 0); +#endif +#ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX + sprintf(command, "hdprx load 0x%x", + IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE); + run_command(command, 0); +#endif +#endif /* CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX || CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX */ + + /* BOOT_SEL0 */ + ret = dm_gpio_lookup_name("GPIO3_18", &desc); + if (ret) { + printf("%s lookup GPIO@3_18 failed ret = %d\n", __func__, ret); + return 0; + } + + ret = dm_gpio_request(&desc, "bootsel0"); + if (ret) { + printf("%s request bootsel0 failed ret = %d\n", __func__, ret); + return 0; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + bootmode |= (dm_gpio_get_value(&desc) ? 1 : 0) << 0; + + /* BOOT_SEL1 */ + ret = dm_gpio_lookup_name("GPIO3_19", &desc); + if (ret) { + printf("%s lookup GPIO@3_19 failed ret = %d\n", __func__, ret); + return 0; + } + + ret = dm_gpio_request(&desc, "bootsel1"); + if (ret) { + printf("%s request bootsel1 failed ret = %d\n", __func__, ret); + return 0; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + bootmode |= (dm_gpio_get_value(&desc) ? 1 : 0) << 1; + + /* BOOT_SEL2 */ + ret = dm_gpio_lookup_name("GPIO3_20", &desc); + if (ret) { + printf("%s lookup GPIO@3_20 failed ret = %d\n", __func__, ret); + return 0; + } + + ret = dm_gpio_request(&desc, "bootsel2"); + if (ret) { + printf("%s request bootsel2 failed ret = %d\n", __func__, ret); + return 0; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + bootmode |= (dm_gpio_get_value(&desc) ? 1 : 0) << 2; + + if (bootmode == 0) { + puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n"); + hang(); + } else if (bootmode == 4) { + puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n"); + env_set_ulong("usb dev", 1); + env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; loadusbimage; run usbboot;"); + } else if (bootmode == 2) { + puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n"); + hang(); + } else if (bootmode == 1) { + puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n"); + env_set_ulong("mmcdev", 1); + env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run loadimage; run mmcboot;"); + } else if (bootmode == 6) { + puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n"); + env_set_ulong("mmcdev", 0); + env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run loadimage; run mmcboot;"); + } else if (bootmode == 5) { + puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); + env_set("bootcmd", "run netboot;"); + } else if (bootmode == 3) { + puts("BOOT_SEL Detected: ON ON OFF, Boot from Carrier SPI is not supported...\n"); + hang(); + } else if (bootmode == 7) { + puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n"); + hang(); + } else { + puts("unsupported boot devices\n"); + hang(); + } + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + sc_bool_t status = SC_FALSE; + + sc_misc_get_button_status(-1, &status); + return (bool)status; +} +#endif diff --git a/board/embedian/smarcimx8qm/spl.c b/board/embedian/smarcimx8qm/spl.c new file mode 100644 index 0000000..e5357d2 --- /dev/null +++ b/board/embedian/smarcimx8qm/spl.c @@ -0,0 +1,60 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + timer_init(); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); + + puts("Normal Boot\n"); +#endif + +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/embedian/smarcimx8qm/uboot-container.cfg b/board/embedian/smarcimx8qm/uboot-container.cfg new file mode 100644 index 0000000..6cc47cd --- /dev/null +++ b/board/embedian/smarcimx8qm/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QM +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/configs/smarcimx8qm_4g_ser0_defconfig b/configs/smarcimx8qm_4g_ser0_defconfig new file mode 100644 index 0000000..da2e642 --- /dev/null +++ b/configs/smarcimx8qm_4g_ser0_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,4GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER0=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/smarcimx8qm_4g_ser1_defconfig b/configs/smarcimx8qm_4g_ser1_defconfig new file mode 100644 index 0000000..7ee95ac --- /dev/null +++ b/configs/smarcimx8qm_4g_ser1_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,4GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER1=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/smarcimx8qm_4g_ser2_defconfig b/configs/smarcimx8qm_4g_ser2_defconfig new file mode 100644 index 0000000..c821534 --- /dev/null +++ b/configs/smarcimx8qm_4g_ser2_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,4GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER2=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/smarcimx8qm_4g_ser3_defconfig b/configs/smarcimx8qm_4g_ser3_defconfig new file mode 100644 index 0000000..4568c27 --- /dev/null +++ b/configs/smarcimx8qm_4g_ser3_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,4GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER3=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/smarcimx8qm_8g_ser0_defconfig b/configs/smarcimx8qm_8g_ser0_defconfig new file mode 100644 index 0000000..4348a23 --- /dev/null +++ b/configs/smarcimx8qm_8g_ser0_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,8GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER0=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/smarcimx8qm_8g_ser1_defconfig b/configs/smarcimx8qm_8g_ser1_defconfig new file mode 100644 index 0000000..ff10fe0 --- /dev/null +++ b/configs/smarcimx8qm_8g_ser1_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,8GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER1=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/smarcimx8qm_8g_ser2_defconfig b/configs/smarcimx8qm_8g_ser2_defconfig new file mode 100644 index 0000000..04303a9 --- /dev/null +++ b/configs/smarcimx8qm_8g_ser2_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,8GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER2=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/smarcimx8qm_8g_ser3_defconfig b/configs/smarcimx8qm_8g_ser3_defconfig new file mode 100644 index 0000000..ea1757c --- /dev/null +++ b/configs/smarcimx8qm_8g_ser3_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/embedian/smarcimx8qm/uboot-container.cfg,8GB_LPDDR4" +CONFIG_TARGET_SMARCIMX8QM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcimx8qm/imximage.cfg" +CONFIG_CONSOLE_SER3=y +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_SYS_PROMPT="u-boot$ " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8qm" +CONFIG_DEFAULT_FDT_FILE="imx8qm-smarc.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +#CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +#CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +#CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 7d1dc46..c796208 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -40,6 +40,7 @@ static struct imx8_clks imx8qm_clks[] = { CLK_4( IMX8QM_UART1_DIV, "UART1_DIV", SC_R_UART_1, SC_PM_CLK_PER ), CLK_4( IMX8QM_UART2_DIV, "UART2_DIV", SC_R_UART_2, SC_PM_CLK_PER ), CLK_4( IMX8QM_UART3_DIV, "UART3_DIV", SC_R_UART_3, SC_PM_CLK_PER ), + CLK_4( IMX8QM_UART4_DIV, "UART4_DIV", SC_R_UART_4, SC_PM_CLK_PER ), CLK_4( IMX8QM_SDHC0_DIV, "SDHC0_DIV", SC_R_SDHC_0, SC_PM_CLK_PER ), CLK_4( IMX8QM_SDHC1_DIV, "SDHC1_DIV", SC_R_SDHC_1, SC_PM_CLK_PER ), CLK_4( IMX8QM_SDHC2_DIV, "SDHC2_DIV", SC_R_SDHC_2, SC_PM_CLK_PER ), @@ -139,7 +140,8 @@ static struct imx8_lpcg_clks imx8qm_lpcg_clks[] = { CLK_5( IMX8QM_UART2_IPG_CLK, "UART2_IPG", 16, LPUART_2_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), CLK_5( IMX8QM_UART3_CLK, "UART3_CLK", 0, LPUART_3_LPCG, IMX8QM_UART3_DIV ), CLK_5( IMX8QM_UART3_IPG_CLK, "UART3_IPG", 16, LPUART_3_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), - + CLK_5( IMX8QM_UART4_CLK, "UART4_CLK", 0, LPUART_4_LPCG, IMX8QM_UART4_DIV ), + CLK_5( IMX8QM_UART4_IPG_CLK, "UART4_IPG", 16, LPUART_4_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), CLK_5( IMX8QM_SDHC0_CLK, "SDHC0_CLK", 0, USDHC_0_LPCG, IMX8QM_SDHC0_DIV ), CLK_5( IMX8QM_SDHC0_IPG_CLK, "SDHC0_IPG", 16, USDHC_0_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), CLK_5( IMX8QM_SDHC0_AHB_CLK, "SDHC0_AHB", 20, USDHC_0_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ), diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 31cf28e..bf1b14e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -763,6 +763,26 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config CONSOLE_SER0 + bool "SMARC modules default console serial output port" + help + Select this to enable a debug UART port from SER0 of SMARC Modules. + +config CONSOLE_SER1 + bool "SMARC modules default console serial output port" + help + Select this to enable a debug UART port from SER1 of SMARC Modules. + +config CONSOLE_SER2 + bool "SMARC modules default console serial output port" + help + Select this to enable a debug UART port from SER2 of SMARC Modules. + +config CONSOLE_SER3 + bool "SMARC modules default console serial output port" + help + Select this to enable a debug UART port from SER3 of SMARC Modules. + config SIFIVE_SERIAL bool "SiFive UART support" depends on DM_SERIAL diff --git a/include/configs/smarcimx8qm.h b/include/configs/smarcimx8qm.h new file mode 100644 index 0000000..8e5d92a --- /dev/null +++ b/include/configs/smarcimx8qm.h @@ -0,0 +1,433 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __SMARCIMX8QM_H +#define __SMARCIMX8QM_H + +#include +#include +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (192 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */ + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * 0x08181000 - 0x008280FFF is for m4_1 xip image + * So 3rd container image may start from 0x8281000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08281000 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x00130000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#ifdef CONFIG_CONSOLE_SER0 +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 /* lpuart0 */ +#endif +#ifdef CONFIG_CONSOLE_SER1 +#define CONFIG_SERIAL_LPUART_BASE 0x5a090000 /* lpuart3 */ +#endif +#ifdef CONFIG_CONSOLE_SER2 +#define CONFIG_SERIAL_LPUART_BASE 0x5a070000 /* lpuart1 */ +#endif +#ifdef CONFIG_CONSOLE_SER3 +#define CONFIG_SERIAL_LPUART_BASE 0x5a0a0000 /* lpuart4 */ +#endif +#define CONFIG_MALLOC_F_ADDR 0x00138000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +/*#undef CONFIG_CMD_IMPORTENV*/ +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define PHY_ANEG_TIMEOUT 20000 + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x6 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x7 +#define CONFIG_ETHPRIME "eth1" +#endif + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file imx8qm-smarc.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file imx8qm-smarc.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "domu-android-auto=no\0" \ + "xenhyper_bootargs=console=dtuart dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x9e000000\0" \ + "dom0fdt_file=imx8qm-mek-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "if test ${domu-android-auto} = yes; then; " \ + "fdt set /domu/doma android-auto <1>;" \ + "fdt rm /gpio@5d090000 power-domains;" \ + "fi;" \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "splashimage=0x9e000000\0" \ + "console=ttyLP1\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "env_addr=0x83200000\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "usbroot=/dev/sda2 rootwait ro\0" \ + "mmcrootfstype=ext4 \0" \ + "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${env_addr} uEnv.txt\0" \ + "loadusbbootenv=fatload usb 0:1 ${env_addr} uEnv.txt\0" \ + "mmcautodetect=yes\0" \ + "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \ + "env import -t ${env_addr} $filesize\0" \ + "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \ + "env import -t $env_addr $filesize\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \ + "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \ + "hdp_addr=0x9c000000\0" \ + "hdprx_addr=0x9c800000\0" \ + "hdp_file=hdmitxfw.bin\0" \ + "hdprx_file=hdmirxfw.bin\0" \ + "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ + "loadhdprx=fatload mmc ${mmcdev}:${mmcpart} ${hdprx_addr} ${hdprx_file}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "usbboot=echo Booting from usb ...; " \ + "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadusbfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "echo Checking for: uEnv.txt ...; " \ + "if test -e mmc ${bootpart} /uEnv.txt; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment from uEnv.txt;" \ + "run importbootenv;" \ + "fi;" \ + "echo Checking if uenvcmd is set ...;" \ + "if test -n ${uenvcmd}; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_CMD_PART +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#ifdef CONFIG_4GB_LPDDR4 +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ +#else +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) +#define IMX_HDMITX_FIRMWARE_SIZE 0x20000 +#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "smarcimx8qm_android.h" +#elif defined (CONFIG_ANDROID_AUTO_SUPPORT) +#include "smarcimx8qm_android_auto.h" +#elif defined(CONFIG_IMX8_TRUSTY_XEN) +#include "smarcimx8qm_trusty_xen.h" +#endif + +#endif /* __SMARCIMX8QM_H */ diff --git a/include/configs/smarcimx8qm_android.h b/include/configs/smarcimx8qm_android.h new file mode 100644 index 0000000..0768a58 --- /dev/null +++ b/include/configs/smarcimx8qm_android.h @@ -0,0 +1,47 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SMARCIMX8QM_ANDROID_H +#define SMARCIMX8QM_ANDROID_H + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_ANDROID_AB_SUPPORT +#ifdef CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#endif +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) +#define IMX_HDMITX_FIRMWARE_SIZE 0x20000 +#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 + +#define CONFIG_FASTBOOT_USB_DEV 1 + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "splashimage=0x9e000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NS_ARCH_ARM64 1 +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF +#define AVB_RPMB + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_BLK +#define CONFIG_FSL_CAAM_KB +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SYS_FSL_SEC_LE +#endif +#endif + +#endif /* SMARCIMX8QM_ANDROID_H */ diff --git a/include/configs/smarcimx8qm_android_auto.h b/include/configs/smarcimx8qm_android_auto.h new file mode 100644 index 0000000..912d23a --- /dev/null +++ b/include/configs/smarcimx8qm_android_auto.h @@ -0,0 +1,90 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SMARCIMX8QM_ANDROID_AUTO_H +#define SMARCIMX8QM_ANDROID_AUTO_H + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_SKIP_RESOURCE_CHECKING + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#ifndef CONFIG_MXC_USB_PORTSC +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#ifdef CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#endif +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) +#define IMX_HDMITX_FIRMWARE_SIZE 0x20000 +#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Undefine some macros to save boot time */ +#undef CONFIG_FEC_MXC +#undef CONFIG_USB_HOST_ETHER +#undef CONFIG_ARCH_MISC_INIT +#undef CONFIG_SCSI +#undef CONFIG_SCSI_AHCI +#undef CONFIG_SCSI_AHCI_PLAT +#undef CONFIG_CMD_SCSI +#undef CONFIG_LIBATA +#undef CONFIG_SATA_IMX +#undef CONFIG_FSL_HSIO +#undef CONFIG_PCIE_IMX8X +#undef CONFIG_CMD_PCI +#undef CONFIG_PCI +#undef CONFIG_SYS_LONGHELP +#undef CONFIG_AUTO_COMPLETE +#undef CONFIG_MII +#undef CONFIG_PHYLIB +#undef CONFIG_PHY_ATHEROS +#undef CONFIG_CMD_FUSE +#undef CONFIG_USB_FUNCTION_MASS_STORAGE +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_FAT_WRITE + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define NS_ARCH_ARM64 1 +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000 +#endif + + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_BLK +#define CONFIG_FSL_CAAM_KB +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SYS_FSL_SEC_LE +#endif + +#if defined(CONFIG_XEN) +#include "smarcimx8qm_android_auto_xen.h" +#endif + +#endif /* SMARCIMX8QM_ANDROID_AUTO_H */ diff --git a/include/configs/smarcimx8qm_android_auto_xen.h b/include/configs/smarcimx8qm_android_auto_xen.h new file mode 100644 index 0000000..601e577 --- /dev/null +++ b/include/configs/smarcimx8qm_android_auto_xen.h @@ -0,0 +1,51 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SMARCIMX8QM_ANDROID_AUTO_XEN_H +#define SMARCIMX8QM_ANDROID_AUTO_XEN_H + +#undef CONFIG_SYS_SDRAM_BASE +#undef CONFIG_NR_DRAM_BANKS +#undef PHYS_SDRAM_1 +#undef PHYS_SDRAM_2 +#undef PHYS_SDRAM_1_SIZE +#undef PHYS_SDRAM_2_SIZE + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x200000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x50000000 /* 1024 + 256 MB */ + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x80080000 +#undef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR 0x81200000 + +#undef CONFIG_REQUIRE_SERIAL_CONSOLE +#undef CONFIG_IMX_SMMU + +#undef CONFIG_FASTBOOT_USB_DEV +#define CONFIG_FASTBOOT_USB_DEV 0 /* Use OTG port, not typec port */ + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SPL_BSS_START_ADDR +#undef CONFIG_SYS_SPL_MALLOC_START +#undef CONFIG_MALLOC_F_ADDR +#undef CONFIG_SPL_TEXT_BASE +#undef CONFIG_SPL_STACK + +#define CONFIG_MALLOC_F_ADDR 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SPL_BSS_START_ADDR 0x80300000 +#define CONFIG_SPL_STACK 0x80400000 + +#undef CONFIG_SYS_SPL_PTE_RAM_BASE +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x80500000 +#endif + +#endif /* SMARCIMX8QM_ANDROID_AUTO_XEN_H */ diff --git a/include/configs/smarcimx8qm_trusty_xen.h b/include/configs/smarcimx8qm_trusty_xen.h new file mode 100644 index 0000000..3caf412 --- /dev/null +++ b/include/configs/smarcimx8qm_trusty_xen.h @@ -0,0 +1,19 @@ +/* + * Copyright 2020 NXP + * + */ + +#ifndef __SMARCIMX8QM_XEN_TRUSTY_H__ +#define __SMARCIMX8QM_XEN_TRUSTY_H__ + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_AVB_SUPPORT +#define AVB_RPMB +#define CONFIG_SHA256 +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF +#define CONFIG_SUPPORT_EMMC_RPMB +#endif + +#endif +