diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 09ebe00..3509ce9 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -105,6 +105,22 @@ config CMD_BEE help Set "Y" to enable the bee commands +config TARGET_MX6SABREAUTO + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select NXP_BOARD_REVISION + +config TARGET_MX6SABRESD + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select NXP_BOARD_REVISION + choice prompt "MX6 board select" optional @@ -260,23 +276,45 @@ config TARGET_MX6Q_ENGICAM select SPL_SEPARATE_BSS if SPL select SPL_PINCTRL if SPL -config TARGET_MX6SABREAUTO - bool "mx6sabreauto" - select MX6QDL - select BOARD_LATE_INIT - select SUPPORT_SPL - select DM - select DM_THERMAL - select BOARD_EARLY_INIT_F - -config TARGET_MX6SABRESD - bool "mx6sabresd" - select MX6QDL - select BOARD_LATE_INIT - select SUPPORT_SPL - select DM - select DM_THERMAL - select BOARD_EARLY_INIT_F +config TARGET_MX6QSABREAUTO + bool "mx6qsabreauto" + select TARGET_MX6SABREAUTO + select MX6Q + +config TARGET_MX6QPSABREAUTO + bool "mx6qpsabreauto" + select TARGET_MX6SABREAUTO + select MX6QP + +config TARGET_MX6DLSABREAUTO + bool "mx6dlsabreauto" + select TARGET_MX6SABREAUTO + select MX6DL + +config TARGET_MX6SOLOSABREAUTO + bool "mx6solosabreauto" + select TARGET_MX6SABREAUTO + select MX6S + +config TARGET_MX6QSABRESD + bool "mx6qsabresd" + select TARGET_MX6SABRESD + select MX6Q + +config TARGET_MX6QPSABRESD + bool "mx6qpsabresd" + select TARGET_MX6SABRESD + select MX6QP + +config TARGET_MX6DLSABRESD + bool "mx6dlsabresd" + select TARGET_MX6SABRESD + select MX6DL + +config TARGET_MX6SOLOSABRESD + bool "mx6solosabresd" + select TARGET_MX6SABRESD + select MX6S config TARGET_MX6SLEVK bool "mx6slevk" diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig index 5b4faf6..3a63229 100644 --- a/board/freescale/mx6sabreauto/Kconfig +++ b/board/freescale/mx6sabreauto/Kconfig @@ -9,4 +9,12 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sabreauto" +config SYS_TEXT_BASE + default 0x17800000 + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. endif diff --git a/board/freescale/mx6sabreauto/imximage.cfg b/board/freescale/mx6sabreauto/imximage.cfg new file mode 100644 index 0000000..3df5725 --- /dev/null +++ b/board/freescale/mx6sabreauto/imximage.cfg @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000028 +DATA 4 0x020e05b0 0x00000028 +DATA 4 0x020e0524 0x00000028 +DATA 4 0x020e051c 0x00000028 +DATA 4 0x020e0518 0x00000028 +DATA 4 0x020e050c 0x00000028 +DATA 4 0x020e05b8 0x00000028 +DATA 4 0x020e05c0 0x00000028 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e0788 0x00000028 +DATA 4 0x020e0794 0x00000028 +DATA 4 0x020e079c 0x00000028 +DATA 4 0x020e07a0 0x00000028 +DATA 4 0x020e07a4 0x00000028 +DATA 4 0x020e07a8 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e05ac 0x00000028 +DATA 4 0x020e05b4 0x00000028 +DATA 4 0x020e0528 0x00000028 +DATA 4 0x020e0520 0x00000028 +DATA 4 0x020e0514 0x00000028 +DATA 4 0x020e0510 0x00000028 +DATA 4 0x020e05bc 0x00000028 +DATA 4 0x020e05c4 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43260335 +DATA 4 0x021b0840 0x031A030B +DATA 4 0x021b483c 0x4323033B +DATA 4 0x021b4840 0x0323026F +DATA 4 0x021b0848 0x483D4545 +DATA 4 0x021b4848 0x44433E48 +DATA 4 0x021b0850 0x41444840 +DATA 4 0x021b4850 0x4835483E +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x8A8F7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008F1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/mx6dl.cfg b/board/freescale/mx6sabreauto/mx6dl.cfg new file mode 100644 index 0000000..06b23ef --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6dl.cfg @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000028 +DATA 4 0x020e04c0 0x00000028 +DATA 4 0x020e04c4 0x00000028 +DATA 4 0x020e04c8 0x00000028 +DATA 4 0x020e04cc 0x00000028 +DATA 4 0x020e04d0 0x00000028 +DATA 4 0x020e04d4 0x00000028 +DATA 4 0x020e04d8 0x00000028 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000028 +DATA 4 0x020e0770 0x00000028 +DATA 4 0x020e0778 0x00000028 +DATA 4 0x020e077c 0x00000028 +DATA 4 0x020e0780 0x00000028 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e078c 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e0470 0x00000028 +DATA 4 0x020e0474 0x00000028 +DATA 4 0x020e0478 0x00000028 +DATA 4 0x020e047c 0x00000028 +DATA 4 0x020e0480 0x00000028 +DATA 4 0x020e0484 0x00000028 +DATA 4 0x020e0488 0x00000028 +DATA 4 0x020e048c 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x42190217 +DATA 4 0x021b0840 0x017B017B +DATA 4 0x021b483c 0x4176017B +DATA 4 0x021b4840 0x015F016C +DATA 4 0x021b0848 0x4C4C4D4C +DATA 4 0x021b4848 0x4A4D4C48 +DATA 4 0x021b0850 0x3F3F3F40 +DATA 4 0x021b4850 0x3538382E +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020025 +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676B5313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006B1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025565 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/mx6qp.cfg b/board/freescale/mx6sabreauto/mx6qp.cfg new file mode 100644 index 0000000..4511971 --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6qp.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08c0 0x24912249 +DATA 4 0x021b48c0 0x24914289 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x24444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF320F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 + +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0400 0x14420000 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b0890 0x00400C58 +DATA 4 0x00bb0008 0x00000000 +DATA 4 0x00bb000c 0x2891E41A +DATA 4 0x00bb0038 0x00000564 +DATA 4 0x00bb0014 0x00000040 +DATA 4 0x00bb0028 0x00000020 +DATA 4 0x00bb002c 0x00000020 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index 52b016b..2f99be7 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Author: Fabio Estevam * @@ -33,6 +34,16 @@ #include #include "../common/pfuze.h" +#ifdef CONFIG_SATA +#include +#endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -43,6 +54,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +/*Need more drive strength for SD1 slot on base board*/ +#define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -57,10 +73,18 @@ DECLARE_GLOBAL_DATA_PTR; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + #define I2C_PMIC 1 int dram_init(void) @@ -91,31 +115,20 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), }; +#ifdef CONFIG_SYS_I2C /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ -static struct i2c_pads_info mx6q_i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC, + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, .gp = IMX_GPIO_NR(2, 30) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -125,32 +138,20 @@ static struct i2c_pads_info mx6dl_i2c_pad_info1 = { * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, * Compass Sensor, Accelerometer, Res Touch */ -static struct i2c_pads_info mx6q_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { - .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC, + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, .gp = IMX_GPIO_NR(3, 18) } }; #endif +#endif static iomux_v3_cfg_t const i2c3_pads[] = { IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -160,6 +161,8 @@ static iomux_v3_cfg_t const port_exp[] = { IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +#ifdef CONFIG_PCA953X + /*Define for building port exp gpio, pin starts from 0*/ #define PORTEXP_IO_NR(chip, pin) \ ((chip << 5) + pin) @@ -197,6 +200,7 @@ static int port_exp_direction_output(unsigned gpio, int value) return 0; } +#endif #ifdef CONFIG_MTD_NOR_FLASH static iomux_v3_cfg_t const eimnor_pads[] = { @@ -301,6 +305,19 @@ static void setup_iomux_enet(void) SETUP_IOMUX_PADS(enet_pads); } +static iomux_v3_cfg_t const usdhc1_pads[] = { + /*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/ + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + + /*CD pin*/ + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -322,22 +339,89 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_ESDHC -static struct fsl_esdhc_cfg usdhc_cfg[1] = { + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) +#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15) + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR}, }; +int board_mmc_get_env_dev(int devno) +{ + /* + * need ubstract 1 to map to the mmc3 device id + * see the comments in board_mmc_init function + */ + if (devno == 2) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + if (devno == 1) + devno = 2; + + return devno; +} + int board_mmc_getcd(struct mmc *mmc) { - gpio_direction_input(IMX_GPIO_NR(6, 15)); - return !gpio_get_value(IMX_GPIO_NR(6, 15)); + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + gpio_direction_input(USDHC1_CD_GPIO); + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + gpio_direction_input(USDHC3_CD_GPIO); + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - SETUP_IOMUX_PADS(usdhc3_pads); + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + return 0; } #endif @@ -379,20 +463,25 @@ static void setup_gpmi_nand(void) static void setup_fec(void) { + int ret; + if (is_mx6dqp()) { /* * select ENET MAC0 TX clock from PLL */ imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(0, ENET_125MHZ); + } else { + imx_iomux_set_gpr_register(1, 21, 1, 1); } - setup_iomux_enet(); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + printf("Error fec anatop clock settings!\n"); } int board_eth_init(bd_t *bis) { - setup_fec(); + setup_iomux_enet(); return cpu_eth_init(bis); } @@ -477,7 +566,7 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, + .detect = NULL, .enable = do_enable_hdmi, .mode = { .name = "HDMI", @@ -502,6 +591,7 @@ iomux_v3_cfg_t const backlight_pads[] = { static void setup_iomux_backlight(void) { + gpio_request(IMX_GPIO_NR(2, 9), "backlight"); gpio_direction_output(IMX_GPIO_NR(2, 9), 1); SETUP_IOMUX_PADS(backlight_pads); } @@ -570,6 +660,31 @@ int overwrite_console(void) return 1; } +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* Steer logic */ + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + + gpio_request(IMX_GPIO_NR(3, 19), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + gpio_direction_output(IMX_GPIO_NR(3, 19), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(3, 19)) : -1; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -589,20 +704,20 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#ifndef CONFIG_SYS_FLASH_CFI + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif +#endif + /* I2C 3 Steer */ + gpio_request(IMX_GPIO_NR(5, 4), "steer logic"); gpio_direction_output(IMX_GPIO_NR(5, 4), 1); SETUP_IOMUX_PADS(i2c3_pads); -#ifndef CONFIG_SYS_FLASH_CFI - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); - else - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); -#endif + + gpio_request(IMX_GPIO_NR(1, 15), "expander en"); gpio_direction_output(IMX_GPIO_NR(1, 15), 1); SETUP_IOMUX_PADS(port_exp); @@ -610,38 +725,235 @@ int board_init(void) setup_display(); #endif +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_SATA + setup_sata(); +#endif + #ifdef CONFIG_MTD_NOR_FLASH setup_iomux_eimnor(); #endif - return 0; -} -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; -} +#ifdef CONFIG_FEC_MXC + setup_fec(); #endif + return 0; +} + +#ifdef CONFIG_POWER int power_init_board(void) { - struct pmic *p; + struct pmic *pfuze; unsigned int value; + int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) return -ENODEV; + if (is_mx6dqp()) + ret = pfuze_mode_init(pfuze, APS_APS); + else + ret = pfuze_mode_init(pfuze, APS_PFM); + + if (ret < 0) + return ret; + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1f; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); + /* set SW2 staby volatage 0.975V*/ - pmic_reg_read(p, PFUZE100_SW2STBY, &value); + pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value); value &= ~0x3f; value |= 0x17; - pmic_reg_write(p, PFUZE100_SW2STBY, value); + pmic_reg_write(pfuze, PFUZE100_SW2STBY, value); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, value); + } else { + /* set SW1AB staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* set SW1C staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); } - return pfuze_mode_init(p, APS_PFM); + return 0; } +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + if (is_mx6dqp()) + ret = pfuze_mode_init(dev, APS_APS); + else + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW2STBY); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW2CONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + } + + return 0; +} +#endif + +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x29; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + } +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29); + } else { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d); + } + /* increase VDDSOC to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d); + } +} +#endif +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { @@ -668,6 +980,10 @@ int board_late_init(void) env_set("board_rev", "MX6DL"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } @@ -679,11 +995,31 @@ int checkboard(void) } #ifdef CONFIG_USB_EHCI_MX6 +#ifdef CONFIG_DM_USB +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} +#else #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) iomux_v3_cfg_t const usb_otg_pads[] = { - IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL)), }; int board_ehci_hcd_init(int port) @@ -709,6 +1045,7 @@ int board_ehci_hcd_init(int port) int board_ehci_power(int port, int on) { +#ifdef CONFIG_PCA953X switch (port) { case 0: if (on) @@ -726,10 +1063,77 @@ int board_ehci_power(int port, int on) printf("MXC USB port %d not yet supported\n", port); return -EINVAL; } +#elif defined(CONFIG_DM_PCA953X) + struct gpio_desc desc; + int ret; + + switch (port) { + case 0: + ret = dm_gpio_lookup_name("gpio@34_1", &desc); + if (ret) + return ret; + + dm_gpio_request(&desc, "usb_otg_pwr"); + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + + if (on) + dm_gpio_set_value(&desc, 1); + else + dm_gpio_set_value(&desc, 0); + break; + case 1: + ret = dm_gpio_lookup_name("gpio@32_7", &desc); + if (ret) + return ret; + dm_gpio_request(&desc, "usb_host1_pwr"); + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + + if (on) + dm_gpio_set_value(&desc, 1); + else + dm_gpio_set_value(&desc, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } +#endif return 0; } #endif +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 14) +iomux_v3_cfg_t const recovery_key_pads[] = { + IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + SETUP_IOMUX_PADS(recovery_key_pads); + + gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include diff --git a/board/freescale/mx6sabreauto/mx6solo.cfg b/board/freescale/mx6sabreauto/mx6solo.cfg new file mode 100644 index 0000000..22a0247 --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6solo.cfg @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000028 +DATA 4, 0x020e04c0, 0x00000028 +DATA 4, 0x020e04c4, 0x00000028 +DATA 4, 0x020e04c8, 0x00000028 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000028 +DATA 4, 0x020e0770, 0x00000028 +DATA 4, 0x020e0778, 0x00000028 +DATA 4, 0x020e077c, 0x00000028 +DATA 4, 0x020e0470, 0x00000028 +DATA 4, 0x020e0474, 0x00000028 +DATA 4, 0x020e0478, 0x00000028 +DATA 4, 0x020e047c, 0x00000028 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x421C0216 +DATA 4, 0x021b0840, 0x017B017A +DATA 4, 0x021b0848, 0x4B4A4E4C +DATA 4, 0x021b0850, 0x3F3F3334 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020025 +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x676B5313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x006B1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0000, 0x84190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x00025565 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/plugin.S b/board/freescale/mx6sabreauto/plugin.S new file mode 100644 index 0000000..443e6e2 --- /dev/null +++ b/board/freescale/mx6sabreauto/plugin.S @@ -0,0 +1,667 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6dqpsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001b001e + str r2, [r0, #0x80c] + ldr r2, =0x002e0029 + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x001b002a + str r2, [r1, #0x80c] + ldr r2, =0x0019002c + str r2, [r1, #0x810] + + ldr r2, =0x43240334 + str r2, [r0, #0x83c] + ldr r2, =0x0324031a + str r2, [r0, #0x840] + + ldr r2, =0x43340344 + str r2, [r1, #0x83c] + ldr r2, =0x03280276 + str r2, [r1, #0x840] + + ldr r2, =0x44383A3E + str r2, [r0, #0x848] + ldr r2, =0x3C3C3846 + str r2, [r1, #0x848] + + ldr r2, =0x2e303230 + str r2, [r0, #0x850] + ldr r2, =0x38283E34 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x24912249 + str r2, [r0, #0x8c0] + ldr r2, =0x24914289 + str r2, [r1, #0x8c0] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x24444040 + str r2, [r0, #0x008] + + ldr r2, =0x898E7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF320F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x008E1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x14420000 + str r2, [r0, #0x400] + ldr r2, =0x841A0000 + str r2, [r0, #0x000] + + ldr r2, =0x00400C58 + str r2, [r0, #0x890] + + ldr r3, =0x00bb0000 + ldr r2, =0x00000000 + str r2, [r3, #0x008] + ldr r2, =0x2891E41A + str r2, [r3, #0x00c] + ldr r2, =0x00000564 + str r2, [r3, #0x038] + ldr r2, =0x00000040 + str r2, [r3, #0x014] + ldr r2, =0x00000020 + str r2, [r3, #0x028] + str r2, [r3, #0x02c] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000028 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x43260335 + str r2, [r0, #0x83c] + ldr r2, =0x031A030B + str r2, [r0, #0x840] + + ldr r2, =0x4323033B + str r2, [r1, #0x83c] + ldr r2, =0x0323026F + str r2, [r1, #0x840] + + ldr r2, =0x483D4545 + str r2, [r0, #0x848] + ldr r2, =0x44433E48 + str r2, [r1, #0x848] + + ldr r2, =0x41444840 + str r2, [r0, #0x850] + ldr r2, =0x4835483E + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + + ldr r2, =0x8A8F7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF328F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x008F1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x841A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000028 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001f001f + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x42190217 + str r2, [r0, #0x83c] + ldr r2, =0x017b017b + str r2, [r0, #0x840] + + ldr r2, =0x4176017b + str r2, [r1, #0x83c] + ldr r2, =0x015f016c + str r2, [r1, #0x840] + + ldr r2, =0x4c4c4d4c + str r2, [r0, #0x848] + ldr r2, =0x4a4d4c48 + str r2, [r1, #0x848] + + ldr r2, =0x3f3f3f40 + str r2, [r0, #0x850] + ldr r2, =0x3538382e + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020025 + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x676b5313 + str r2, [r0, #0x00c] + ldr r2, =0xb66e8b63 + str r2, [r0, #0x010] + + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x841a0000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025565 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6solosabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000028 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x421C0216 + str r2, [r0, #0x83c] + ldr r2, =0x017B017A + str r2, [r0, #0x840] + + ldr r2, =0x4B4A4E4C + str r2, [r0, #0x848] + + ldr r2, =0x3F3F3334 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x00020025 + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x676B5313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006B1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x84190000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00025565 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00C03F3F + str r1, [r0, #0x068] + ldr r1, =0x0030FC03 + str r1, [r0, #0x06c] + ldr r1, =0x0FFFC000 + str r1, [r0, #0x070] + ldr r1, =0x3FF00000 + str r1, [r0, #0x074] + ldr r1, =0xFFFFF300 + str r1, [r0, #0x078] + ldr r1, =0x0F0000C3 + str r1, [r0, #0x07c] + ldr r1, =0x00000FFF + str r1, [r0, #0x080] +.endm + +.macro imx6_qos_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + +#if defined(CONFIG_MX6QP) + ldr r1, =0x77177717 + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#else + ldr r1, =0x007F007F + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#endif +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6S) + imx6solosabreauto_ddr_setting +#elif defined (CONFIG_MX6DL) + imx6dlsabreauto_ddr_setting +#elif defined (CONFIG_MX6QP) + imx6dqpsabreauto_ddr_setting +#elif defined (CONFIG_MX6Q) + imx6dqsabreauto_ddr_setting +#else + #error "SOC not configured" +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig index e87dea0..f782239 100644 --- a/board/freescale/mx6sabresd/Kconfig +++ b/board/freescale/mx6sabresd/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sabresd" +config SYS_TEXT_BASE + default 0x17800000 + endif diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg new file mode 100644 index 0000000..de1457e --- /dev/null +++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000030 +DATA 4 0x020e04c0 0x00000030 +DATA 4 0x020e04c4 0x00000030 +DATA 4 0x020e04c8 0x00000030 +DATA 4 0x020e04cc 0x00000030 +DATA 4 0x020e04d0 0x00000030 +DATA 4 0x020e04d4 0x00000030 +DATA 4 0x020e04d8 0x00000030 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000030 +DATA 4 0x020e0770 0x00000030 +DATA 4 0x020e0778 0x00000030 +DATA 4 0x020e077c 0x00000030 +DATA 4 0x020e0780 0x00000030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e0470 0x00000030 +DATA 4 0x020e0474 0x00000030 +DATA 4 0x020e0478 0x00000030 +DATA 4 0x020e047c 0x00000030 +DATA 4 0x020e0480 0x00000030 +DATA 4 0x020e0484 0x00000030 +DATA 4 0x020e0488 0x00000030 +DATA 4 0x020e048c 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x4220021F +DATA 4 0x021b0840 0x0207017E +DATA 4 0x021b483c 0x4201020C +DATA 4 0x021b4840 0x01660172 +DATA 4 0x021b0848 0x4A4D4E4D +DATA 4 0x021b4848 0x4A4F5049 +DATA 4 0x021b0850 0x3F3C3D31 +DATA 4 0x021b4850 0x3238372B +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x3F435313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00431023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg new file mode 100644 index 0000000..10ba30c --- /dev/null +++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43270338 +DATA 4 0x021b0840 0x03200314 +DATA 4 0x021b483c 0x431A032F +DATA 4 0x021b4840 0x03200263 +DATA 4 0x021b0848 0x4B434748 +DATA 4 0x021b4848 0x4445404C +DATA 4 0x021b0850 0x38444542 +DATA 4 0x021b4850 0x4935493A +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x555A7975 +DATA 4 0x021b0010 0xFF538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb +#endif diff --git a/board/freescale/mx6sabresd/mx6qp.cfg b/board/freescale/mx6sabresd/mx6qp.cfg new file mode 100644 index 0000000..e97863d --- /dev/null +++ b/board/freescale/mx6sabresd/mx6qp.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0798, 0x000c0000 +DATA 4, 0x020e0758, 0x00000000 +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 + +DATA 4, 0x020e0534, 0x00018200 +DATA 4, 0x020e0538, 0x00008000 +DATA 4, 0x020e053c, 0x00018200 +DATA 4, 0x020e0540, 0x00018200 +DATA 4, 0x020e0544, 0x00018200 +DATA 4, 0x020e0548, 0x00018200 +DATA 4, 0x020e054c, 0x00018200 +DATA 4, 0x020e0550, 0x00018200 + +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001b001e +DATA 4, 0x021b0810, 0x002e0029 +DATA 4, 0x021b480c, 0x001b002a +DATA 4, 0x021b4810, 0x0019002c +DATA 4, 0x021b083c, 0x43240334 +DATA 4, 0x021b0840, 0x0324031a +DATA 4, 0x021b483c, 0x43340344 +DATA 4, 0x021b4840, 0x03280276 +DATA 4, 0x021b0848, 0x44383A3E +DATA 4, 0x021b4848, 0x3C3C3846 +DATA 4, 0x021b0850, 0x2e303230 +DATA 4, 0x021b4850, 0x38283E34 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b08c0, 0x24912489 +DATA 4, 0x021b48c0, 0x24914452 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x24444040 +DATA 4, 0x021b000c, 0x555A7955 +DATA 4, 0x021b0010, 0xFF320F64 +DATA 4, 0x021b0014, 0x01ff00db +DATA 4, 0x021b0018, 0x00011740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x005A1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0400, 0x14420000 +DATA 4, 0x021b0000, 0x831A0000 +DATA 4, 0x021b0890, 0x00400C58 +DATA 4, 0x00bb0008, 0x00000000 +DATA 4, 0x00bb000c, 0x2891E41A +DATA 4, 0x00bb0038, 0x00000564 +DATA 4, 0x00bb0014, 0x00000040 +DATA 4, 0x00bb0028, 0x00000020 +DATA 4, 0x00bb002c, 0x00000020 +DATA 4, 0x021b001c, 0x04088032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x09408030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b4818, 0x00011117 +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index d75dd88..b86d5be 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Author: Fabio Estevam * @@ -32,6 +33,20 @@ #include "../common/pfuze.h" #include #include +#include +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#ifdef CONFIG_SATA +#include +#endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -53,6 +68,14 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + #define I2C_PMIC 1 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -92,17 +115,22 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static void setup_iomux_enet(void) +static void fec_phy_reset(void) { - SETUP_IOMUX_PADS(enet_pads); - /* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset"); gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 25), 1); udelay(100); } +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + fec_phy_reset(); +} + static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -144,6 +172,7 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; +#ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), @@ -151,6 +180,18 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +static void setup_spi(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 9), "ECSPI1 CS"); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + static iomux_v3_cfg_t const rgb_pads[] = { IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -190,6 +231,7 @@ static iomux_v3_cfg_t const bl_pads[] = { static void enable_backlight(void) { SETUP_IOMUX_PADS(bl_pads); + gpio_request(DISP0_PWR_EN, "Display Power Enable"); gpio_direction_output(DISP0_PWR_EN, 1); } @@ -204,37 +246,22 @@ static void enable_lvds(struct display_info_t const *dev) enable_backlight(); } -static struct i2c_pads_info mx6q_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { +#ifdef CONFIG_SYS_I2C +static struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, .gp = IMX_GPIO_NR(4, 13) } }; +#endif -static void setup_spi(void) -{ - SETUP_IOMUX_PADS(ecspi1_pads); -} - +#ifdef CONFIG_PCIE_IMX iomux_v3_cfg_t const pcie_pads[] = { IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */ @@ -243,7 +270,10 @@ iomux_v3_cfg_t const pcie_pads[] = { static void setup_pcie(void) { SETUP_IOMUX_PADS(pcie_pads); + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable"); + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset"); } +#endif iomux_v3_cfg_t const di0_pads[] = { IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */ @@ -256,6 +286,54 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +static iomux_v3_cfg_t const epdc_enable_pads[] = { + IOMUX_PADS(PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22), + IOMUX_PADS(PAD_EIM_DA10__GPIO3_IO10), + IOMUX_PADS(PAD_EIM_DA12__GPIO3_IO12), + IOMUX_PADS(PAD_EIM_DA11__GPIO3_IO11), + IOMUX_PADS(PAD_EIM_LBA__GPIO2_IO27), + IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30), + IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23), + IOMUX_PADS(PAD_EIM_RW__GPIO2_IO26), + IOMUX_PADS(PAD_EIM_A21__GPIO2_IO17), + IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16), + IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06), + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31), + IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27), + IOMUX_PADS(PAD_EIM_DA1__GPIO3_IO01), + IOMUX_PADS(PAD_EIM_EB1__GPIO2_IO29), + IOMUX_PADS(PAD_EIM_DA2__GPIO3_IO02), + IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04), + IOMUX_PADS(PAD_EIM_DA5__GPIO3_IO05), + IOMUX_PADS(PAD_EIM_DA6__GPIO3_IO06), +}; +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR}, @@ -271,6 +349,11 @@ int board_mmc_get_env_dev(int devno) return devno - 1; } +int mmc_map_to_kernel_blk(int devno) +{ + return devno + 1; +} + int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; @@ -308,11 +391,13 @@ int board_mmc_init(bd_t *bis) switch (i) { case 0: SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "USDHC2 CD"); gpio_direction_input(USDHC2_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; case 1: SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "USDHC3 CD"); gpio_direction_input(USDHC3_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; @@ -376,14 +461,20 @@ static int ar8031_phy_fixup(struct phy_device *phydev) unsigned short val; /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + if (!is_mx6dqp()) { + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + } - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + /* set the IO voltage to 1.8v */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); /* introduce tx clock delay */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); @@ -404,6 +495,176 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 800, + .vl_row = 600, + .vl_pixclock = 26666667, + .vl_left_margin = 8, + .vl_right_margin = 100, + .vl_upper_margin = 4, + .vl_lower_margin = 8, + .vl_hsync = 4, + .vl_vsync = 1, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 419, + .gdsp_offs = 20, + .gdoe_offs = 0, + .gdclk_offs = 5, + .num_ce = 1, +}; + +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = { + IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static void setup_epdc_power(void) +{ + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads); + + /* Setup epdc voltage */ + + /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ + /* Set as input */ + gpio_request(IMX_GPIO_NR(2, 21), "EPDC PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(2, 21)); + + /* EIM_D17 - GPIO3[17] for VCOM control */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 17), "EPDC VCOM0"); + gpio_direction_output(IMX_GPIO_NR(3, 17), 1); + + /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 20), "EPDC PWR WAKEUP"); + gpio_direction_output(IMX_GPIO_NR(3, 20), 1); + + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 20), "EPDC PWR CTRL0"); + gpio_direction_output(IMX_GPIO_NR(2, 20), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + SETUP_IOMUX_PADS(epdc_enable_pads); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO */ + SETUP_IOMUX_PADS(epdc_disable_pads); +} + +static void setup_epdc(void) +{ + unsigned int reg; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ + reg = readl(&ccm_regs->cscdr3); + reg &= ~0x7C000; + reg |= (1 << 16) | (1 << 14); + writel(reg, &ccm_regs->cscdr3); + + /* EPDC AXI clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x00C0; + writel(reg, &ccm_regs->CCGR3); + + /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ + reg = readl(&ccm_regs->cscdr2); + reg &= ~0x3FE00; + reg |= (2 << 15) | (5 << 12); + writel(reg, &ccm_regs->cscdr2); + + /* PLL5 enable (defaults to 650) */ + reg = readl(&ccm_regs->analog_pll_video); + reg &= ~((1 << 16) | (1 << 12)); + reg |= (1 << 13); + writel(reg, &ccm_regs->analog_pll_video); + + /* EPDC PIX clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0C00; + writel(reg, &ccm_regs->CCGR3); + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 21))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 0); +} +#endif + #if defined(CONFIG_VIDEO_IPUV3) static void disable_lvds(struct display_info_t const *dev) { @@ -447,7 +708,7 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, + .detect = NULL, .enable = do_enable_hdmi, .mode = { .name = "HDMI", @@ -551,15 +812,48 @@ int overwrite_console(void) return 1; } +static void setup_fec(void) +{ + if (is_mx6dqp()) { + int ret; + + /* select ENET MAC0 TX clock from PLL */ + imx_iomux_set_gpr_register(5, 9, 1, 1); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + printf("Error fec anatop clock settings!\n"); + } + + fec_phy_reset(); +} + int board_eth_init(bd_t *bis) { setup_iomux_enet(); - setup_pcie(); - return cpu_eth_init(bis); } #ifdef CONFIG_USB_EHCI_MX6 +#ifdef CONFIG_DM_USB +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} +#else #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) @@ -572,30 +866,33 @@ static iomux_v3_cfg_t const usb_hc1_pads[] = { IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static void setup_usb(void) -{ - SETUP_IOMUX_PADS(usb_otg_pads); - - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 0); - - SETUP_IOMUX_PADS(usb_hc1_pads); -} - int board_ehci_hcd_init(int port) { u32 *usbnc_usb_ctrl; - if (port > 1) - return -EINVAL; + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg_pads); - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + port * 4); - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + break; + case 1: + SETUP_IOMUX_PADS(usb_hc1_pads); + gpio_request(IMX_GPIO_NR(1, 29), "USB HC1 Power Enable"); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } return 0; } @@ -619,10 +916,14 @@ int board_ehci_power(int port, int on) return 0; } #endif +#endif int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } @@ -635,55 +936,393 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); + +#ifdef CONFIG_SYS_I2C + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); + +#ifdef CONFIG_PCIE_IMX + setup_pcie(); +#endif + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) + setup_epdc(); #endif +#ifdef CONFIG_SATA + setup_sata(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +#ifdef CONFIG_POWER +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + if (is_mx6dqp()) + ret = pfuze_mode_init(pfuze, APS_APS); + else + ret = pfuze_mode_init(pfuze, APS_PFM); + + if (ret < 0) + return ret; + /* VGEN3 and VGEN5 corrected on i.mx6qp board */ + if (!is_mx6dqp()) { + /* Increase VGEN3 from 2.5 to 2.8V */ + pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); + } + + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW2STBY, ®); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + } + return 0; } +#elif defined(CONFIG_DM_PMIC_PFUZE100) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; unsigned int reg; int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + dev = pfuze_common_init(); + if (!dev) return -ENODEV; - ret = pfuze_mode_init(p, APS_PFM); + if (is_mx6dqp()) + ret = pfuze_mode_init(dev, APS_APS); + else + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; - /* Increase VGEN3 from 2.5 to 2.8V */ - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_2_80V; - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + /* VGEN3 and VGEN5 corrected on i.mx6qp board */ + if (!is_mx6dqp()) { + /* Increase VGEN3 from 2.5 to 2.8V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + } - /* Increase VGEN5 from 2.8 to 3V */ - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_3_00V; - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW2STBY); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW2CONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + } return 0; } +#endif -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) { - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; + unsigned int value; + int is_400M; + unsigned char vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x29; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + if (is_mx6dqp()) { + /* decrease VDDARM for 400Mhz DQP:1.1V*/ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x1c; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + if (is_mx6dl()) + value |= 0x27; + else + value |= 0x20; + + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x28; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + /* + * MX6Q/DQP: + * VDDARM:1.15V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + * MX6DL: + * VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M + */ + is_400M = set_anatop_bypass(2); + if (is_mx6dqp()) { + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + if (is_400M) + value |= 0x17; + else + value |= 0x1e; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } + + if (is_400M) { + if (is_mx6dl()) + vddarm = 0x22; + else + vddarm = 0x1b; + } else { + if (is_mx6dl()) + vddarm = 0x23; + else + vddarm = 0x22; + } + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.175V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + int is_400M; + unsigned char vddarm; + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29); + } else { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d); + } + /* increase VDDSOC to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d); + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + if (is_mx6dqp()) { + /* decrease VDDARM for 400Mhz DQP:1.1V*/ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c); + } else { + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + if (is_mx6dl()) + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27); + else + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20); + } + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28); + + /* + * MX6Q/DQP: + * VDDARM:1.15V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + * MX6DL: + * VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M + */ + is_400M = set_anatop_bypass(2); + if (is_mx6dqp()) { + if (is_400M) + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17); + else + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e); + } + + if (is_400M) { + if (is_mx6dl()) + vddarm = 0x22; + else + vddarm = 0x1b; + } else { + if (is_mx6dl()) + vddarm = 0x23; + else + vddarm = 0x22; + } + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } } #endif +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { @@ -713,6 +1352,10 @@ int board_late_init(void) env_set("board_rev", "MX6DL"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } @@ -722,6 +1365,36 @@ int checkboard(void) return 0; } +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5) +iomux_v3_cfg_t const recovery_key_pads[] = { + IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + SET_IOMUX_PADS(recovery_key_pads); + + gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include #include @@ -730,6 +1403,7 @@ int checkboard(void) #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { + gpio_request(KEY_VOL_UP, "KEY Volume UP"); gpio_direction_input(KEY_VOL_UP); /* Only enter in Falcon mode if KEY_VOL_UP is pressed */ diff --git a/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg new file mode 100644 index 0000000..c2fcbd9 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000030 +DATA 4, 0x020e04c0, 0x00000030 +DATA 4, 0x020e04c4, 0x00000030 +DATA 4, 0x020e04c8, 0x00000030 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000030 +DATA 4, 0x020e0770, 0x00000030 +DATA 4, 0x020e0778, 0x00000030 +DATA 4, 0x020e077c, 0x00000030 +DATA 4, 0x020e0470, 0x00000030 +DATA 4, 0x020e0474, 0x00000030 +DATA 4, 0x020e0478, 0x00000030 +DATA 4, 0x020e047c, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x42190219 +DATA 4, 0x021b0840, 0x017B0177 +DATA 4, 0x021b0848, 0x4B4D4E4D +DATA 4, 0x021b0850, 0x3F3E2D36 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x0002002D +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x3F435313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x00431023 +DATA 4, 0x021b0040, 0x00000017 +DATA 4, 0x021b0000, 0x83190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x0002556D +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif diff --git a/board/freescale/mx6sabresd/plugin.S b/board/freescale/mx6sabresd/plugin.S new file mode 100644 index 0000000..b748676 --- /dev/null +++ b/board/freescale/mx6sabresd/plugin.S @@ -0,0 +1,683 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6dqpsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00018200 + str r1, [r0, #0x534] + ldr r1, =0x00008000 + str r1, [r0, #0x538] + ldr r1, =0x00018200 + str r1, [r0, #0x53c] + str r1, [r0, #0x540] + str r1, [r0, #0x544] + str r1, [r0, #0x548] + str r1, [r0, #0x54c] + str r1, [r0, #0x550] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001b001e + str r2, [r0, #0x80c] + ldr r2, =0x002e0029 + str r2, [r0, #0x810] + + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x001b002a + str r2, [r1, #0x80c] + ldr r2, =0x0019002c + str r2, [r1, #0x810] + + ldr r2, =0x43240334 + str r2, [r0, #0x83c] + ldr r2, =0x0324031a + str r2, [r0, #0x840] + + ldr r2, =0x43340344 + str r2, [r1, #0x83c] + ldr r2, =0x03280276 + str r2, [r1, #0x840] + + ldr r2, =0x44383A3E + str r2, [r0, #0x848] + ldr r2, =0x3C3C3846 + str r2, [r1, #0x848] + + ldr r2, =0x2e303230 + str r2, [r0, #0x850] + ldr r2, =0x38283E34 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x24912489 + str r2, [r0, #0x8c0] + ldr r2, =0x24914452 + str r2, [r1, #0x8c0] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x24444040 + str r2, [r0, #0x008] + + ldr r2, =0x555A7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF320F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005A1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x14420000 + str r2, [r0, #0x400] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x00400C58 + str r2, [r0, #0x890] + + ldr r3, =0x00bb0000 + ldr r2, =0x00000000 + str r2, [r3, #0x008] + ldr r2, =0x2891E41A + str r2, [r3, #0x00C] + ldr r2, =0x00000564 + str r2, [r3, #0x038] + ldr r2, =0x00000040 + str r2, [r3, #0x014] + ldr r2, =0x00000020 + str r2, [r3, #0x028] + ldr r2, =0x00000020 + str r2, [r3, #0x02c] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x43270338 + str r2, [r0, #0x83c] + ldr r2, =0x03200314 + str r2, [r0, #0x840] + + ldr r2, =0x431A032F + str r2, [r1, #0x83c] + ldr r2, =0x03200263 + str r2, [r1, #0x840] + + ldr r2, =0x4B434748 + str r2, [r0, #0x848] + ldr r2, =0x4445404C + str r2, [r1, #0x848] + + ldr r2, =0x38444542 + str r2, [r0, #0x850] + ldr r2, =0x4935493A + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + + ldr r2, =0x555A7975 + str r2, [r0, #0x00c] + ldr r2, =0xFF538F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005A1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001f001f + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x4220021F + str r2, [r0, #0x83c] + ldr r2, =0x0207017E + str r2, [r0, #0x840] + + ldr r2, =0x4201020C + str r2, [r1, #0x83c] + ldr r2, =0x01660172 + str r2, [r1, #0x840] + + ldr r2, =0x4A4D4E4D + str r2, [r0, #0x848] + ldr r2, =0x4A4F5049 + str r2, [r1, #0x848] + + ldr r2, =0x3F3C3D31 + str r2, [r0, #0x850] + ldr r2, =0x3238372B + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6solosabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x42190219 + str r2, [r0, #0x83c] + ldr r2, =0x017B0177 + str r2, [r0, #0x840] + + ldr r2, =0x4B4D4E4D + str r2, [r0, #0x848] + + ldr r2, =0x3F3E2D36 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000017 + str r2, [r0, #0x040] + + ldr r2, =0x83190000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00C03F3F + str r1, [r0, #0x068] + ldr r1, =0x0030FC03 + str r1, [r0, #0x06c] + ldr r1, =0x0FFFC000 + str r1, [r0, #0x070] + ldr r1, =0x3FF00000 + str r1, [r0, #0x074] + ldr r1, =0x00FFF300 + str r1, [r0, #0x078] + ldr r1, =0x0F0000C3 + str r1, [r0, #0x07c] + ldr r1, =0x000003FF + str r1, [r0, #0x080] +.endm + +.macro imx6_qos_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + +#if defined(CONFIG_MX6QP) + ldr r1, =0x77177717 + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#else + ldr r1, =0x007F007F + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#endif +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6S) + imx6solosabresd_ddr_setting +#elif defined (CONFIG_MX6DL) + imx6dlsabresd_ddr_setting +#elif defined (CONFIG_MX6QP) + imx6dqpsabresd_ddr_setting +#elif defined (CONFIG_MX6Q) + imx6dqsabresd_ddr_setting +#else + #error "SOC not configured" +#endif + +.endm + +/* include the common plugin code here */ +#include diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index d976e77..84ade59 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreSD board. * @@ -14,7 +15,7 @@ #define CONFIG_IMX_THERMAL /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) #define CONFIG_MXC_UART @@ -25,18 +26,43 @@ #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else #define CONFIG_ETHPRIME "FEC" +#endif #define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS -#ifdef CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 20000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#ifdef CONFIG_MX6S +#define SYS_NOSMP "nosmp" +#else +#define SYS_NOSMP #endif +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=" CONSOLE_DEV ",115200 " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "enable_wait_mode=off "\ + MFG_NAND_PARTITION \ + "\0" \ + "initrd_addr=0x12C00000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + + #ifdef CONFIG_SUPPORT_EMMC_BOOT #define EMMC_ENV \ "emmcdev=2\0" \ @@ -59,7 +85,46 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#if defined(CONFIG_NAND_BOOT) + /* + * The dts also enables the WEIN NOR which is mtd0. + * So the partions' layout for NAND is: + * mtd1: 16M (uboot) + * mtd2: 16M (kernel) + * mtd3: 16M (dtb) + * mtd4: left (rootfs) + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#elif defined(CONFIG_SATA_BOOT) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "bootargs=console=" CONSOLE_DEV ",115200 \0"\ + "bootargs_sata=setenv bootargs ${bootargs} " \ + "root=/dev/sda1 rootwait rw \0" \ + "bootcmd_sata=run bootargs_sata; sata init; " \ + "sata read ${loadaddr} 0x800 0x4000; " \ + "sata read ${fdt_addr} 0x8000 0x800; " \ + "bootz ${loadaddr} - ${fdt_addr} \0" \ + "bootcmd=run bootcmd_sata \0" + +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ "fdt_file=undefined\0" \ @@ -76,6 +141,8 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "update_sd_firmware=" \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ @@ -90,8 +157,9 @@ "fi; " \ "fi\0" \ EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "smp=" SYS_NOSMP "\0"\ + "mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \ + "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ @@ -99,7 +167,6 @@ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ @@ -114,7 +181,7 @@ "else " \ "bootz; " \ "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ + "netargs=setenv bootargs console=${console},${baudrate} ${smp} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ @@ -169,6 +236,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif #define CONFIG_ARP_TIMEOUT 200UL @@ -192,8 +260,96 @@ /* Environment organization */ #define CONFIG_ENV_SIZE (8 * 1024) +#ifdef CONFIG_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif + +#ifdef CONFIG_CMD_NAND +/* NAND flash command */ +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + #if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_OFFSET (896 * 1024) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#elif defined(CONFIG_ENV_IS_IN_SATA) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_SYS_SATA_ENV_DEV 0 +#define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */ +#endif + +/* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* Framebuffer */ @@ -207,6 +363,10 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6sabreandroid_common.h" +#else #define CONFIG_USBD_HS +#endif /* CONFIG_ANDROID_SUPPORT */ #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index bba15a7..a2fc6aa 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreAuto board. * @@ -16,17 +17,47 @@ #define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) +#ifdef CONFIG_MX6S +#undef PHYS_SDRAM_SIZE +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#endif + +#include "mx6sabre_common.h" +#undef MFG_NAND_PARTITION +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=8000000.nor:1m(boot),-(rootfs)\\\\;gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_CS 1 +#endif + +/*Since the pin conflicts on EIM D18, disable the USB host if the NOR flash is enabled */ +#ifdef CONFIG_USB /* USB Configs */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#if !defined(CONFIG_DM_PCA953X) && defined(CONFIG_SYS_I2C) #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } - -#include "mx6sabre_common.h" +#endif +#endif /* Falcon Mode */ #ifdef CONFIG_SPL_OS_BOOT @@ -40,43 +71,4 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ #endif -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 8c06512..f51f08e 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreSD board. * @@ -16,8 +17,15 @@ #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#if defined(CONFIG_MX6Q) +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#elif defined(CONFIG_MX6DL) +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#elif defined(CONFIG_MX6S) +#define PHYS_SDRAM_SIZE (512u * 1024 * 1024) +#endif #include "mx6sabre_common.h" @@ -34,8 +42,26 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ +#ifndef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#endif +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_CS 0 #endif +/* + * imx6 q/dl/solo pcie would be failed to work properly in kernel, if + * the pcie module is iniialized/enumerated both in uboot and linux + * kernel. + * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. + * it is only be RESET by the POR. So, the pcie module only be + * initialized/enumerated once in one POR. + * Set to use pcie in kernel defaultly, mask the pcie config here. + * Remove the mask freely, if the uboot pcie functions, rather than + * the kernel's, are required. + */ #ifdef CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX @@ -43,26 +69,33 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif +/*#define CONFIG_SPLASH_SCREEN*/ +/*#define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) + /* + * Framebuffer and LCD + */ + #define CONFIG_CMD_BMP + #undef LCD_TEST_PATTERN + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_WAVEFORM_BUF_SIZE 0x200000 +#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */ + #endif /* __MX6SABRESD_CONFIG_H */