From 3afecc120b3079e26ce9afb1edf94f9db819802f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 12 Jun 2018 16:07:24 +0800 Subject: [PATCH] MLK-18577-5 imx8: update soc code to support uboot in XEN VM Update SOC code to support U-Boot in a XEN VM. Currently we only support to boot android using uboot in a VM, so there is hardcode that using MMC1_BOOT boot. There are a few small fixes included. For the mmu configuration, the mem map is used from xen guest VM and our iomem space in vm cfg file. Signed-off-by: Peng Fan (cherry picked from commit 533087bc1bce0c35fead0956b0613971862c280f) (cherry picked from commit c2ba2460d8985aa0b084f7beef2d0bc8773d90e3) (cherry picked from commit 2b0a537f59646f3f222d60ebe46611160ba6bdc9) (cherry picked from commit 179a0a6ff3eba16fcf8d5966904b810531fe8665) --- arch/arm/mach-imx/imx8/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 5448aa6..202fd13 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -91,6 +91,9 @@ int arch_cpu_init_dm(void) return ret; } + if (IS_ENABLED(CONFIG_XEN)) + return 0; + struct pass_over_info_t *pass_over; if ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A)) { @@ -388,6 +391,10 @@ enum boot_device get_boot_device(void) sc_rsrc_t dev_rsrc; + /* Note we only support android in EMMC SDHC0 */ + if (IS_ENABLED(CONFIG_XEN)) + return MMC1_BOOT; + sc_misc_get_boot_dev(-1, &dev_rsrc); switch (dev_rsrc) { @@ -537,8 +544,10 @@ phys_size_t get_effective_memsize(void) sc_faddr_t start, end, end1, start_aligned; int err; - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + if (IS_ENABLED(CONFIG_XEN)) + return PHYS_SDRAM_1_SIZE; + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -569,6 +578,13 @@ int dram_init(void) sc_faddr_t start, end, end1, end2; int err; + if (IS_ENABLED(CONFIG_XEN)) { + gd->ram_size = PHYS_SDRAM_1_SIZE; + gd->ram_size += PHYS_SDRAM_2_SIZE; + + return 0; + } + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; for (mr = 0; mr < 64; mr++) { @@ -631,9 +647,17 @@ int dram_init_banksize(void) int i = 0; int err; + if (IS_ENABLED(CONFIG_XEN)) { + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + + return 0; + } + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; - for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -726,6 +750,29 @@ void enable_caches(void) sc_faddr_t start, end; int err, i; + if (IS_ENABLED(CONFIG_XEN)) { + imx8_mem_map[0].virt = 0x00000000UL; + imx8_mem_map[0].phys = 0x00000000UL; + imx8_mem_map[0].size = 0x40000000UL; + imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + imx8_mem_map[1].virt = 0x40000000UL; + imx8_mem_map[1].phys = 0x40000000UL; + imx8_mem_map[1].size = 0xC0000000UL; + imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); + + imx8_mem_map[2].virt = 0x100000000UL; + imx8_mem_map[2].phys = 0x100000000UL; + imx8_mem_map[2].size = 0x100000000UL; + imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + icache_enable(); + dcache_enable(); + + return; + } + /* Create map for registers access from 0x1c000000 to 0x80000000*/ imx8_mem_map[0].virt = 0x1c000000UL; imx8_mem_map[0].phys = 0x1c000000UL; -- 1.9.1