Eric Lee / smarc-uboot

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Commit 40419231e2bcba5892cb48fc9b55c42f8edf5017

Authored by Breno Lima
Committed by Ye Li
1 parent 63602a7cd5
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22755 mx7ulp: wdog: Wait for WDOG unlock and reconfiguration to complete 

According to i.MX7ULP Reference Manual we should wait for WDOG unlock
and reconfiguration to complete.

Section "59.5.3 Configure Watchdog" provides the following example:

DisableInterrupts; //disable global interrupt
WDOG_CNT = 0xD928C520; //unlock watchdog
while(WDOG_CS[ULK]==0); //wait until registers are unlocked
WDOG_TOVAL = 256; //set timeout value
WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |
	  WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1);
while(WDOG_CS[RCS]==0); //wait until new configuration takes effect
EnableInterrupts; //enable global interrupt

Update U-Boot WDOG driver to align with i.MX7ULP reference manual.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
(cherry picked from commit 3ffee301cb4570e0e7681448ec434f0689bcbaa3)

Showing 1 changed file with 14 additions and 0 deletions Side-by-side Diff

drivers/watchdog/ulp_wdog.c
Diff comments   View file @ 4041923
... ... @@ -32,6 +32,8 @@
32 32 #define WDGCS1_WDGE (1<<7)
33 33 #define WDGCS1_WDGUPDATE (1<<5)
34 34  
  35 +#define WDGCS2_RCS (1<<2)
  36 +#define WDGCS2_ULK (1<<3)
35 37 #define WDGCS2_FLG (1<<6)
36 38  
37 39 #define WDG_BUS_CLK (0x0)
... ... @@ -67,6 +69,9 @@
67 69 __raw_writel(UNLOCK_WORD1, &wdog->cnt);
68 70 dmb();
69 71  
  72 + /* Wait WDOG Unlock */
  73 + while (!(readl(&wdog->cs2) & WDGCS2_ULK));
  74 +
70 75 val = readb(&wdog->cs2);
71 76 val |= WDGCS2_FLG;
72 77 writeb(val, &wdog->cs2);
... ... @@ -77,6 +82,9 @@
77 82 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
78 83 writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
79 84  
  85 + /* Wait WDOG reconfiguration */
  86 + while (!(readl(&wdog->cs2) & WDGCS2_RCS));
  87 +
80 88 hw_watchdog_reset();
81 89 }
82 90  
83 91  
... ... @@ -89,11 +97,17 @@
89 97 __raw_writel(UNLOCK_WORD1, &wdog->cnt);
90 98 dmb();
91 99  
  100 + /* Wait WDOG Unlock */
  101 + while (!(readl(&wdog->cs2) & WDGCS2_ULK));
  102 +
92 103 hw_watchdog_set_timeout(5); /* 5ms timeout */
93 104 writel(0, &wdog->win);
94 105  
95 106 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
96 107 writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
  108 +
  109 + /* Wait WDOG reconfiguration */
  110 + while (!(readl(&wdog->cs2) & WDGCS2_RCS));
97 111  
98 112 hw_watchdog_reset();
99 113