From 40419231e2bcba5892cb48fc9b55c42f8edf5017 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Sun, 13 Oct 2019 21:35:53 -0300 Subject: [PATCH] MLK-22755 mx7ulp: wdog: Wait for WDOG unlock and reconfiguration to complete According to i.MX7ULP Reference Manual we should wait for WDOG unlock and reconfiguration to complete. Section "59.5.3 Configure Watchdog" provides the following example: DisableInterrupts; //disable global interrupt WDOG_CNT = 0xD928C520; //unlock watchdog while(WDOG_CS[ULK]==0); //wait until registers are unlocked WDOG_TOVAL = 256; //set timeout value WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) | WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1); while(WDOG_CS[RCS]==0); //wait until new configuration takes effect EnableInterrupts; //enable global interrupt Update U-Boot WDOG driver to align with i.MX7ULP reference manual. Reviewed-by: Ye Li Signed-off-by: Breno Lima (cherry picked from commit 3ffee301cb4570e0e7681448ec434f0689bcbaa3) --- drivers/watchdog/ulp_wdog.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 0cc06c1..e6faae2 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -32,6 +32,8 @@ struct wdog_regs { #define WDGCS1_WDGE (1<<7) #define WDGCS1_WDGUPDATE (1<<5) +#define WDGCS2_RCS (1<<2) +#define WDGCS2_ULK (1<<3) #define WDGCS2_FLG (1<<6) #define WDG_BUS_CLK (0x0) @@ -67,6 +69,9 @@ void hw_watchdog_init(void) __raw_writel(UNLOCK_WORD1, &wdog->cnt); dmb(); + /* Wait WDOG Unlock */ + while (!(readl(&wdog->cs2) & WDGCS2_ULK)); + val = readb(&wdog->cs2); val |= WDGCS2_FLG; writeb(val, &wdog->cs2); @@ -77,6 +82,9 @@ void hw_watchdog_init(void) writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ + /* Wait WDOG reconfiguration */ + while (!(readl(&wdog->cs2) & WDGCS2_RCS)); + hw_watchdog_reset(); } @@ -89,12 +97,18 @@ void reset_cpu(ulong addr) __raw_writel(UNLOCK_WORD1, &wdog->cnt); dmb(); + /* Wait WDOG Unlock */ + while (!(readl(&wdog->cs2) & WDGCS2_ULK)); + hw_watchdog_set_timeout(5); /* 5ms timeout */ writel(0, &wdog->win); writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ + /* Wait WDOG reconfiguration */ + while (!(readl(&wdog->cs2) & WDGCS2_RCS)); + hw_watchdog_reset(); while (1); -- 1.9.1