Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 464f93e0be8347f80f519c75bfe1b4dece47a8d6

Authored by Eric Lee
1 parent a25b51e561
Exists in smarc-imx_v2015.04_4.1.15_1.0.0_ga

Add solo core 1G DDR3L configuration

Showing 5 changed files with 223 additions and 0 deletions Side-by-side Diff

board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg
Diff comments   View file @ 464f93e
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Jason Liu <r64343@freescale.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Refer docs/README.imxmage for more details about how-to configure
  8 + * and create imximage boot image
  9 + *
  10 + * The syntax is taken as close as possible with the kwbimage
  11 + */
  12 +
  13 +#define __ASSEMBLY__
  14 +#include <config.h>
  15 +
  16 +/* image version */
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of spi, sd, sata
  21 + * the board has no nand and eimnor
  22 + * spinor: flash_offset: 0x0400
  23 + * sata: flash_offset: 0x0400
  24 + * sd/mmc: flash_offset: 0x0400
  25 + */
  26 +
  27 +/* the same flash_offset as sd */
  28 +BOOT_FROM spi
  29 +
  30 +#ifdef CONFIG_USE_PLUGIN
  31 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  32 +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000
  33 +#else
  34 +
  35 +#ifdef CONFIG_SECURE_BOOT
  36 +CSF 0x2000
  37 +#endif
  38 +
  39 +/*
  40 + * Device Configuration Data (DCD)
  41 + *
  42 + * Each entry must have the format:
  43 + * Addr-type Address Value
  44 + *
  45 + * where:
  46 + * Addr-type register length (1,2 or 4 bytes)
  47 + * Address absolute address of the register
  48 + * value value to be stored in the register
  49 + */
  50 +/* Enable all clocks */
  51 +/*DATA 4 0x020c4068 0xffffffff
  52 +DATA 4 0x020c406c 0xffffffff
  53 +DATA 4 0x020c4070 0xffffffff
  54 +DATA 4 0x020c4074 0xffffffff
  55 +DATA 4 0x020c4078 0xffffffff
  56 +DATA 4 0x020c407c 0xffffffff
  57 +DATA 4 0x020c4080 0xffffffff
  58 +DATA 4 0x020c4084 0xffffffff*/
  59 +
  60 +/* IOMUX */
  61 +/* DDR IO TYPE */
  62 +DATA 4 0x020e0774 0x000C0000
  63 +DATA 4 0x020e0754 0x00000000
  64 +
  65 +/* CLOCK */
  66 +DATA 4 0x020e04ac 0x00000030
  67 +DATA 4 0x020e04b0 0x00000030
  68 +
  69 +/* ADDRESS */
  70 +DATA 4 0x020e0464 0x00000030
  71 +DATA 4 0x020e0490 0x00000030
  72 +DATA 4 0x020e074c 0x00000030
  73 +
  74 +/* CONTROL */
  75 +DATA 4 0x020e0494 0x00000030
  76 +DATA 4 0x020e04a0 0x00000000
  77 +DATA 4 0x020e04b4 0x00000030
  78 +DATA 4 0x020e04b8 0x00000030
  79 +DATA 4 0x020e076c 0x00000030
  80 +
  81 +/* DATA STROBE */
  82 +DATA 4 0x020e0750 0x00020000
  83 +DATA 4 0x020e04bc 0x00000028
  84 +DATA 4 0x020e04c0 0x00000028
  85 +DATA 4 0x020e04c4 0x00000028
  86 +DATA 4 0x020e04c8 0x00000028
  87 +DATA 4 0x020e04cc 0x00000028
  88 +DATA 4 0x020e04d0 0x00000028
  89 +DATA 4 0x020e04d4 0x00000028
  90 +DATA 4 0x020e04d8 0x00000028
  91 +
  92 +/* DATA */
  93 +DATA 4 0x020e0760 0x00020000
  94 +DATA 4 0x020e0764 0x00000028
  95 +DATA 4 0x020e0770 0x00000028
  96 +DATA 4 0x020e0778 0x00000028
  97 +DATA 4 0x020e077c 0x00000028
  98 +DATA 4 0x020e0780 0x00000028
  99 +DATA 4 0x020e0784 0x00000028
  100 +DATA 4 0x020e078c 0x00000028
  101 +DATA 4 0x020e0748 0x00000028
  102 +DATA 4 0x020e0470 0x00000028
  103 +DATA 4 0x020e0474 0x00000028
  104 +DATA 4 0x020e0478 0x00000028
  105 +DATA 4 0x020e047c 0x00000028
  106 +DATA 4 0x020e0480 0x00000028
  107 +DATA 4 0x020e0484 0x00000028
  108 +DATA 4 0x020e0488 0x00000028
  109 +DATA 4 0x020e048c 0x00000028
  110 +
  111 +/* Calibrations */
  112 +/* ZQ */
  113 +DATA 4 0x021b0800 0xa1390003
  114 +/* write leveling */
  115 +DATA 4 0x021b080c 0x004D004D
  116 +DATA 4 0x021b0810 0x00420046
  117 +DATA 4 0x021b480c 0x001F001F
  118 +DATA 4 0x021b4810 0x001F001F
  119 +
  120 +/* DQS Read Gate */
  121 +DATA 4 0x021b083c 0x424C0254
  122 +DATA 4 0x021b0840 0x02340234
  123 +DATA 4 0x021b483c 0x42640264
  124 +DATA 4 0x021b4840 0x02400250
  125 +
  126 +/* Read/Write Delay */
  127 +DATA 4 0x021b0848 0x48484A4A
  128 +DATA 4 0x021b4848 0x44484A4C
  129 +
  130 +DATA 4 0x021b0850 0x36343032
  131 +DATA 4 0x021b4850 0x3C383434
  132 +
  133 +/* read data bit delay */
  134 +DATA 4 0x021b081c 0x33333333
  135 +DATA 4 0x021b0820 0x33333333
  136 +DATA 4 0x021b0824 0x33333333
  137 +DATA 4 0x021b0828 0x33333333
  138 +DATA 4 0x021b481c 0x33333333
  139 +DATA 4 0x021b4820 0x33333333
  140 +DATA 4 0x021b4824 0x33333333
  141 +DATA 4 0x021b4828 0x33333333
  142 +
  143 +/* Complete calibration by forced measurment */
  144 +DATA 4 0x021b08b8 0x00000800
  145 +DATA 4 0x021b48b8 0x00000800
  146 +
  147 +/* MMDC init */
  148 +DATA 4 0x021b0004 0x00020025
  149 +DATA 4 0x021b0008 0x00333030
  150 +DATA 4 0x021b000c 0x676B5313
  151 +DATA 4 0x021b0010 0xB66E8B63
  152 +DATA 4 0x021b0014 0x01FF00DB
  153 +DATA 4 0x021b0018 0x00001740
  154 +DATA 4 0x021b001c 0x00008000
  155 +DATA 4 0x021b002c 0x000026d2
  156 +DATA 4 0x021b0030 0x006B1023
  157 +DATA 4 0x021b0040 0x00000027
  158 +DATA 4 0x021b0000 0x84190000
  159 +
  160 +/* Initialize CS0: K4B2G1646Q-BCK0 */
  161 +/* MR2 */
  162 +DATA 4 0x021b001c 0x04008032
  163 +/* MR3 */
  164 +DATA 4 0x021b001c 0x00008033
  165 +/* MR1 */
  166 +DATA 4 0x021b001c 0x00048031
  167 +/* MR0 */
  168 +DATA 4 0x021b001c 0x05208030
  169 +/* DDR device ZQ calibration */
  170 +DATA 4 0x021b001c 0x04008040
  171 +/*MDREF*/
  172 +DATA 4 0x021b0020 0x00005800
  173 +
  174 +/* final DDR setup, before operation start */
  175 +DATA 4 0x021b0818 0x00011117
  176 +/*DATA 4 0x021b4818 0x00011117*/
  177 +DATA 4 0x021b0004 0x00025565
  178 +DATA 4 0x021b0404 0x00011006
  179 +DATA 4 0x021b001c 0x00000000
  180 +
  181 +/* set the default clock gate to save power */
  182 +DATA 4 0x020c4068 0x00C03F3F
  183 +DATA 4 0x020c406c 0x0030FC03
  184 +DATA 4 0x020c4070 0x0FFFC000
  185 +DATA 4 0x020c4074 0x3FF00000
  186 +DATA 4 0x020c4078 0x00FFF300
  187 +DATA 4 0x020c407c 0x0F0000C3
  188 +DATA 4 0x020c4080 0x000003FF
  189 +
  190 +/* enable AXI cache for VDOA/VPU/IPU */
  191 +DATA 4 0x020e0010 0xF00000CF
  192 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  193 +DATA 4 0x020e0018 0x007F007F
  194 +DATA 4 0x020e001c 0x007F007F
  195 +#endif
configs/smarcfimx6_solo_1g_ser0_defconfig
Diff comments   View file @ 464f93e
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER0,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\""
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_SMARCFIMX6=y
  4 +CONFIG_SYS_MALLOC_F=y
  5 +CONFIG_SYS_MALLOC_F_LEN=0x400
  6 +CONFIG_DM=y
  7 +CONFIG_DM_THERMAL=y
configs/smarcfimx6_solo_1g_ser1_defconfig
Diff comments   View file @ 464f93e
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER1,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\""
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_SMARCFIMX6=y
  4 +CONFIG_SYS_MALLOC_F=y
  5 +CONFIG_SYS_MALLOC_F_LEN=0x400
  6 +CONFIG_DM=y
  7 +CONFIG_DM_THERMAL=y
configs/smarcfimx6_solo_1g_ser2_defconfig
Diff comments   View file @ 464f93e
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER2,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\""
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_SMARCFIMX6=y
  4 +CONFIG_SYS_MALLOC_F=y
  5 +CONFIG_SYS_MALLOC_F_LEN=0x400
  6 +CONFIG_DM=y
  7 +CONFIG_DM_THERMAL=y
configs/smarcfimx6_solo_1g_ser3_defconfig
Diff comments   View file @ 464f93e
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER3,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\""
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_SMARCFIMX6=y
  4 +CONFIG_SYS_MALLOC_F=y
  5 +CONFIG_SYS_MALLOC_F_LEN=0x400
  6 +CONFIG_DM=y
  7 +CONFIG_DM_THERMAL=y