diff --git a/board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg b/board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg new file mode 100644 index 0000000..d2a345a --- /dev/null +++ b/board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, sata + * the board has no nand and eimnor + * spinor: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + */ + +/* the same flash_offset as sd */ +BOOT_FROM spi + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF 0x2000 +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +/* Enable all clocks */ +/*DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff*/ + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 + +/* CLOCK */ +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 + +/* ADDRESS */ +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 + +/* CONTROL */ +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 + +/* DATA STROBE */ +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000028 +DATA 4 0x020e04c0 0x00000028 +DATA 4 0x020e04c4 0x00000028 +DATA 4 0x020e04c8 0x00000028 +DATA 4 0x020e04cc 0x00000028 +DATA 4 0x020e04d0 0x00000028 +DATA 4 0x020e04d4 0x00000028 +DATA 4 0x020e04d8 0x00000028 + +/* DATA */ +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000028 +DATA 4 0x020e0770 0x00000028 +DATA 4 0x020e0778 0x00000028 +DATA 4 0x020e077c 0x00000028 +DATA 4 0x020e0780 0x00000028 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e078c 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e0470 0x00000028 +DATA 4 0x020e0474 0x00000028 +DATA 4 0x020e0478 0x00000028 +DATA 4 0x020e047c 0x00000028 +DATA 4 0x020e0480 0x00000028 +DATA 4 0x020e0484 0x00000028 +DATA 4 0x020e0488 0x00000028 +DATA 4 0x020e048c 0x00000028 + +/* Calibrations */ +/* ZQ */ +DATA 4 0x021b0800 0xa1390003 +/* write leveling */ +DATA 4 0x021b080c 0x004D004D +DATA 4 0x021b0810 0x00420046 +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x424C0254 +DATA 4 0x021b0840 0x02340234 +DATA 4 0x021b483c 0x42640264 +DATA 4 0x021b4840 0x02400250 + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x48484A4A +DATA 4 0x021b4848 0x44484A4C + +DATA 4 0x021b0850 0x36343032 +DATA 4 0x021b4850 0x3C383434 + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +/* MMDC init */ +DATA 4 0x021b0004 0x00020025 +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676B5313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006B1023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x84190000 + +/* Initialize CS0: K4B2G1646Q-BCK0 */ +/* MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 +/*MDREF*/ +DATA 4 0x021b0020 0x00005800 + +/* final DDR setup, before operation start */ +DATA 4 0x021b0818 0x00011117 +/*DATA 4 0x021b4818 0x00011117*/ +DATA 4 0x021b0004 0x00025565 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/configs/smarcfimx6_solo_1g_ser0_defconfig b/configs/smarcfimx6_solo_1g_ser0_defconfig new file mode 100644 index 0000000..41a11b7 --- /dev/null +++ b/configs/smarcfimx6_solo_1g_ser0_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER0,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\"" +CONFIG_ARM=y +CONFIG_TARGET_SMARCFIMX6=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/smarcfimx6_solo_1g_ser1_defconfig b/configs/smarcfimx6_solo_1g_ser1_defconfig new file mode 100644 index 0000000..30651c5 --- /dev/null +++ b/configs/smarcfimx6_solo_1g_ser1_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER1,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\"" +CONFIG_ARM=y +CONFIG_TARGET_SMARCFIMX6=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/smarcfimx6_solo_1g_ser2_defconfig b/configs/smarcfimx6_solo_1g_ser2_defconfig new file mode 100644 index 0000000..439dc9a --- /dev/null +++ b/configs/smarcfimx6_solo_1g_ser2_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER2,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\"" +CONFIG_ARM=y +CONFIG_TARGET_SMARCFIMX6=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/smarcfimx6_solo_1g_ser3_defconfig b/configs/smarcfimx6_solo_1g_ser3_defconfig new file mode 100644 index 0000000..398bf87 --- /dev/null +++ b/configs/smarcfimx6_solo_1g_ser3_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b4g1646q.cfg,MX6SOLO,SER3,SYS_USE_SPINOR,SYS_NOSMP=\"nosmp\"" +CONFIG_ARM=y +CONFIG_TARGET_SMARCFIMX6=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y