Eric Lee / smarc-uboot

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Commit 47096e5310d76672df4b8222b60c4c158b019edc

Authored by Ye Li
1 parent 9d6623f13f
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-21158 imx8mm: Add workaround for arm timer stopped issue 

When switching ARM root clock source from ARM PLL to 24M OSC,
found the ARM timer may stop on few chips during stress reboot test.
The system counter is still increasing, but ARM timer is stopped.

Add a workaround that switch ARM clock source from ARM PLL to
Sys PLL2 500M clock instead of 24M OSC. Stress reboot test is
passed on all failed chips.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 74770228976c013a3e289b21f6e27334ea97bee4)

Showing 1 changed file with 10 additions and 10 deletions Side-by-side Diff

arch/arm/mach-imx/imx8m/clock_imx8mm.c
Diff comments   View file @ 47096e5
... ... @@ -612,16 +612,6 @@
612 612 {
613 613 uint32_t val_cfg0;
614 614  
615   - /* Configure ARM at 1GHz */
616   - clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
617   - CLK_ROOT_SOURCE_SEL(0));
618   -
619   - intpll_configure(ANATOP_ARM_PLL, INTPLL_OUT_1200M);
620   -
621   - clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
622   - CLK_ROOT_SOURCE_SEL(1) | \
623   - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
624   -
625 615 /*
626 616 * According to ANAMIX SPEC
627 617 * sys pll1 fixed at 800MHz
... ... @@ -643,6 +633,16 @@
643 633 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
644 634 INTPLL_DIV20_CLKE_MASK;
645 635 writel(val_cfg0, SYS_PLL2_GNRL_CTL);
  636 +
  637 + /* Configure ARM at 1.2GHz */
  638 + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
  639 + CLK_ROOT_SOURCE_SEL(2));
  640 +
  641 + intpll_configure(ANATOP_ARM_PLL, INTPLL_OUT_1200M);
  642 +
  643 + clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
  644 + CLK_ROOT_SOURCE_SEL(1) | \
  645 + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
646 646  
647 647 intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_750M);
648 648 clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));