Commit 4dfff1b1666b8b1d589b2aebb356cc61bd335c62
1 parent
0044258713
Make changes for hw revision 00D0 of SMARC-iMX8M
Showing 2 changed files with 15 additions and 8 deletions Side-by-side Diff
arch/arm/dts/fsl-smarcimx8mq.dts
| ... | ... | @@ -152,8 +152,8 @@ |
| 152 | 152 | fsl,pins = < |
| 153 | 153 | MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79 |
| 154 | 154 | MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79 |
| 155 | - MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */ | |
| 156 | - MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */ | |
| 155 | + MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x79 /* RTS */ | |
| 156 | + MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x79 /* CTS */ | |
| 157 | 157 | |
| 158 | 158 | >; |
| 159 | 159 | }; |
| ... | ... | @@ -167,8 +167,10 @@ |
| 167 | 167 | |
| 168 | 168 | pinctrl_uart4: uart4grp { |
| 169 | 169 | fsl,pins = < |
| 170 | - MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79 | |
| 171 | - MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79 | |
| 170 | + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x79 | |
| 171 | + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x79 | |
| 172 | + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x79 /* RTS */ | |
| 173 | + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x79 /* CTS */ | |
| 172 | 174 | >; |
| 173 | 175 | }; |
| 174 | 176 | |
| ... | ... | @@ -239,6 +241,7 @@ |
| 239 | 241 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 |
| 240 | 242 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 |
| 241 | 243 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 |
| 244 | + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 | |
| 242 | 245 | >; |
| 243 | 246 | }; |
| 244 | 247 | |
| ... | ... | @@ -250,6 +253,7 @@ |
| 250 | 253 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd |
| 251 | 254 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd |
| 252 | 255 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd |
| 256 | + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 | |
| 253 | 257 | >; |
| 254 | 258 | }; |
| 255 | 259 | |
| ... | ... | @@ -261,6 +265,7 @@ |
| 261 | 265 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf |
| 262 | 266 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf |
| 263 | 267 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf |
| 268 | + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 | |
| 264 | 269 | >; |
| 265 | 270 | }; |
| 266 | 271 | |
| ... | ... | @@ -393,7 +398,6 @@ |
| 393 | 398 | vgen6_reg: vgen6 { |
| 394 | 399 | regulator-min-microvolt = <1800000>; |
| 395 | 400 | regulator-max-microvolt = <3300000>; |
| 396 | - regulator-always-on; | |
| 397 | 401 | }; |
| 398 | 402 | }; |
| 399 | 403 | }; |
| ... | ... | @@ -584,7 +588,7 @@ |
| 584 | 588 | pinctrl-names = "default"; |
| 585 | 589 | pinctrl-0 = <&pinctrl_uart3>; |
| 586 | 590 | assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; |
| 587 | - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; | |
| 591 | + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; | |
| 588 | 592 | status = "okay"; |
| 589 | 593 | }; |
| 590 | 594 |
board/embedian/smarcimx8mq/smarcimx8mq.c
| ... | ... | @@ -80,6 +80,9 @@ |
| 80 | 80 | static iomux_v3_cfg_t const uart2_pads[] = { |
| 81 | 81 | IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 82 | 82 | IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 83 | + IMX8MQ_PAD_UART4_TXD__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 84 | + IMX8MQ_PAD_UART4_RXD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 85 | + | |
| 83 | 86 | }; |
| 84 | 87 | #endif |
| 85 | 88 | |
| 86 | 89 | |
| ... | ... | @@ -92,10 +95,10 @@ |
| 92 | 95 | |
| 93 | 96 | #ifdef CONFIG_CONSOLE_SER0 |
| 94 | 97 | static iomux_v3_cfg_t const uart4_pads[] = { |
| 95 | - IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 98 | + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 96 | 99 | IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 97 | 100 | IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 98 | - IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 101 | + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 99 | 102 | }; |
| 100 | 103 | #endif |
| 101 | 104 |