diff --git a/arch/arm/dts/fsl-smarcimx8mq.dts b/arch/arm/dts/fsl-smarcimx8mq.dts
index bbf92e6..ba80d22 100644
--- a/arch/arm/dts/fsl-smarcimx8mq.dts
+++ b/arch/arm/dts/fsl-smarcimx8mq.dts
@@ -152,8 +152,8 @@
                         fsl,pins = <
                                 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x79
                                 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x79
-                                MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11             0x19    /* RTS */
-                                MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10             0x19    /* CTS */
+                                MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B         	0x79    /* RTS */
+                                MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B        	0x79    /* CTS */
 
                         >;
                 };
@@ -167,8 +167,10 @@
 
                 pinctrl_uart4: uart4grp {
                         fsl,pins = <
-                                MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX             0x79
-                                MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX             0x79
+                               	MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX          	0x79
+                                MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX          	0x79
+                                MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B        	0x79    /* RTS */
+                                MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B       	0x79    /* CTS */
                         >;
                 };
 
@@ -239,6 +241,7 @@
 				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
 				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
 				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+                                MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 			>;
 		};
 
@@ -250,6 +253,7 @@
 				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
 				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
 				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
+                                MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 			>;
 		};
 
@@ -261,6 +265,7 @@
 				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
 				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
 				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
+                                MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 			>;
 		};
 
@@ -393,7 +398,6 @@
 			vgen6_reg: vgen6 {
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
 			};
 		};
 	};
@@ -584,7 +588,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3>;
 	assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
-	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
 	status = "okay";
 };
 
diff --git a/board/embedian/smarcimx8mq/smarcimx8mq.c b/board/embedian/smarcimx8mq/smarcimx8mq.c
index 9eedb2c..ddfadfe 100644
--- a/board/embedian/smarcimx8mq/smarcimx8mq.c
+++ b/board/embedian/smarcimx8mq/smarcimx8mq.c
@@ -80,6 +80,9 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 static iomux_v3_cfg_t const uart2_pads[] = {
         IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
         IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART4_TXD__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART4_RXD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+
 };
 #endif
 
@@ -92,10 +95,10 @@ static iomux_v3_cfg_t const uart3_pads[] = {
 
 #ifdef CONFIG_CONSOLE_SER0
 static iomux_v3_cfg_t const uart4_pads[] = {
-        IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
         IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
         IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-        IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 #endif