Eric Lee / smarc-uboot

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Commit 4e9acc16fc026ae0991b32e52c15c0e9a36a53a7

Authored by Michal Simek
1 parent ebd322de43
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

fpga: xilinx: spartan2: Setup NULL fpga_op without driver 

Set fpga operations to NULL for cases where
FPGA is setup in board file but driver is not added.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 1 changed file with 27 additions and 11 deletions Side-by-side Diff

... ... @@ -38,7 +38,12 @@
38 38 xilinx_post_fn post;
39 39 } xilinx_spartan2_slave_serial_fns;
40 40  
  41 +#if defined(CONFIG_FPGA_SPARTAN2)
41 42 extern struct xilinx_fpga_op spartan2_op;
  43 +# define FPGA_SPARTAN2_OPS &spartan2_op
  44 +#else
  45 +# define FPGA_SPARTAN2_OPS NULL
  46 +#endif
42 47  
43 48 /* Device Image Sizes
44 49 *********************************************************************/
45 50  
46 51  
47 52  
48 53  
49 54  
50 55  
51 56  
52 57  
53 58  
54 59  
... ... @@ -61,37 +66,48 @@
61 66 *********************************************************************/
62 67 /* Spartan-II devices */
63 68 #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
64   -{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
  69 +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
  70 + FPGA_SPARTAN2_OPS }
65 71  
66 72 #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
67   -{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
  73 +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
  74 + FPGA_SPARTAN2_OPS }
68 75  
69 76 #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
70   -{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
  77 +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
  78 + FPGA_SPARTAN2_OPS }
71 79  
72 80 #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
73   -{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
  81 +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
  82 + FPGA_SPARTAN2_OPS }
74 83  
75 84 #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
76   -{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
  85 +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
  86 + FPGA_SPARTAN2_OPS }
77 87  
78 88 #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
79   -{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
  89 +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
  90 + FPGA_SPARTAN2_OPS }
80 91  
81 92 #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
82   -{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
  93 +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
  94 + FPGA_SPARTAN2_OPS }
83 95  
84 96 #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
85   -{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
  97 +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
  98 + FPGA_SPARTAN2_OPS }
86 99  
87 100 #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
88   -{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
  101 +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
  102 + FPGA_SPARTAN2_OPS }
89 103  
90 104 #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
91   -{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
  105 +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
  106 + FPGA_SPARTAN2_OPS }
92 107  
93 108 #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
94   -{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
  109 +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
  110 + FPGA_SPARTAN2_OPS }
95 111  
96 112 #endif /* _SPARTAN2_H_ */