From 5187303fc8ae3f5e266e725c5b526381d2b77236 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Fri, 8 May 2020 10:54:49 -0500 Subject: [PATCH] MLK-23928: board: freescale: imx8mn audio board 2.0 Add support for imx8mn audio board 2.0 support reuse common settings from imx8mn evk som Rework for imx_v2020.04 defconfig, dts and SPL Reviewed-by: Ye Li Signed-off-by: Adrian Alonso --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx8mn-ab2-u-boot.dtsi | 127 ++ arch/arm/dts/imx8mn-ab2.dts | 497 ++++++++ arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi | 127 ++ arch/arm/dts/imx8mn-ddr4-ab2.dts | 477 +++++++ arch/arm/mach-imx/imx8m/Kconfig | 12 + board/freescale/imx8mm_ab2/Kconfig | 7 +- board/freescale/imx8mm_ab2/Makefile | 2 + board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c | 1057 ++++++++++++++++ board/freescale/imx8mm_ab2/imx8mm_ab2.c | 25 + board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c | 1585 ++++++++++++++++++++++++ board/freescale/imx8mm_ab2/spl.c | 95 +- configs/imx8mn_ab2_defconfig | 113 ++ configs/imx8mn_ddr4_ab2_defconfig | 113 ++ include/configs/imx8mn_ab2.h | 239 ++++ 15 files changed, 4469 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/imx8mn-ab2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-ab2.dts create mode 100644 arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-ddr4-ab2.dts create mode 100644 board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c create mode 100644 board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c create mode 100644 configs/imx8mn_ab2_defconfig create mode 100644 configs/imx8mn_ddr4_ab2_defconfig create mode 100644 include/configs/imx8mn_ab2.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8543421..000d031 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -789,7 +789,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-ddr4-val.dtb \ imx8mq-evk.dtb \ imx8mp-evk.dtb \ - imx8mm-ab2.dtb + imx8mm-ab2.dtb \ + imx8mn-ddr4-ab2.dtb \ + imx8mn-ab2.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb diff --git a/arch/arm/dts/imx8mn-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi new file mode 100644 index 0000000..d4c5e43 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&flexspi { + assigned-clock-rates = <100000000>; + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; +}; diff --git a/arch/arm/dts/imx8mn-ab2.dts b/arch/arm/dts/imx8mn-ab2.dts new file mode 100644 index 0000000..99aac03 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2.dts @@ -0,0 +1,497 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano LPDDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + u-boot,off-on-delay-us = <12000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8mn-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_uart2: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450b"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi new file mode 100644 index 0000000..d4c5e43 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&flexspi { + assigned-clock-rates = <100000000>; + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2.dts b/arch/arm/dts/imx8mn-ddr4-ab2.dts new file mode 100644 index 0000000..7ad77db --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2.dts @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mn.dtsi" + +/ { + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + u-boot,off-on-delay-us = <12000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8mn-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_uart2: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <150>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index cb06338..719769c 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -102,6 +102,18 @@ config TARGET_IMX8MM_AB2 select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_IMX8MN_AB2 + bool "imx8mn LPDDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MN_DDR4_AB2 + bool "imx8mn DDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR4 + config TARGET_VERDIN_IMX8MM bool "Support Toradex Verdin iMX8M Mini module" select IMX8MM diff --git a/board/freescale/imx8mm_ab2/Kconfig b/board/freescale/imx8mm_ab2/Kconfig index bc8945f..cf1c31d 100644 --- a/board/freescale/imx8mm_ab2/Kconfig +++ b/board/freescale/imx8mm_ab2/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MM_AB2 +if TARGET_IMX8MM_AB2 || TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2 config SYS_BOARD default "imx8mm_ab2" @@ -11,6 +11,11 @@ config SYS_CONFIG_NAME default "imx8mm_ab2" endif +if TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2 +config SYS_CONFIG_NAME + default "imx8mn_ab2" +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/imx8mm_ab2/Makefile b/board/freescale/imx8mm_ab2/Makefile index 854d1fd..668512d 100644 --- a/board/freescale/imx8mm_ab2/Makefile +++ b/board/freescale/imx8mm_ab2/Makefile @@ -9,4 +9,6 @@ obj-y += imx8mm_ab2.o ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-$(CONFIG_TARGET_IMX8MM_AB2) += lpddr4_imx8mm_som.o +obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som.o +obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som.o endif diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c new file mode 100644 index 0000000..84114a3 --- /dev/null +++ b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c @@ -0,0 +1,1057 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x92014a }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x810 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x7070d0c }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1809010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + + /* performance setting */ + { 0x3d400250, 0x00001f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x900003ff }, + { 0x3d40026c, 0x200003ff }, + { 0x3d400494, 0x01000e00 }, + { 0x3d400498, 0x03ff0000 }, + { 0x3d40049c, 0x01000e00 }, + { 0x3d4004a0, 0x03ff0000 }, + + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3848204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x404 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000600 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x010082, 0x0}, + {0x110082, 0x0}, + {0x210082, 0x0}, + {0x010182, 0x0}, + {0x110182, 0x0}, + {0x210182, 0x0}, + {0x010083, 0x0}, + {0x110083, 0x0}, + {0x210083, 0x0}, + {0x010183, 0x0}, + {0x110183, 0x0}, + {0x210183, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x011082, 0x0}, + {0x111082, 0x0}, + {0x211082, 0x0}, + {0x011182, 0x0}, + {0x111182, 0x0}, + {0x211182, 0x0}, + {0x011083, 0x0}, + {0x111083, 0x0}, + {0x211083, 0x0}, + {0x011183, 0x0}, + {0x111183, 0x0}, + {0x211183, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0100d2, 0x0}, + {0x1100d2, 0x0}, + {0x2100d2, 0x0}, + {0x0101d2, 0x0}, + {0x1101d2, 0x0}, + {0x2101d2, 0x0}, + {0x0100d3, 0x0}, + {0x1100d3, 0x0}, + {0x2100d3, 0x0}, + {0x0101d3, 0x0}, + {0x1101d3, 0x0}, + {0x2101d3, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x0110d2, 0x0}, + {0x1110d2, 0x0}, + {0x2110d2, 0x0}, + {0x0111d2, 0x0}, + {0x1111d2, 0x0}, + {0x2111d2, 0x0}, + {0x0110d3, 0x0}, + {0x1110d3, 0x0}, + {0x2110d3, 0x0}, + {0x0111d3, 0x0}, + {0x1111d3, 0x0}, + {0x2111d3, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x01006a, 0x0}, + {0x01016a, 0x0}, + {0x01026a, 0x0}, + {0x01036a, 0x0}, + {0x01046a, 0x0}, + {0x01056a, 0x0}, + {0x01066a, 0x0}, + {0x01076a, 0x0}, + {0x01086a, 0x0}, + {0x01006b, 0x0}, + {0x01016b, 0x0}, + {0x01026b, 0x0}, + {0x01036b, 0x0}, + {0x01046b, 0x0}, + {0x01056b, 0x0}, + {0x01066b, 0x0}, + {0x01076b, 0x0}, + {0x01086b, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01106a, 0x0}, + {0x01116a, 0x0}, + {0x01126a, 0x0}, + {0x01136a, 0x0}, + {0x01146a, 0x0}, + {0x01156a, 0x0}, + {0x01166a, 0x0}, + {0x01176a, 0x0}, + {0x01186a, 0x0}, + {0x01106b, 0x0}, + {0x01116b, 0x0}, + {0x01126b, 0x0}, + {0x01136b, 0x0}, + {0x01146b, 0x0}, + {0x01156b, 0x0}, + {0x01166b, 0x0}, + {0x01176b, 0x0}, + {0x01186b, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01008e, 0x0}, + {0x11008e, 0x0}, + {0x21008e, 0x0}, + {0x01018e, 0x0}, + {0x11018e, 0x0}, + {0x21018e, 0x0}, + {0x01008f, 0x0}, + {0x11008f, 0x0}, + {0x21008f, 0x0}, + {0x01018f, 0x0}, + {0x11018f, 0x0}, + {0x21018f, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x01108e, 0x0}, + {0x11108e, 0x0}, + {0x21108e, 0x0}, + {0x01118e, 0x0}, + {0x11118e, 0x0}, + {0x21118e, 0x0}, + {0x01108f, 0x0}, + {0x11108f, 0x0}, + {0x21108f, 0x0}, + {0x01118f, 0x0}, + {0x11118f, 0x0}, + {0x21118f, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0100c2, 0x0}, + {0x1100c2, 0x0}, + {0x2100c2, 0x0}, + {0x0101c2, 0x0}, + {0x1101c2, 0x0}, + {0x2101c2, 0x0}, + {0x0102c2, 0x0}, + {0x1102c2, 0x0}, + {0x2102c2, 0x0}, + {0x0103c2, 0x0}, + {0x1103c2, 0x0}, + {0x2103c2, 0x0}, + {0x0104c2, 0x0}, + {0x1104c2, 0x0}, + {0x2104c2, 0x0}, + {0x0105c2, 0x0}, + {0x1105c2, 0x0}, + {0x2105c2, 0x0}, + {0x0106c2, 0x0}, + {0x1106c2, 0x0}, + {0x2106c2, 0x0}, + {0x0107c2, 0x0}, + {0x1107c2, 0x0}, + {0x2107c2, 0x0}, + {0x0108c2, 0x0}, + {0x1108c2, 0x0}, + {0x2108c2, 0x0}, + {0x0100c3, 0x0}, + {0x1100c3, 0x0}, + {0x2100c3, 0x0}, + {0x0101c3, 0x0}, + {0x1101c3, 0x0}, + {0x2101c3, 0x0}, + {0x0102c3, 0x0}, + {0x1102c3, 0x0}, + {0x2102c3, 0x0}, + {0x0103c3, 0x0}, + {0x1103c3, 0x0}, + {0x2103c3, 0x0}, + {0x0104c3, 0x0}, + {0x1104c3, 0x0}, + {0x2104c3, 0x0}, + {0x0105c3, 0x0}, + {0x1105c3, 0x0}, + {0x2105c3, 0x0}, + {0x0106c3, 0x0}, + {0x1106c3, 0x0}, + {0x2106c3, 0x0}, + {0x0107c3, 0x0}, + {0x1107c3, 0x0}, + {0x2107c3, 0x0}, + {0x0108c3, 0x0}, + {0x1108c3, 0x0}, + {0x2108c3, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x0110c2, 0x0}, + {0x1110c2, 0x0}, + {0x2110c2, 0x0}, + {0x0111c2, 0x0}, + {0x1111c2, 0x0}, + {0x2111c2, 0x0}, + {0x0112c2, 0x0}, + {0x1112c2, 0x0}, + {0x2112c2, 0x0}, + {0x0113c2, 0x0}, + {0x1113c2, 0x0}, + {0x2113c2, 0x0}, + {0x0114c2, 0x0}, + {0x1114c2, 0x0}, + {0x2114c2, 0x0}, + {0x0115c2, 0x0}, + {0x1115c2, 0x0}, + {0x2115c2, 0x0}, + {0x0116c2, 0x0}, + {0x1116c2, 0x0}, + {0x2116c2, 0x0}, + {0x0117c2, 0x0}, + {0x1117c2, 0x0}, + {0x2117c2, 0x0}, + {0x0118c2, 0x0}, + {0x1118c2, 0x0}, + {0x2118c2, 0x0}, + {0x0110c3, 0x0}, + {0x1110c3, 0x0}, + {0x2110c3, 0x0}, + {0x0111c3, 0x0}, + {0x1111c3, 0x0}, + {0x2111c3, 0x0}, + {0x0112c3, 0x0}, + {0x1112c3, 0x0}, + {0x2112c3, 0x0}, + {0x0113c3, 0x0}, + {0x1113c3, 0x0}, + {0x2113c3, 0x0}, + {0x0114c3, 0x0}, + {0x1114c3, 0x0}, + {0x2114c3, 0x0}, + {0x0115c3, 0x0}, + {0x1115c3, 0x0}, + {0x2115c3, 0x0}, + {0x0116c3, 0x0}, + {0x1116c3, 0x0}, + {0x2116c3, 0x0}, + {0x0117c3, 0x0}, + {0x1117c3, 0x0}, + {0x2117c3, 0x0}, + {0x0118c3, 0x0}, + {0x1118c3, 0x0}, + {0x2118c3, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, +}; + diff --git a/board/freescale/imx8mm_ab2/imx8mm_ab2.c b/board/freescale/imx8mm_ab2/imx8mm_ab2.c index 9852827..6b5fc76 100644 --- a/board/freescale/imx8mm_ab2/imx8mm_ab2.c +++ b/board/freescale/imx8mm_ab2/imx8mm_ab2.c @@ -14,6 +14,8 @@ #include #ifdef CONFIG_TARGET_IMX8MM_AB2 #include +#else +#include #endif #include #include @@ -49,6 +51,25 @@ static iomux_v3_cfg_t const pwr_en_ana[] = { }; #endif +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwr_en_5v0[] = { + IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwr_en_ana[] = { + IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + #ifdef CONFIG_NAND_MXS static void setup_gpmi_nand(void) { @@ -118,7 +139,11 @@ int board_late_init(void) #endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "AB2"); +#ifdef CONFIG_TARGET_IMX8MM_AB2 env_set("board_rev", "iMX8MM"); +#else + env_set("board_rev", "iMX8MN"); +#endif #endif return 0; } diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c new file mode 100644 index 0000000..8929bc6 --- /dev/null +++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c @@ -0,0 +1,1585 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400020, 0x00000213}, + {0x3d400024, 0x0003e800}, + {0x3d400030, 0x00000120}, + {0x3d400000, 0xa3080020}, + {0x3d400064, 0x006100e0}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x009e0000}, + {0x3d4000dc, 0x00d4002d}, + {0x3d4000e0, 0x00310000}, + {0x3d4000e8, 0x0066004d}, + {0x3d4000ec, 0x0016004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x00060633}, + {0x3d40010c, 0x00c0c000}, + {0x3d400110, 0x0f04080f}, + {0x3d400114, 0x02040c0c}, + {0x3d400118, 0x01010007}, + {0x3d40011c, 0x00000401}, + {0x3d400130, 0x00020600}, + {0x3d400134, 0x0c100002}, + {0x3d400138, 0x000000e6}, + {0x3d400144, 0x00a00050}, + {0x3d400180, 0x03200018}, + {0x3d400184, 0x028061a8}, + {0x3d400188, 0x00000000}, + {0x3d400190, 0x0497820a}, + {0x3d4001b4, 0x0000170a}, + {0x3d400108, 0x070e1617}, + {0x3d4001c0, 0x00000001}, + {0x3d400194, 0x00080303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0x00df00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x00000011}, + {0x3d4001c4, 0x00000001}, + {0x3d4000f4, 0x00000c99}, + {0x3d400200, 0x00000017}, + {0x3d400204, 0x00080808}, + {0x3d400208, 0x00000000}, + {0x3d40020c, 0x00000000}, + {0x3d400210, 0x00001f1f}, + {0x3d400214, 0x07070707}, + {0x3d400218, 0x07070707}, + {0x3d40021c, 0x00000f0f}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x0000002c}, + {0x3d40025c, 0x04000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x20005574}, + {0x3d400400, 0x00000111}, + {0x3d400408, 0x000072ff}, + {0x3d400494, 0x02100e07}, + {0x3d400498, 0x00620096}, + {0x3d40049c, 0x01100e07}, + {0x3d4004a0, 0x00c8012c}, + {0x3d402020, 0x00000011}, + {0x3d402024, 0x00007d00}, + {0x3d402050, 0x0020d040}, + {0x3d402064, 0x000c001d}, + {0x3d4020f4, 0x00000c99}, + {0x3d402100, 0x0a040305}, + {0x3d402104, 0x00030407}, + {0x3d402108, 0x0203060b}, + {0x3d40210c, 0x00505000}, + {0x3d402110, 0x02040202}, + {0x3d402114, 0x02030202}, + {0x3d402118, 0x01010004}, + {0x3d40211c, 0x00000301}, + {0x3d402130, 0x00020300}, + {0x3d402134, 0x0a100002}, + {0x3d402138, 0x0000001d}, + {0x3d402144, 0x0014000a}, + {0x3d402180, 0x00650004}, + {0x3d402190, 0x03818200}, + {0x3d402194, 0x00080303}, + {0x3d4021b4, 0x00000100}, + {0x3d4020dc, 0x00840000}, + {0x3d4020e0, 0x00310000}, + {0x3d4020e8, 0x0066004d}, + {0x3d4020ec, 0x0016004a}, + {0x3d403020, 0x00000011}, + {0x3d403024, 0x00001f40}, + {0x3d403050, 0x0020d040}, + {0x3d403064, 0x00030007}, + {0x3d4030f4, 0x00000c99}, + {0x3d403100, 0x0a010102}, + {0x3d403104, 0x00030404}, + {0x3d403108, 0x0203060b}, + {0x3d40310c, 0x00505000}, + {0x3d403110, 0x02040202}, + {0x3d403114, 0x02030202}, + {0x3d403118, 0x01010004}, + {0x3d40311c, 0x00000301}, + {0x3d403130, 0x00020300}, + {0x3d403134, 0x0a100002}, + {0x3d403138, 0x00000008}, + {0x3d403144, 0x00050003}, + {0x3d403180, 0x00190004}, + {0x3d403190, 0x03818200}, + {0x3d403194, 0x00080303}, + {0x3d4031b4, 0x00000100}, + {0x3d4030dc, 0x00840000}, + {0x3d4030e0, 0x00310000}, + {0x3d4030e8, 0x0066004d}, + {0x3d4030ec, 0x0016004a}, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x000100a0, 0x00000000}, + {0x000100a1, 0x00000001}, + {0x000100a2, 0x00000002}, + {0x000100a3, 0x00000003}, + {0x000100a4, 0x00000004}, + {0x000100a5, 0x00000005}, + {0x000100a6, 0x00000006}, + {0x000100a7, 0x00000007}, + {0x000110a0, 0x00000000}, + {0x000110a1, 0x00000001}, + {0x000110a2, 0x00000003}, + {0x000110a3, 0x00000004}, + {0x000110a4, 0x00000005}, + {0x000110a5, 0x00000002}, + {0x000110a6, 0x00000007}, + {0x000110a7, 0x00000006}, + {0x0001005f, 0x0000015f}, + {0x0001015f, 0x0000015f}, + {0x0001105f, 0x0000015f}, + {0x0001115f, 0x0000015f}, + {0x0011005f, 0x0000015f}, + {0x0011015f, 0x0000015f}, + {0x0011105f, 0x0000015f}, + {0x0011115f, 0x0000015f}, + {0x0021005f, 0x0000015f}, + {0x0021015f, 0x0000015f}, + {0x0021105f, 0x0000015f}, + {0x0021115f, 0x0000015f}, + {0x00000055, 0x0000016f}, + {0x00001055, 0x0000016f}, + {0x00002055, 0x0000016f}, + {0x00003055, 0x0000016f}, + {0x00004055, 0x0000016f}, + {0x00005055, 0x0000016f}, + {0x00006055, 0x0000016f}, + {0x00007055, 0x0000016f}, + {0x00008055, 0x0000016f}, + {0x00009055, 0x0000016f}, + {0x000200c5, 0x00000019}, + {0x001200c5, 0x00000007}, + {0x002200c5, 0x00000007}, + {0x0002002e, 0x00000002}, + {0x0012002e, 0x00000002}, + {0x0022002e, 0x00000002}, + {0x00090204, 0x00000000}, + {0x00190204, 0x00000000}, + {0x00290204, 0x00000000}, + {0x00020024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0002007d, 0x00000212}, + {0x0002007c, 0x00000061}, + {0x00120024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0012007d, 0x00000212}, + {0x0012007c, 0x00000061}, + {0x00220024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0022007d, 0x00000212}, + {0x0022007c, 0x00000061}, + {0x00020056, 0x00000003}, + {0x00120056, 0x00000003}, + {0x00220056, 0x00000003}, + {0x0001004d, 0x00000f80}, + {0x0001014d, 0x00000f80}, + {0x0001104d, 0x00000f80}, + {0x0001114d, 0x00000f80}, + {0x0011004d, 0x00000f80}, + {0x0011014d, 0x00000f80}, + {0x0011104d, 0x00000f80}, + {0x0011114d, 0x00000f80}, + {0x0021004d, 0x00000f80}, + {0x0021014d, 0x00000f80}, + {0x0021104d, 0x00000f80}, + {0x0021114d, 0x00000f80}, + {0x00010049, 0x00000fbe}, + {0x00010149, 0x00000fbe}, + {0x00011049, 0x00000fbe}, + {0x00011149, 0x00000fbe}, + {0x00110049, 0x00000fbe}, + {0x00110149, 0x00000fbe}, + {0x00111049, 0x00000fbe}, + {0x00111149, 0x00000fbe}, + {0x00210049, 0x00000fbe}, + {0x00210149, 0x00000fbe}, + {0x00211049, 0x00000fbe}, + {0x00211149, 0x00000fbe}, + {0x00000043, 0x00000063}, + {0x00001043, 0x00000063}, + {0x00002043, 0x00000063}, + {0x00003043, 0x00000063}, + {0x00004043, 0x00000063}, + {0x00005043, 0x00000063}, + {0x00006043, 0x00000063}, + {0x00007043, 0x00000063}, + {0x00008043, 0x00000063}, + {0x00009043, 0x00000063}, + {0x00020018, 0x00000001}, + {0x00020075, 0x00000004}, + {0x00020050, 0x00000000}, + {0x00020008, 0x00000320}, + {0x00120008, 0x00000064}, + {0x00220008, 0x00000019}, + {0x00020088, 0x00000009}, + {0x000200b2, 0x000000dc}, + {0x00010043, 0x000005a1}, + {0x00010143, 0x000005a1}, + {0x00011043, 0x000005a1}, + {0x00011143, 0x000005a1}, + {0x001200b2, 0x000000dc}, + {0x00110043, 0x000005a1}, + {0x00110143, 0x000005a1}, + {0x00111043, 0x000005a1}, + {0x00111143, 0x000005a1}, + {0x002200b2, 0x000000dc}, + {0x00210043, 0x000005a1}, + {0x00210143, 0x000005a1}, + {0x00211043, 0x000005a1}, + {0x00211143, 0x000005a1}, + {0x000200fa, 0x00000001}, + {0x001200fa, 0x00000001}, + {0x002200fa, 0x00000001}, + {0x00020019, 0x00000001}, + {0x00120019, 0x00000001}, + {0x00220019, 0x00000001}, + {0x000200f0, 0x00000660}, + {0x000200f1, 0x00000000}, + {0x000200f2, 0x00004444}, + {0x000200f3, 0x00008888}, + {0x000200f4, 0x00005665}, + {0x000200f5, 0x00000000}, + {0x000200f6, 0x00000000}, + {0x000200f7, 0x0000f000}, + {0x0001004a, 0x00000500}, + {0x0001104a, 0x00000500}, + {0x00020025, 0x00000000}, + {0x0002002d, 0x00000000}, + {0x0012002d, 0x00000000}, + {0x0022002d, 0x00000000}, + {0x0002002c, 0x00000000}, + {0x000200c7, 0x00000021}, + {0x000200ca, 0x00000024}, + {0x000200cc, 0x000001f7}, + {0x001200c7, 0x00000021}, + {0x001200ca, 0x00000024}, + {0x001200cc, 0x000001f7}, + {0x002200c7, 0x00000021}, + {0x002200ca, 0x00000024}, + {0x002200cc, 0x000001f7}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000131f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000101}, + {0x00054003, 0x00000190}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000102}, + {0x00054003, 0x00000064}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x00000061}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00001f7f}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x448}, + {0x90169, 0x109}, + {0x9016a, 0xf}, + {0x9016b, 0x7c0}, + {0x9016c, 0x109}, + {0x9016d, 0x0}, + {0x9016e, 0xe8}, + {0x9016f, 0x109}, + {0x90170, 0x47}, + {0x90171, 0x630}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0x618}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0xe0}, + {0x90178, 0x109}, + {0x90179, 0x0}, + {0x9017a, 0x7c8}, + {0x9017b, 0x109}, + {0x9017c, 0x8}, + {0x9017d, 0x8140}, + {0x9017e, 0x10c}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x7c8}, + {0x90187, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mm_ab2/spl.c b/board/freescale/imx8mm_ab2/spl.c index cfd3d8a..a18209f 100644 --- a/board/freescale/imx8mm_ab2/spl.c +++ b/board/freescale/imx8mm_ab2/spl.c @@ -24,6 +24,8 @@ #ifdef CONFIG_TARGET_IMX8MM_AB2 #include +#else +#include #endif #ifdef CONFIG_POWER_PCA9450 @@ -36,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; int spl_board_boot_device(enum boot_device boot_dev_spl) { +#ifdef CONFIG_TARGET_IMX8MM_AB2 switch (boot_dev_spl) { case SD2_BOOT: case MMC2_BOOT: @@ -52,6 +55,9 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) default: return BOOT_DEVICE_NONE; } +#else + return BOOT_DEVICE_BOOTROM; +#endif } void spl_dram_init(void) @@ -81,6 +87,21 @@ struct i2c_pads_info i2c_pad_info1 = { }; #endif +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MN_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MN_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MN_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; +#endif + #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) @@ -110,6 +131,32 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { }; #endif +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MN_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MN_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MN_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MN_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), +}; +#endif + static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC2_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR, 0, 8}, @@ -177,12 +224,13 @@ int board_mmc_getcd(struct mmc *mmc) #ifdef CONFIG_POWER #define I2C_PMIC 0 + +#ifdef CONFIG_POWER_PCA9450 int power_init_board(void) { struct pmic *p; int ret; -#ifdef CONFIG_POWER_PCA9450 ret = power_pca9450b_init(I2C_PMIC); if (ret) printf("power init failed"); @@ -202,14 +250,25 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); - /* Kernel uses OD/OD freq for SOC */ - /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); - +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0); + /* enable LDO4 to 1.2v */ + pmic_reg_write(p, PCA9450_LDO4CTRL, 0x44); +#endif /* set WDOG_B_CFG to cold reset */ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); -#else + return 0; +} +#endif /* CONFIG_POWER_PCA9450 */ + +#ifdef CONFIG_POWER_BD71837 +int power_init_board(void) +{ + struct pmic *p; + int ret; + ret = power_bd71837_init(I2C_PMIC); if (ret) printf("power init failed"); @@ -220,21 +279,39 @@ int power_init_board(void) pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); /* unlock the PMIC regs */ pmic_reg_write(p, BD71837_REGLOCK, 0x1); +#ifdef CONFIG_TARGET_IMX8MM_AB2 /* increase VDD_SOC to typical value 0.85v before first DRAM access */ pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); -#ifndef CONFIG_IMX8M_LPDDR4 +#ifdef CONFIG_IMX8M_DDR4 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); +#endif +#endif /* CONFIG_TARGET_IMX8MM_AB2 */ + +#if defined(CONFIG_TARGET_IMX8MN_AB2) || defined(CONFIG_TARGET_IMX8MN_DDR4_AB2) + /* Set VDD_ARM to typical value 0.85v for 1.2Ghz */ + pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0xf); +#ifdef CONFIG_IMX8M_DDR4 + /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0xf); +#endif + /* Set VDD_SOC 0.85v for suspend */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_SUSP, 0xf); +#ifdef CONFIG_IMX8M_DDR4 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); #endif +#endif /* CONFIG_TARGET_IMX8MN_AB2 */ + /* lock the PMIC regs */ pmic_reg_write(p, BD71837_REGLOCK, 0x11); -#endif return 0; } -#endif +#endif /* CONFIG_POWER_BD71837 */ +#endif /* CONFIG_POWER */ void spl_board_init(void) { diff --git a/configs/imx8mn_ab2_defconfig b/configs/imx8mn_ab2_defconfig new file mode 100644 index 0000000..83d0cae --- /dev/null +++ b/configs/imx8mn_ab2_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_IMX8MN_AB2=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_CSF_SIZE=0x2000 +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ab2" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ab2.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_NXP_TMU=y + +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mn_ddr4_ab2_defconfig b/configs/imx8mn_ddr4_ab2_defconfig new file mode 100644 index 0000000..d346408 --- /dev/null +++ b/configs/imx8mn_ddr4_ab2_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_IMX8MN_DDR4_AB2=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_CSF_SIZE=0x2000 +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg" +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-ab2" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-ab2.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_NXP_TMU=y + +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/imx8mn_ab2.h b/include/configs/imx8mn_ab2.h new file mode 100644 index 0000000..3499a84 --- /dev/null +++ b/include/configs/imx8mn_ab2.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8MN_AB2_H +#define __IMX8MN_AB2_H + +#include +#include + +#include "imx_env.h" + +#define CONFIG_SPL_MAX_SIZE (208 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_64K /* 64 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x184000 + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#ifdef CONFIG_IMX8M_DDR4 +#define CONFIG_POWER_BD71837 +#else +#define CONFIG_POWER_PCA9450 +#endif + +#define CONFIG_SYS_I2C + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG + +#define CONFIG_REMAKE_ELF +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "eth0" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 +#endif + + +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mm.c, then clk_ingore_unused could be removed. + */ +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file imx8mn-ddr4-ab2-root.dtb;" \ + "setenv jh_clk clk_ignore_unused; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file imx8mn-ddr4-ab2-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=no\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_FSL_FSPI +#define FSL_FSPI_FLASH_SIZE SZ_32M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x30bb0000 +#define FSPI0_AMBA_BASE 0x0 +#define CONFIG_FSPI_QUAD_SUPPORT + +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif -- 1.9.1