Commit 5da847a4fad5d85aab497c78a6008cd94b750b35
1 parent
b053775c03
Exists in
smarc-imx_v2018.03_4.14.78_1.0.0_ga
MLK-20635 imx8: clock: Fix GPR settings for FEC
FEC has some clock settings inside DSC GPR. Kernel configures them, but u-boot not. So when doing partition reset, the GPR keeps the value from kernel, and cause clock issue to u-boot FEC: kernel enables the divclk in GPR and set the clock slice to 250Mhz, u-boot configures the clock slice to 125Mhz, the divclk causes the RGMII TX CLK to 62.5Mhz. Fix the issue by aligning the GPR and clock slice settings with kernel Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit ab6b18bcf3cade15586839274bfde2030726ad37)
Showing 1 changed file with 12 additions and 2 deletions Side-by-side Diff
arch/arm/mach-imx/imx8/clock.c
... | ... | @@ -403,8 +403,10 @@ |
403 | 403 | return; |
404 | 404 | } |
405 | 405 | |
406 | - /* Set SC_R_ENET_0 clock root to 125 MHz */ | |
407 | - rate = 125000000; | |
406 | + /* Set SC_R_ENET_0 clock root to 250 MHz, the clkdiv is set to div 2 | |
407 | + * so finally RGMII TX clk is 125Mhz | |
408 | + */ | |
409 | + rate = 250000000; | |
408 | 410 | |
409 | 411 | /* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */ |
410 | 412 | err = sc_pm_set_clock_rate(ipc, enet[index], 2, &rate); |
... | ... | @@ -421,6 +423,14 @@ |
421 | 423 | printf("\nSC_R_ENET_0 set clock enable failed! (error = %d)\n", err); |
422 | 424 | return; |
423 | 425 | } |
426 | + | |
427 | + /* Configure GPR regisers */ | |
428 | + sc_misc_set_control(ipc, enet[index], SC_C_TXCLK, 0); | |
429 | + sc_misc_set_control(ipc, enet[index], SC_C_CLKDIV, 1); /* Enable divclk */ | |
430 | + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 1); | |
431 | + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_125, 1); | |
432 | + sc_misc_set_control(ipc, enet[index], SC_C_SEL_125, 0); | |
433 | + sc_misc_set_control(ipc, enet[index], SC_C_IPG_STOP, 0); | |
424 | 434 | |
425 | 435 | LPCG_AllClockOn(ENET_0_LPCG + index * 0x10000); |
426 | 436 | } |