Eric Lee / smarc-uboot

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Commit 653c84e3e50a32bd82afc3a5294a8288988eed7e

Authored by Ye Li
1 parent 443b88f333
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22748 imx8mn: Fix flexspi flash SCLK violation 

Current flexspi driver enables the Quad DTR read, so the measured
100Mhz SCLK is actually for DTR mode not SDR. However, according to
MT25QU256ABA datasheet, this flash only supports max DTR at 90Mhz and
max SDR at 166Mhz. It means current clock setting violate the flash
spec. So change back the flexspi clock to align with imx8mm.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 3bf41bae974003550b70ea1a8b44ccb3117d818f)
(cherry picked from commit 4a369b527c3842751a4edf0171562a0e40c331ba)

Showing 1 changed file with 1 additions and 8 deletions Side-by-side Diff

arch/arm/mach-imx/imx8m/clock_imx8mm.c
Diff comments   View file @ 653c84e
... ... @@ -728,14 +728,7 @@
728 728 * sys pll1 100M
729 729 */
730 730 clock_enable(CCGR_QSPI, 0);
731   -
732   - if (is_imx8mn()) {
733   - clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
734   - CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
735   - } else {
736   - clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
737   - CLK_ROOT_SOURCE_SEL(7));
738   - }
  731 + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7));
739 732 clock_enable(CCGR_QSPI, 1);
740 733  
741 734 return 0;