diff --git a/arch/arm/dts/imx7d-smarcfimx7.dts b/arch/arm/dts/imx7d-smarcfimx7.dts index 0ba5813..da8dd9a 100644 --- a/arch/arm/dts/imx7d-smarcfimx7.dts +++ b/arch/arm/dts/imx7d-smarcfimx7.dts @@ -216,7 +216,7 @@ <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,magic-packet; status = "okay"; @@ -225,14 +225,14 @@ #address-cells = <1>; #size-cells = <0>; - ethphy0: ethernet-phy@6 { + ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; + reg = <1>; }; - ethphy1: ethernet-phy@7 { + ethphy1: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; + reg = <2>; }; }; }; @@ -249,7 +249,7 @@ <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy1>; fsl,magic-packet; status = "okay"; diff --git a/arch/arm/dts/imx7s-smarcfimx7.dts b/arch/arm/dts/imx7s-smarcfimx7.dts index a47fc4b..1c8ee98 100644 --- a/arch/arm/dts/imx7s-smarcfimx7.dts +++ b/arch/arm/dts/imx7s-smarcfimx7.dts @@ -190,9 +190,9 @@ #address-cells = <1>; #size-cells = <0>; - ethphy0: ethernet-phy@6 { + ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; + reg = <1>; }; }; }; diff --git a/include/configs/smarcfimx7.h b/include/configs/smarcfimx7.h index 868a764..48c7daf 100644 --- a/include/configs/smarcfimx7.h +++ b/include/configs/smarcfimx7.h @@ -35,15 +35,15 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_ENET_DEV 0 -#define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_REALTEK /* ENET1 */ #if (CONFIG_FEC_ENET_DEV == 0) #define IMX_FEC_BASE ENET_IPS_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x6 +#define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_ETHPRIME "eth0" #elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE ENET2_IPS_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x7 +#define CONFIG_FEC_MXC_PHYADDR 0x2 #define CONFIG_ETHPRIME "eth1" #endif