Eric Lee / smarc-uboot

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Commit 71e4d73734f74bd9cfb2be435fc553afe09a9002

Authored by Ye Li
1 parent e3c8f8e376
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22757-1 imx8: Update SCFW API to fix HDP authentication issue 

Current codes have wrong definitions for SC_MISC_SECO_AUTH_SECO_FW,
SC_MISC_SECO_AUTH_HDMI_TX_FW and SC_MISC_SECO_AUTH_HDMI_RX_FW and
cause HDP firmware authentication failed.

Sync the API definitions with latest SCFW export.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 87ee3c16a649a418b8c6fdae53234f88a90c8fb3)

Showing 11 changed files with 377 additions and 76 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx8/sci/rpc.h
Diff comments   View file @ 71e4d73
... ... @@ -8,6 +8,11 @@
8 8 #define SC_RPC_H
9 9  
10 10 /* Note: Check SCFW API Released DOC before you want to modify something */
  11 +/* Defines */
  12 +
  13 +#define SCFW_API_VERSION_MAJOR 1U
  14 +#define SCFW_API_VERSION_MINOR 13U
  15 +
11 16 #define SC_RPC_VERSION 1U
12 17  
13 18 #define SC_RPC_MAX_MSG 8U
14 19  
... ... @@ -58,7 +63,9 @@
58 63 #define PM_FUNC_SET_SYS_POWER_MODE 19U
59 64 #define PM_FUNC_SET_PARTITION_POWER_MODE 1U
60 65 #define PM_FUNC_GET_SYS_POWER_MODE 2U
  66 +#define PM_FUNC_PARTITION_WAKE 28U
61 67 #define PM_FUNC_SET_RESOURCE_POWER_MODE 3U
  68 +#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U
62 69 #define PM_FUNC_GET_RESOURCE_POWER_MODE 4U
63 70 #define PM_FUNC_REQ_LOW_POWER_MODE 16U
64 71 #define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U
65 72  
66 73  
67 74  
... ... @@ -72,10 +79,14 @@
72 79 #define PM_FUNC_GET_CLOCK_PARENT 15U
73 80 #define PM_FUNC_RESET 13U
74 81 #define PM_FUNC_RESET_REASON 10U
  82 +#define PM_FUNC_GET_RESET_PART 26U
75 83 #define PM_FUNC_BOOT 8U
  84 +#define PM_FUNC_SET_BOOT_PARM 27U
76 85 #define PM_FUNC_REBOOT 9U
77 86 #define PM_FUNC_REBOOT_PARTITION 12U
  87 +#define PM_FUNC_REBOOT_CONTINUE 25U
78 88 #define PM_FUNC_CPU_START 11U
  89 +#define PM_FUNC_CPU_RESET 23U
79 90 #define PM_FUNC_IS_PARTITION_STARTED 24U
80 91  
81 92 /* MISC RPC */
82 93  
... ... @@ -84,16 +95,10 @@
84 95 #define MISC_FUNC_GET_CONTROL 2U
85 96 #define MISC_FUNC_SET_MAX_DMA_GROUP 4U
86 97 #define MISC_FUNC_SET_DMA_GROUP 5U
87   -#define MISC_FUNC_SECO_IMAGE_LOAD 8U
88   -#define MISC_FUNC_SECO_AUTHENTICATE 9U
89   -#define MISC_FUNC_SECO_FUSE_WRITE 20U
90   -#define MISC_FUNC_SECO_ENABLE_DEBUG 21U
91   -#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U
92   -#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U
93   -#define MISC_FUNC_SECO_BUILD_INFO 24U
94 98 #define MISC_FUNC_DEBUG_OUT 10U
95 99 #define MISC_FUNC_WAVEFORM_CAPTURE 6U
96 100 #define MISC_FUNC_BUILD_INFO 15U
  101 +#define MISC_FUNC_API_VER 35U
97 102 #define MISC_FUNC_UNIQUE_ID 19U
98 103 #define MISC_FUNC_SET_ARI 3U
99 104 #define MISC_FUNC_BOOT_STATUS 7U
100 105  
... ... @@ -103,7 +108,11 @@
103 108 #define MISC_FUNC_SET_TEMP 12U
104 109 #define MISC_FUNC_GET_TEMP 13U
105 110 #define MISC_FUNC_GET_BOOT_DEV 16U
  111 +#define MISC_FUNC_GET_BOOT_TYPE 33U
  112 +#define MISC_FUNC_GET_BOOT_CONTAINER 36U
106 113 #define MISC_FUNC_GET_BUTTON_STATUS 18U
  114 +#define MISC_FUNC_ROMPATCH_CHECKSUM 26U
  115 +#define MISC_FUNC_BOARD_IOCTL 34U
107 116  
108 117 /* PAD RPC */
109 118 #define PAD_FUNC_UNKNOWN 0
... ... @@ -148,6 +157,7 @@
148 157 #define RM_FUNC_GET_RESOURCE_INFO 16U
149 158 #define RM_FUNC_MEMREG_ALLOC 17U
150 159 #define RM_FUNC_MEMREG_SPLIT 29U
  160 +#define RM_FUNC_MEMREG_FRAG 32U
151 161 #define RM_FUNC_MEMREG_FREE 18U
152 162 #define RM_FUNC_FIND_MEMREG 30U
153 163 #define RM_FUNC_ASSIGN_MEMREG 19U
... ... @@ -160,27 +170,59 @@
160 170 #define RM_FUNC_DUMP 27U
161 171  
162 172 /* SECO RPC */
163   -#define SECO_FUNC_UNKNOWN 0 /*!< Unknown function */
164   -#define SECO_FUNC_IMAGE_LOAD 1U /*!< Index for seco_image_load() RPC call */
165   -#define SECO_FUNC_AUTHENTICATE 2U /*!< Index for seco_authenticate() RPC call */
166   -#define SECO_FUNC_FORWARD_LIFECYCLE 3U /*!< Index for seco_forward_lifecycle() RPC call */
167   -#define SECO_FUNC_RETURN_LIFECYCLE 4U /*!< Index for seco_return_lifecycle() RPC call */
168   -#define SECO_FUNC_COMMIT 5U /*!< Index for seco_commit() RPC call */
169   -#define SECO_FUNC_ATTEST_MODE 6U /*!< Index for seco_attest_mode() RPC call */
170   -#define SECO_FUNC_ATTEST 7U /*!< Index for seco_attest() RPC call */
171   -#define SECO_FUNC_GET_ATTEST_PKEY 8U /*!< Index for seco_get_attest_pkey() RPC call */
172   -#define SECO_FUNC_GET_ATTEST_SIGN 9U /*!< Index for seco_get_attest_sign() RPC call */
173   -#define SECO_FUNC_ATTEST_VERIFY 10U /*!< Index for seco_attest_verify() RPC call */
174   -#define SECO_FUNC_GEN_KEY_BLOB 11U /*!< Index for seco_gen_key_blob() RPC call */
175   -#define SECO_FUNC_LOAD_KEY 12U /*!< Index for seco_load_key() RPC call */
176   -#define SECO_FUNC_GET_MP_KEY 13U /*!< Index for seco_get_mp_key() RPC call */
177   -#define SECO_FUNC_UPDATE_MPMR 14U /*!< Index for seco_update_mpmr() RPC call */
178   -#define SECO_FUNC_GET_MP_SIGN 15U /*!< Index for seco_get_mp_sign() RPC call */
179   -#define SECO_FUNC_BUILD_INFO 16U /*!< Index for seco_build_info() RPC call */
180   -#define SECO_FUNC_CHIP_INFO 17U /*!< Index for seco_chip_info() RPC call */
181   -#define SECO_FUNC_ENABLE_DEBUG 18U /*!< Index for seco_enable_debug() RPC call */
182   -#define SECO_FUNC_GET_EVENT 19U /*!< Index for seco_get_event() RPC call */
183   -#define SECO_FUNC_FUSE_WRITE 20U /*!< Index for seco_fuse_write() RPC call */
  173 +#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
  174 +#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
  175 +#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
  176 +#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */
  177 +#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
  178 +#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
  179 +#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
  180 +#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
  181 +#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
  182 +#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
  183 +#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
  184 +#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
  185 +#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
  186 +#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
  187 +#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
  188 +#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
  189 +#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
  190 +#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
  191 +#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
  192 +#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
  193 +#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
  194 +#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
  195 +#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */
  196 +#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */
  197 +#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */
  198 +#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */
  199 +#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */
  200 +
  201 +/* IRQ RPC */
  202 +#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
  203 +#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */
  204 +#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */
  205 +
  206 +/* TIMER RPC */
  207 +#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
  208 +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
  209 +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
  210 +#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
  211 +#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
  212 +#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
  213 +#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */
  214 +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */
  215 +#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */
  216 +#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */
  217 +#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */
  218 +#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */
  219 +#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */
  220 +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */
  221 +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */
  222 +#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */
  223 +#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */
  224 +#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
  225 +#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
184 226  
185 227 #endif /* SC_RPC_H */
arch/arm/include/asm/arch-imx8/sci/sci.h
Diff comments   View file @ 71e4d73
... ... @@ -13,6 +13,8 @@
13 13 #include <asm/arch/sci/svc/pm/api.h>
14 14 #include <asm/arch/sci/svc/rm/api.h>
15 15 #include <asm/arch/sci/svc/seco/api.h>
  16 +#include <asm/arch/sci/svc/irq/api.h>
  17 +#include <asm/arch/sci/svc/timer/api.h>
16 18 #include <asm/arch/sci/rpc.h>
17 19 #include <dt-bindings/soc/imx_rsrc.h>
18 20 #include <linux/errno.h>
arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h
Diff comments   View file @ 71e4d73
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018-2019 NXP
  4 + */
  5 +
  6 +#ifndef SC_IRQ_API_H
  7 +#define SC_IRQ_API_H
  8 +
  9 +/* Defines */
  10 +
  11 +#define SC_IRQ_NUM_GROUP 7U /* Number of groups */
  12 +
  13 +/* Defines for sc_irq_group_t */
  14 +#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */
  15 +#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */
  16 +#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */
  17 +#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */
  18 +#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */
  19 +#define SC_IRQ_GROUP_REBOOTED 5U /* Partition reboot complete */
  20 +#define SC_IRQ_GROUP_REBOOT 6U /* Partition reboot starting */
  21 +
  22 +/* Defines for sc_irq_temp_t */
  23 +#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */
  24 +#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */
  25 +#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */
  26 +#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */
  27 +#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */
  28 +#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */
  29 +#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */
  30 +#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */
  31 +#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */
  32 +#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */
  33 +#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */
  34 +#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */
  35 +#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */
  36 +#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */
  37 +#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */
  38 +#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */
  39 +#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */
  40 +#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */
  41 +#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */
  42 +#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */
  43 +#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */
  44 +#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */
  45 +
  46 +/* Defines for sc_irq_wdog_t */
  47 +#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */
  48 +
  49 +/* Defines for sc_irq_rtc_t */
  50 +#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */
  51 +
  52 +/* Defines for sc_irq_wake_t */
  53 +#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */
  54 +#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */
  55 +#define SC_IRQ_USR1 (1U << 2U) /* User defined 1 */
  56 +#define SC_IRQ_USR2 (1U << 3U) /* User defined 2 */
  57 +#define SC_IRQ_BC_PAD (1U << 4U) /* Pad wakeup (broadcast to all partitions) */
  58 +#define SC_IRQ_SW_WAKE (1U << 5U) /* Software requested wake */
  59 +#define SC_IRQ_SECVIO (1U << 6U) /* Security violation */
  60 +
  61 +/* Defines for sc_irq_sysctr_t */
  62 +#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */
  63 +
  64 +/* Types */
  65 +
  66 +/*
  67 + * This type is used to declare an interrupt group.
  68 + */
  69 +typedef u8 sc_irq_group_t;
  70 +
  71 +/*
  72 + * This type is used to declare a bit mask of temp interrupts.
  73 + */
  74 +typedef u8 sc_irq_temp_t;
  75 +
  76 +/*
  77 + * This type is used to declare a bit mask of watchdog interrupts.
  78 + */
  79 +typedef u8 sc_irq_wdog_t;
  80 +
  81 +/*
  82 + * This type is used to declare a bit mask of RTC interrupts.
  83 + */
  84 +typedef u8 sc_irq_rtc_t;
  85 +
  86 +/*
  87 + * This type is used to declare a bit mask of wakeup interrupts.
  88 + */
  89 +typedef u8 sc_irq_wake_t;
  90 +
  91 +#endif /* SC_IRQ_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
Diff comments   View file @ 71e4d73
... ... @@ -5,29 +5,46 @@
5 5  
6 6 #ifndef SC_MISC_API_H
7 7 #define SC_MISC_API_H
  8 +/* Defines for type widths */
  9 +#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */
8 10  
  11 +/* Max DMA channel priority group */
  12 +#define SC_MISC_DMA_GRP_MAX 31U
9 13 /* Defines for sc_misc_boot_status_t */
10 14 #define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */
11 15 #define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */
12 16  
13   -/* Defines for sc_misc_seco_auth_cmd_t */
14   -#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */
15   -#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */
16   -#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */
17   -
18 17 /* Defines for sc_misc_temp_t */
19   -#define SC_MISC_TEMP 0U /* Temp sensor */
20   -#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
21   -#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
  18 +#define SC_MISC_TEMP 0U /* Temp sensor */
  19 +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
  20 +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
22 21  
23   -/* Defines for sc_misc_seco_auth_cmd_t */
24   -#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */
25   -#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */
26   -#define SC_MISC_REL_CONTAINER 2U /* Release container */
  22 +/* Defines for sc_misc_bt_t */
  23 +#define SC_MISC_BT_PRIMARY 0U /* Primary boot */
  24 +#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */
  25 +#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */
  26 +#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */
  27 +#define SC_MISC_BT_SERIAL 4U /* Serial boot */
  28 +/* Types */
27 29  
  30 +/*
  31 + * This type is used to store a DMA channel priority group.
  32 + */
  33 +typedef u8 sc_misc_dma_group_t;
  34 +
  35 +/*
  36 + * This type is used report boot status.
  37 + */
28 38 typedef u8 sc_misc_boot_status_t;
29 39  
  40 +/*
  41 + * This type is used report boot status.
  42 + */
30 43 typedef u8 sc_misc_temp_t;
31 44  
  45 +/*
  46 + * This type is used report the boot type.
  47 + */
  48 +typedef u8 sc_misc_bt_t;
32 49 #endif /* SC_MISC_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
Diff comments   View file @ 71e4d73
... ... @@ -6,6 +6,14 @@
6 6 #ifndef SC_PM_API_H
7 7 #define SC_PM_API_H
8 8  
  9 +#include <asm/arch/sci/types.h>
  10 +/* Defines for type widths */
  11 +#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */
  12 +#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */
  13 +#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */
  14 +#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */
  15 +/* Defines for ALL parameters */
  16 +#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */
9 17 /* Defines for sc_pm_power_mode_t */
10 18 #define SC_PM_PW_MODE_OFF 0U /* Power off */
11 19 #define SC_PM_PW_MODE_STBY 1U /* Power in standby */
12 20  
13 21  
14 22  
15 23  
16 24  
... ... @@ -42,11 +50,85 @@
42 50 #define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */
43 51 #define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */
44 52  
  53 +/* Defines for sc_pm_reset_type_t */
  54 +#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */
  55 +#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */
  56 +#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */
  57 +
  58 +/* Defines for sc_pm_reset_reason_t */
  59 +#define SC_PM_RESET_REASON_POR 0U /* Power on reset */
  60 +#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */
  61 +#define SC_PM_RESET_REASON_SW 2U /* Software reset */
  62 +#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */
  63 +#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */
  64 +#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */
  65 +#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */
  66 +#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */
  67 +#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */
  68 +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */
  69 +#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */
  70 +#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */
  71 +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */
  72 +
  73 +/* Defines for sc_pm_sys_if_t */
  74 +#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */
  75 +#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */
  76 +#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */
  77 +#define SC_PM_SYS_IF_DDR 3U /* DDR memory */
  78 +
  79 +/* Defines for sc_pm_wake_src_t */
  80 +#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */
  81 +#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
  82 +#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
  83 +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
  84 +#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */
  85 +/* Types */
  86 +
  87 +/*
  88 + * This type is used to declare a power mode. Note resources only use
  89 + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
  90 + * as system power modes.
  91 + */
45 92 typedef u8 sc_pm_power_mode_t;
  93 +
  94 +/*
  95 + * This type is used to declare a clock.
  96 + */
46 97 typedef u8 sc_pm_clk_t;
  98 +
  99 +/*
  100 + * This type is used to declare a clock mode.
  101 + */
47 102 typedef u8 sc_pm_clk_mode_t;
  103 +
  104 +/*
  105 + * This type is used to declare the clock parent.
  106 + */
48 107 typedef u8 sc_pm_clk_parent_t;
  108 +
  109 +/*
  110 + * This type is used to declare clock rates.
  111 + */
49 112 typedef u32 sc_pm_clock_rate_t;
50 113  
  114 +/*
  115 + * This type is used to declare a desired reset type.
  116 + */
  117 +typedef u8 sc_pm_reset_type_t;
  118 +
  119 +/*
  120 + * This type is used to declare a reason for a reset.
  121 + */
  122 +typedef u8 sc_pm_reset_reason_t;
  123 +
  124 +/*
  125 + * This type is used to specify a system-level interface to be power managed.
  126 + */
  127 +typedef u8 sc_pm_sys_if_t;
  128 +
  129 +/*
  130 + * This type is used to specify a wake source for CPU resources.
  131 + */
  132 +typedef u8 sc_pm_wake_src_t;
51 133 #endif /* SC_PM_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
Diff comments   View file @ 71e4d73
... ... @@ -38,32 +38,36 @@
38 38  
39 39 /* Types */
40 40  
41   -/*!
  41 +/*
42 42 * This type is used to declare a resource partition.
43 43 */
44 44 typedef u8 sc_rm_pt_t;
45 45  
46   -/*!
  46 +/*
47 47 * This type is used to declare a memory region.
48 48 */
49 49 typedef u8 sc_rm_mr_t;
50 50  
51   -/*!
  51 +/*
52 52 * This type is used to declare a resource domain ID used by the
53 53 * isolation HW.
54 54 */
55 55 typedef u8 sc_rm_did_t;
56 56  
57   -/*!
  57 +/*
58 58 * This type is used to declare an SMMU StreamID.
59 59 */
60 60 typedef u16 sc_rm_sid_t;
61 61  
62   -/*!
  62 +/*
63 63 * This type is a used to declare master transaction attributes.
64 64 */
65 65 typedef u8 sc_rm_spa_t;
66 66  
  67 +/*
  68 + * This type is used to declare a resource/memory region access permission.
  69 + * Refer to the XRDC2 Block Guide for more information.
  70 + */
67 71 typedef u8 sc_rm_perm_t;
68 72  
69 73 #endif /* SC_RM_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
Diff comments   View file @ 71e4d73
... ... @@ -17,6 +17,7 @@
17 17 #define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */
18 18 #define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */
19 19 #define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */
  20 +#define SC_SECO_EVERIFY_IMAGE 6U /* Enhanced verify image */
20 21  
21 22 #define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */
22 23 #define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */
23 24  
... ... @@ -24,12 +25,12 @@
24 25  
25 26 /* Types */
26 27  
27   -/*!
  28 +/*
28 29 * This type is used to issue SECO authenticate commands.
29 30 */
30 31 typedef uint8_t sc_seco_auth_cmd_t;
31 32  
32   -/*!
  33 +/*
33 34 * This type is used to return the RNG initialization status.
34 35 */
35 36 typedef uint32_t sc_seco_rng_stat_t;
arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h
Diff comments   View file @ 71e4d73
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018-2019 NXP
  4 + */
  5 +
  6 +
  7 +#ifndef SC_TIMER_API_H
  8 +#define SC_TIMER_API_H
  9 +
  10 +/* Defines */
  11 +
  12 +/* Defines for type widths */
  13 +#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */
  14 +
  15 +/* Defines for sc_timer_wdog_action_t */
  16 +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */
  17 +#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */
  18 +#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */
  19 +#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */
  20 +#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */
  21 +
  22 +/* Types */
  23 +
  24 +/*
  25 + * This type is used to configure the watchdog action.
  26 + */
  27 +typedef u8 sc_timer_wdog_action_t;
  28 +
  29 +/*
  30 + * This type is used to declare a watchdog time value in milliseconds.
  31 + */
  32 +typedef u32 sc_timer_wdog_time_t;
  33 +
  34 +#endif /* SC_TIMER_API_H */
arch/arm/include/asm/arch-imx8/sci/types.h
Diff comments   View file @ 71e4d73
... ... @@ -19,6 +19,7 @@
19 19 /* Defines for common frequencies */
20 20 #define SC_32KHZ 32768U /* 32KHz */
21 21 #define SC_10MHZ 10000000U /* 10MHz */
  22 +#define SC_16MHZ 16000000U /* 16MHz */
22 23 #define SC_20MHZ 20000000U /* 20MHz */
23 24 #define SC_25MHZ 25000000U /* 25MHz */
24 25 #define SC_27MHZ 27000000U /* 27MHz */
25 26  
26 27  
27 28  
28 29  
29 30  
30 31  
... ... @@ -56,21 +57,33 @@
56 57 #define SC_594MHZ 594000000U /* 594MHz */
57 58 #define SC_625MHZ 625000000U /* 625MHz */
58 59 #define SC_640MHZ 640000000U /* 640MHz */
  60 +#define SC_648MHZ 648000000U /* 648MHz */
59 61 #define SC_650MHZ 650000000U /* 650MHz */
60 62 #define SC_667MHZ 666666667U /* 667MHz */
61 63 #define SC_675MHZ 675000000U /* 675MHz */
62 64 #define SC_700MHZ 700000000U /* 700MHz */
63 65 #define SC_720MHZ 720000000U /* 720MHz */
64 66 #define SC_750MHZ 750000000U /* 750MHz */
  67 +#define SC_753MHZ 753000000U /* 753MHz */
  68 +#define SC_793MHZ 793000000U /* 793MHz */
65 69 #define SC_800MHZ 800000000U /* 800MHz */
66 70 #define SC_850MHZ 850000000U /* 850MHz */
  71 +#define SC_858MHZ 858000000U /* 858MHz */
67 72 #define SC_900MHZ 900000000U /* 900MHz */
  73 +#define SC_953MHZ 953000000U /* 953MHz */
  74 +#define SC_963MHZ 963000000U /* 963MHz */
68 75 #define SC_1000MHZ 1000000000U /* 1GHz */
69 76 #define SC_1060MHZ 1060000000U /* 1.06GHz */
  77 +#define SC_1068MHZ 1068000000U /* 1.068GHz */
  78 +#define SC_1121MHZ 1121000000U /* 1.121GHz */
  79 +#define SC_1173MHZ 1173000000U /* 1.173GHz */
70 80 #define SC_1188MHZ 1188000000U /* 1.188GHz */
71 81 #define SC_1260MHZ 1260000000U /* 1.26GHz */
  82 +#define SC_1278MHZ 1278000000U /* 1.278GHz */
72 83 #define SC_1280MHZ 1280000000U /* 1.28GHz */
73 84 #define SC_1300MHZ 1300000000U /* 1.3GHz */
  85 +#define SC_1313MHZ 1313000000U /* 1.313GHz */
  86 +#define SC_1345MHZ 1345000000U /* 1.345GHz */
74 87 #define SC_1400MHZ 1400000000U /* 1.4GHz */
75 88 #define SC_1500MHZ 1500000000U /* 1.5GHz */
76 89 #define SC_1600MHZ 1600000000U /* 1.6GHz */
... ... @@ -113,7 +126,6 @@
113 126 #define SC_755MHZ 755250000U /* 755.25MHz */
114 127  
115 128 /* Defines for type widths */
116   -#define SC_FADDR_W 36U /* Width of sc_faddr_t */
117 129 #define SC_BOOL_W 1U /* Width of sc_bool_t */
118 130 #define SC_ERR_W 4U /* Width of sc_err_t */
119 131 #define SC_RSRC_W 10U /* Width of sc_rsrc_t */
... ... @@ -195,7 +207,9 @@
195 207 #define SC_C_IPG_STOP_MODE 53U
196 208 #define SC_C_IPG_STOP_ACK 54U
197 209 #define SC_C_SYNC_CTRL 55U
198   -#define SC_C_LAST 56U
  210 +#define SC_C_OFS_AUDIO_ALT 56U
  211 +#define SC_C_DSP_BYP 57U
  212 +#define SC_C_LAST 58U
199 213  
200 214  
201 215 #define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */
include/dt-bindings/pinctrl/pads-imx8qxp.h
Diff comments   View file @ 71e4d73
... ... @@ -3,8 +3,8 @@
3 3 * Copyright 2018 NXP
4 4 */
5 5  
6   -#ifndef _SC_PADS_H
7   -#define _SC_PADS_H
  6 +#ifndef SC_PADS_H
  7 +#define SC_PADS_H
8 8  
9 9 #define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
10 10 #define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
... ... @@ -312,7 +312,6 @@
312 312 #define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
313 313 #define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
314 314 #define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
315   -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
316 315 #define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
317 316 #define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
318 317 #define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
... ... @@ -335,7 +334,6 @@
335 334 #define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
336 335 #define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
337 336 #define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
338   -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
339 337 #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
340 338 #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
341 339 #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
... ... @@ -407,7 +405,6 @@
407 405 #define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
408 406 #define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
409 407 #define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
410   -#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
411 408 #define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
412 409 #define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
413 410 #define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
... ... @@ -754,5 +751,23 @@
754 751 #define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
755 752 #define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
756 753  
757   -#endif /* _SC_PADS_H */
  754 +/* Fake Pad Mux Definitions */
  755 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0
  756 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0
  757 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0
  758 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0
  759 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0
  760 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0
  761 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
  762 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
  763 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0
  764 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
  765 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0
  766 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0
  767 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0
  768 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0
  769 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0
  770 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0
  771 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0
  772 +#endif /* SC_PADS_H */
include/dt-bindings/soc/imx_rsrc.h
Diff comments   View file @ 71e4d73
... ... @@ -35,14 +35,14 @@
35 35 #define SC_R_DC_0_BLIT2 21
36 36 #define SC_R_DC_0_BLIT_OUT 22
37 37 #define SC_R_PERF 23
38   -#define SC_R_UNUSED5 24
  38 +#define SC_R_USB_1_PHY 24
39 39 #define SC_R_DC_0_WARP 25
40   -#define SC_R_UNUSED7 26
41   -#define SC_R_UNUSED8 27
  40 +#define SC_R_V2X_MU_0 26
  41 +#define SC_R_V2X_MU_1 27
42 42 #define SC_R_DC_0_VIDEO0 28
43 43 #define SC_R_DC_0_VIDEO1 29
44 44 #define SC_R_DC_0_FRAC0 30
45   -#define SC_R_UNUSED6 31
  45 +#define SC_R_V2X_MU_2 31
46 46 #define SC_R_DC_0 32
47 47 #define SC_R_GPU_2_PID0 33
48 48 #define SC_R_DC_0_PLL_0 34
49 49  
... ... @@ -51,11 +51,11 @@
51 51 #define SC_R_DC_1_BLIT1 37
52 52 #define SC_R_DC_1_BLIT2 38
53 53 #define SC_R_DC_1_BLIT_OUT 39
54   -#define SC_R_UNUSED9 40
55   -#define SC_R_UNUSED10 41
  54 +#define SC_R_V2X_MU_3 40
  55 +#define SC_R_V2X_MU_4 41
56 56 #define SC_R_DC_1_WARP 42
57   -#define SC_R_UNUSED11 43
58   -#define SC_R_UNUSED12 44
  57 +#define SC_R_TBU_CTL 43
  58 +#define SC_R_SECVIO 44
59 59 #define SC_R_DC_1_VIDEO0 45
60 60 #define SC_R_DC_1_VIDEO1 46
61 61 #define SC_R_DC_1_FRAC0 47
... ... @@ -151,10 +151,10 @@
151 151 #define SC_R_DMA_1_CH29 137
152 152 #define SC_R_DMA_1_CH30 138
153 153 #define SC_R_DMA_1_CH31 139
154   -#define SC_R_UNUSED1 140
155   -#define SC_R_UNUSED2 141
156   -#define SC_R_UNUSED3 142
157   -#define SC_R_UNUSED4 143
  154 +#define SC_R_V2X_PID0 140
  155 +#define SC_R_V2X_PID1 141
  156 +#define SC_R_V2X_PID2 142
  157 +#define SC_R_V2X_PID3 143
158 158 #define SC_R_GPU_0_PID0 144
159 159 #define SC_R_GPU_0_PID1 145
160 160 #define SC_R_GPU_0_PID2 146
... ... @@ -301,8 +301,8 @@
301 301 #define SC_R_M4_0_UART 287
302 302 #define SC_R_M4_0_I2C 288
303 303 #define SC_R_M4_0_INTMUX 289
304   -#define SC_R_UNUSED15 290
305   -#define SC_R_UNUSED16 291
  304 +#define SC_R_ENET_0_A0 290
  305 +#define SC_R_ENET_0_A1 291
306 306 #define SC_R_M4_0_MU_0B 292
307 307 #define SC_R_M4_0_MU_0A0 293
308 308 #define SC_R_M4_0_MU_0A1 294
... ... @@ -377,12 +377,12 @@
377 377 #define SC_R_VPU_PID5 363
378 378 #define SC_R_VPU_PID6 364
379 379 #define SC_R_VPU_PID7 365
380   -#define SC_R_VPU_UART 366
381   -#define SC_R_VPUCORE 367
382   -#define SC_R_VPUCORE_0 368
383   -#define SC_R_VPUCORE_1 369
384   -#define SC_R_VPUCORE_2 370
385   -#define SC_R_VPUCORE_3 371
  380 +#define SC_R_ENET_0_A2 366
  381 +#define SC_R_ENET_1_A0 367
  382 +#define SC_R_ENET_1_A1 368
  383 +#define SC_R_ENET_1_A2 369
  384 +#define SC_R_ENET_1_A3 370
  385 +#define SC_R_ENET_1_A4 371
386 386 #define SC_R_DMA_4_CH0 372
387 387 #define SC_R_DMA_4_CH1 373
388 388 #define SC_R_DMA_4_CH2 374
... ... @@ -558,7 +558,6 @@
558 558 #define SC_R_DMA_5_CH3 544
559 559 #define SC_R_ATTESTATION 545
560 560 #define SC_R_LAST 546
561   -
562 561 #define SC_R_NONE 0xFFF0
563 562  
564 563 #endif /* DT_BINDINGS_RSCRC_IMX_H */