From 7499ae1d3ce97ceecd9ad9d050953ceee055fea8 Mon Sep 17 00:00:00 2001 From: Eric Lee Date: Thu, 8 Apr 2021 13:34:56 +0800 Subject: [PATCH] Make changes for hardware rev. 00E0 --- arch/arm/dts/fsl-smarcimx8mq.dts | 13 +++++++------ board/embedian/smarcimx8mq/smarcimx8mq.c | 8 +++++--- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/fsl-smarcimx8mq.dts b/arch/arm/dts/fsl-smarcimx8mq.dts index 8485d5f..77f5819 100644 --- a/arch/arm/dts/fsl-smarcimx8mq.dts +++ b/arch/arm/dts/fsl-smarcimx8mq.dts @@ -152,8 +152,8 @@ fsl,pins = < MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79 - MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */ - MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */ + MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x79 /* RTS */ + MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x79 /* CTS */ >; }; @@ -167,8 +167,10 @@ pinctrl_uart4: uart4grp { fsl,pins = < - MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79 - MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79 + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x79 + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x79 + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x79 /* RTS */ + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x79 /* CTS */ >; }; @@ -393,7 +395,6 @@ vgen6_reg: vgen6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; }; }; @@ -584,7 +585,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; status = "okay"; }; diff --git a/board/embedian/smarcimx8mq/smarcimx8mq.c b/board/embedian/smarcimx8mq/smarcimx8mq.c index 91df5b6..c3d82b6 100644 --- a/board/embedian/smarcimx8mq/smarcimx8mq.c +++ b/board/embedian/smarcimx8mq/smarcimx8mq.c @@ -80,6 +80,8 @@ static iomux_v3_cfg_t const uart1_pads[] = { static iomux_v3_cfg_t const uart2_pads[] = { IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART4_TXD__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART4_RXD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), }; #endif @@ -92,10 +94,10 @@ static iomux_v3_cfg_t const uart3_pads[] = { #ifdef CONFIG_CONSOLE_SER0 static iomux_v3_cfg_t const uart4_pads[] = { - IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; #endif @@ -116,7 +118,7 @@ static iomux_v3_cfg_t const misc_pads[] = { IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE*/ IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /*S148, LID#*/ IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), /*S149, SLEEP#*/ - IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/ + IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/ IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*S152, CHARGER_PRSNT#*/ IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /*S153, CARRIER_STBY#*/ IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*S156, BATLOW#*/ -- 1.9.1