Eric Lee / smarc-uboot | Embedian Git Server

Commit 75d3e8fbd93c14d9929d024c75af2d742c76db70

Authored by Marian Balakowicz 2008-02-22 00:20:18 +0800

Exists in master and in 55 other branches

[new uImage] Pull in libfdt if CONFIG_FIT is enabled

New uImage format (Flattened Image Tree) requires libfdt
functionality, print out error message if CONFIG_OF_LIBFDT
is not defined.

New uImage support is enabled by defining CONFIG_FIT (and CONFIG_OF_LIBFDT).
This commit turns it on by default.

Signed-off-by: Marian Balakowicz <m8@semihalf.com>

Showing 4 changed files with 12 additions and 3 deletions Inline Diff

cpu/mpc5xxx/cpu.c
cpu/mpc8260/cpu.c
cpu/mpc8xx/cpu.c
include/image.h

cpu/mpc5xxx/cpu.c

Diff comments View file @ 75d3e8f

1	/*	1	/*
2	* (C) Copyright 2000-2003	2	* (C) Copyright 2000-2003
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License as	9	* modify it under the terms of the GNU General Public License as
10	* published by the Free Software Foundation; either version 2 of	10	* published by the Free Software Foundation; either version 2 of
11	* the License, or (at your option) any later version.	11	* the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* You should have received a copy of the GNU General Public License	18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software	19	* along with this program; if not, write to the Free Software
20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	* MA 02111-1307 USA	21	* MA 02111-1307 USA
22	*/	22	*/
23		23
24	/*	24	/*
25	* CPU specific code for the MPC5xxx CPUs	25	* CPU specific code for the MPC5xxx CPUs
26	*/	26	*/
27		27
28	#include <common.h>	28	#include <common.h>
29	#include <watchdog.h>	29	#include <watchdog.h>
30	#include <command.h>	30	#include <command.h>
31	#include <mpc5xxx.h>	31	#include <mpc5xxx.h>
32	#include <asm/io.h>	32	#include <asm/io.h>
33	#include <asm/processor.h>	33	#include <asm/processor.h>
34		34
35	#if defined(CONFIG_OF_LIBFDT)	35	#if defined(CONFIG_OF_LIBFDT)
36	#include <libfdt.h>	36	#include <libfdt.h>
37	#include <libfdt_env.h>	37	#include <libfdt_env.h>
38	#include <fdt_support.h>	38	#include <fdt_support.h>
39	#endif	39	#endif
40		40
41	DECLARE_GLOBAL_DATA_PTR;	41	DECLARE_GLOBAL_DATA_PTR;
42		42
43	int checkcpu (void)	43	int checkcpu (void)
44	{	44	{
45	ulong clock = gd->cpu_clk;	45	ulong clock = gd->cpu_clk;
46	char buf[32];	46	char buf[32];
47	#ifndef CONFIG_MGT5100	47	#ifndef CONFIG_MGT5100
48	uint svr, pvr;	48	uint svr, pvr;
49	#endif	49	#endif
50		50
51	puts ("CPU: ");	51	puts ("CPU: ");
52		52
53	#ifdef CONFIG_MGT5100	53	#ifdef CONFIG_MGT5100
54	puts (CPU_ID_STR);	54	puts (CPU_ID_STR);
55	printf (" (JTAG ID %08lx)", (vu_long )MPC5XXX_CDM_JTAGID);	55	printf (" (JTAG ID %08lx)", (vu_long )MPC5XXX_CDM_JTAGID);
56	#else	56	#else
57	svr = get_svr();	57	svr = get_svr();
58	pvr = get_pvr();	58	pvr = get_pvr();
59		59
60	switch (pvr) {	60	switch (pvr) {
61	case PVR_5200:	61	case PVR_5200:
62	printf("MPC5200");	62	printf("MPC5200");
63	break;	63	break;
64	case PVR_5200B:	64	case PVR_5200B:
65	printf("MPC5200B");	65	printf("MPC5200B");
66	break;	66	break;
67	default:	67	default:
68	printf("Unknown MPC5xxx");	68	printf("Unknown MPC5xxx");
69	break;	69	break;
70	}	70	}
71		71
72	printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),	72	printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
73	PVR_MAJ(pvr), PVR_MIN(pvr));	73	PVR_MAJ(pvr), PVR_MIN(pvr));
74	#endif	74	#endif
75	printf (" at %s MHz\n", strmhz (buf, clock));	75	printf (" at %s MHz\n", strmhz (buf, clock));
76	return 0;	76	return 0;
77	}	77	}
78		78
79	/* ------------------------------------------------------------------------- */	79	/* ------------------------------------------------------------------------- */
80		80
81	int	81	int
82	do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])	82	do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
83	{	83	{
84	ulong msr;	84	ulong msr;
85	/* Interrupts and MMU off */	85	/* Interrupts and MMU off */
86	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);	86	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
87		87
88	msr &= ~(MSR_ME \| MSR_EE \| MSR_IR \| MSR_DR);	88	msr &= ~(MSR_ME \| MSR_EE \| MSR_IR \| MSR_DR);
89	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));	89	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
90		90
91	/* Charge the watchdog timer */	91	/* Charge the watchdog timer */
92	(vu_long )(MPC5XXX_GPT0_COUNTER) = 0x0001000f;	92	(vu_long )(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
93	(vu_long )(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden\|ce\|timer_ms */	93	(vu_long )(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden\|ce\|timer_ms */
94	while(1);	94	while(1);
95		95
96	return 1;	96	return 1;
97		97
98	}	98	}
99		99
100	/* ------------------------------------------------------------------------- */	100	/* ------------------------------------------------------------------------- */
101		101
102	/*	102	/*
103	* Get timebase clock frequency (like cpu_clk in Hz)	103	* Get timebase clock frequency (like cpu_clk in Hz)
104	*	104	*
105	*/	105	*/
106	unsigned long get_tbclk (void)	106	unsigned long get_tbclk (void)
107	{	107	{
108	ulong tbclk;	108	ulong tbclk;
109		109
110	tbclk = (gd->bus_clk + 3L) / 4L;	110	tbclk = (gd->bus_clk + 3L) / 4L;
111		111
112	return (tbclk);	112	return (tbclk);
113	}	113	}
114		114
115	/* ------------------------------------------------------------------------- */	115	/* ------------------------------------------------------------------------- */
116		116
117	#ifdef CONFIG_OF_LIBFDT	117	#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
118	void ft_cpu_setup(void blob, bd_t bd)	118	void ft_cpu_setup(void blob, bd_t bd)
119	{	119	{
120	int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;	120	int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
121	char * cpu_path = "/cpus/" OF_CPU;	121	char * cpu_path = "/cpus/" OF_CPU;
122	char * eth_path = "/" OF_SOC "/ethernet@3000";	122	char * eth_path = "/" OF_SOC "/ethernet@3000";
123		123
124	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);	124	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
125	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);	125	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
126	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);	126	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
127	do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);	127	do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
128	do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",	128	do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
129	bd->bi_busfreq*div, 1);	129	bd->bi_busfreq*div, 1);
130	do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);	130	do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);
131	do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);	131	do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
132	}	132	}
133	#endif	133	#endif
134		134

cpu/mpc8260/cpu.c

Diff comments View file @ 75d3e8f

1	/*	1	/*
2	* (C) Copyright 2000-2006	2	* (C) Copyright 2000-2006
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License as	9	* modify it under the terms of the GNU General Public License as
10	* published by the Free Software Foundation; either version 2 of	10	* published by the Free Software Foundation; either version 2 of
11	* the License, or (at your option) any later version.	11	* the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* You should have received a copy of the GNU General Public License	18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software	19	* along with this program; if not, write to the Free Software
20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	* MA 02111-1307 USA	21	* MA 02111-1307 USA
22	*/	22	*/
23		23
24	/*	24	/*
25	* CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x	25	* CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
26	*	26	*
27	* written or collected and sometimes rewritten by	27	* written or collected and sometimes rewritten by
28	* Magnus Damm <damm@bitsmart.com>	28	* Magnus Damm <damm@bitsmart.com>
29	*	29	*
30	* modified by	30	* modified by
31	* Wolfgang Denk <wd@denx.de>	31	* Wolfgang Denk <wd@denx.de>
32	*	32	*
33	* modified for 8260 by	33	* modified for 8260 by
34	* Murray Jensen <Murray.Jensen@cmst.csiro.au>	34	* Murray Jensen <Murray.Jensen@cmst.csiro.au>
35	*	35	*
36	* added 8260 masks by	36	* added 8260 masks by
37	* Marius Groeger <mag@sysgo.de>	37	* Marius Groeger <mag@sysgo.de>
38	*	38	*
39	* added HiP7 (824x/827x/8280) processors support by	39	* added HiP7 (824x/827x/8280) processors support by
40	* Yuli Barcohen <yuli@arabellasw.com>	40	* Yuli Barcohen <yuli@arabellasw.com>
41	*/	41	*/
42		42
43	#include <common.h>	43	#include <common.h>
44	#include <watchdog.h>	44	#include <watchdog.h>
45	#include <command.h>	45	#include <command.h>
46	#include <mpc8260.h>	46	#include <mpc8260.h>
47	#include <asm/processor.h>	47	#include <asm/processor.h>
48	#include <asm/cpm_8260.h>	48	#include <asm/cpm_8260.h>
49		49
50	#if defined(CONFIG_OF_LIBFDT)	50	#if defined(CONFIG_OF_LIBFDT)
51	#include <libfdt.h>	51	#include <libfdt.h>
52	#include <libfdt_env.h>	52	#include <libfdt_env.h>
53	#include <fdt_support.h>	53	#include <fdt_support.h>
54	#endif	54	#endif
55		55
56	DECLARE_GLOBAL_DATA_PTR;	56	DECLARE_GLOBAL_DATA_PTR;
57		57
58	#if defined(CONFIG_GET_CPU_STR_F)	58	#if defined(CONFIG_GET_CPU_STR_F)
59	extern int get_cpu_str_f (char *buf);	59	extern int get_cpu_str_f (char *buf);
60	#endif	60	#endif
61		61
62	int checkcpu (void)	62	int checkcpu (void)
63	{	63	{
64	volatile immap_t immap = (immap_t ) CFG_IMMR;	64	volatile immap_t immap = (immap_t ) CFG_IMMR;
65	ulong clock = gd->cpu_clk;	65	ulong clock = gd->cpu_clk;
66	uint pvr = get_pvr ();	66	uint pvr = get_pvr ();
67	uint immr, rev, m, k;	67	uint immr, rev, m, k;
68	char buf[32];	68	char buf[32];
69		69
70	puts ("CPU: ");	70	puts ("CPU: ");
71		71
72	switch (pvr) {	72	switch (pvr) {
73	case PVR_8260:	73	case PVR_8260:
74	case PVR_8260_HIP3:	74	case PVR_8260_HIP3:
75	k = 3;	75	k = 3;
76	break;	76	break;
77	case PVR_8260_HIP4:	77	case PVR_8260_HIP4:
78	k = 4;	78	k = 4;
79	break;	79	break;
80	case PVR_8260_HIP7R1:	80	case PVR_8260_HIP7R1:
81	case PVR_8260_HIP7RA:	81	case PVR_8260_HIP7RA:
82	case PVR_8260_HIP7:	82	case PVR_8260_HIP7:
83	k = 7;	83	k = 7;
84	break;	84	break;
85	default:	85	default:
86	return -1; /* whoops! not an MPC8260 */	86	return -1; /* whoops! not an MPC8260 */
87	}	87	}
88	rev = pvr & 0xff;	88	rev = pvr & 0xff;
89		89
90	immr = immap->im_memctl.memc_immr;	90	immr = immap->im_memctl.memc_immr;
91	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)	91	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
92	return -1; /* whoops! someone moved the IMMR */	92	return -1; /* whoops! someone moved the IMMR */
93		93
94	#if defined(CONFIG_GET_CPU_STR_F)	94	#if defined(CONFIG_GET_CPU_STR_F)
95	get_cpu_str_f (buf);	95	get_cpu_str_f (buf);
96	printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);	96	printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
97	#else	97	#else
98	printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);	98	printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
99	#endif	99	#endif
100		100
101	/*	101	/*
102	* the bottom 16 bits of the immr are the Part Number and Mask Number	102	* the bottom 16 bits of the immr are the Part Number and Mask Number
103	* (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the	103	* (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
104	* RISC Microcode Revision Number (13-10).	104	* RISC Microcode Revision Number (13-10).
105	* For the 8260, Motorola doesn't include the Microcode Revision	105	* For the 8260, Motorola doesn't include the Microcode Revision
106	* in the mask.	106	* in the mask.
107	*/	107	*/
108	m = immr & (IMMR_PARTNUM_MSK \| IMMR_MASKNUM_MSK);	108	m = immr & (IMMR_PARTNUM_MSK \| IMMR_MASKNUM_MSK);
109	k = ((ushort ) & immap->im_dprambase[PROFF_REVNUM]);	109	k = ((ushort ) & immap->im_dprambase[PROFF_REVNUM]);
110		110
111	switch (m) {	111	switch (m) {
112	case 0x0000:	112	case 0x0000:
113	puts ("0.2 2J24M");	113	puts ("0.2 2J24M");
114	break;	114	break;
115	case 0x0010:	115	case 0x0010:
116	puts ("A.0 K22A");	116	puts ("A.0 K22A");
117	break;	117	break;
118	case 0x0011:	118	case 0x0011:
119	puts ("A.1 1K22A-XC");	119	puts ("A.1 1K22A-XC");
120	break;	120	break;
121	case 0x0001:	121	case 0x0001:
122	puts ("B.1 1K23A");	122	puts ("B.1 1K23A");
123	break;	123	break;
124	case 0x0021:	124	case 0x0021:
125	puts ("B.2 2K23A-XC");	125	puts ("B.2 2K23A-XC");
126	break;	126	break;
127	case 0x0023:	127	case 0x0023:
128	puts ("B.3 3K23A");	128	puts ("B.3 3K23A");
129	break;	129	break;
130	case 0x0024:	130	case 0x0024:
131	puts ("C.2 6K23A");	131	puts ("C.2 6K23A");
132	break;	132	break;
133	case 0x0060:	133	case 0x0060:
134	puts ("A.0(A) 2K25A");	134	puts ("A.0(A) 2K25A");
135	break;	135	break;
136	case 0x0062:	136	case 0x0062:
137	puts ("B.1 4K25A");	137	puts ("B.1 4K25A");
138	break;	138	break;
139	case 0x0064:	139	case 0x0064:
140	puts ("C.0 5K25A");	140	puts ("C.0 5K25A");
141	break;	141	break;
142	case 0x0A00:	142	case 0x0A00:
143	puts ("0.0 0K49M");	143	puts ("0.0 0K49M");
144	break;	144	break;
145	case 0x0A01:	145	case 0x0A01:
146	puts ("0.1 1K49M");	146	puts ("0.1 1K49M");
147	break;	147	break;
148	case 0x0A10:	148	case 0x0A10:
149	puts ("1.0 1K49M");	149	puts ("1.0 1K49M");
150	break;	150	break;
151	case 0x0C00:	151	case 0x0C00:
152	puts ("0.0 0K50M");	152	puts ("0.0 0K50M");
153	break;	153	break;
154	case 0x0C10:	154	case 0x0C10:
155	puts ("1.0 1K50M");	155	puts ("1.0 1K50M");
156	break;	156	break;
157	case 0x0D00:	157	case 0x0D00:
158	puts ("0.0 0K50M");	158	puts ("0.0 0K50M");
159	break;	159	break;
160	case 0x0D10:	160	case 0x0D10:
161	puts ("1.0 1K50M");	161	puts ("1.0 1K50M");
162	break;	162	break;
163	default:	163	default:
164	printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);	164	printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
165	break;	165	break;
166	}	166	}
167		167
168	printf (") at %s MHz\n", strmhz (buf, clock));	168	printf (") at %s MHz\n", strmhz (buf, clock));
169		169
170	return 0;	170	return 0;
171	}	171	}
172		172
173	/* ------------------------------------------------------------------------- */	173	/* ------------------------------------------------------------------------- */
174	/* configures a UPM by writing into the UPM RAM array */	174	/* configures a UPM by writing into the UPM RAM array */
175	/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */	175	/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
176	/* NOTE: the physical address chosen must not overlap into any other area */	176	/* NOTE: the physical address chosen must not overlap into any other area */
177	/* mapped by the memory controller because bank 11 has the lowest priority */	177	/* mapped by the memory controller because bank 11 has the lowest priority */
178		178
179	void upmconfig (uint upm, uint * table, uint size)	179	void upmconfig (uint upm, uint * table, uint size)
180	{	180	{
181	volatile immap_t immap = (immap_t ) CFG_IMMR;	181	volatile immap_t immap = (immap_t ) CFG_IMMR;
182	volatile memctl8260_t *memctl = &immap->im_memctl;	182	volatile memctl8260_t *memctl = &immap->im_memctl;
183	volatile uchar dummy = (uchar ) BRx_BA_MSK; /* set all BA bits */	183	volatile uchar dummy = (uchar ) BRx_BA_MSK; /* set all BA bits */
184	uint i;	184	uint i;
185		185
186	/* first set up bank 11 to reference the correct UPM at a dummy address */	186	/* first set up bank 11 to reference the correct UPM at a dummy address */
187		187
188	memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */	188	memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
189		189
190	switch (upm) {	190	switch (upm) {
191		191
192	case UPMA:	192	case UPMA:
193	memctl->memc_br11 =	193	memctl->memc_br11 =
194	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMA \|	194	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMA \|
195	BRx_V;	195	BRx_V;
196	memctl->memc_mamr = MxMR_OP_WARR;	196	memctl->memc_mamr = MxMR_OP_WARR;
197	break;	197	break;
198		198
199	case UPMB:	199	case UPMB:
200	memctl->memc_br11 =	200	memctl->memc_br11 =
201	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMB \|	201	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMB \|
202	BRx_V;	202	BRx_V;
203	memctl->memc_mbmr = MxMR_OP_WARR;	203	memctl->memc_mbmr = MxMR_OP_WARR;
204	break;	204	break;
205		205
206	case UPMC:	206	case UPMC:
207	memctl->memc_br11 =	207	memctl->memc_br11 =
208	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMC \|	208	((uint)dummy & BRx_BA_MSK) \| BRx_PS_32 \| BRx_MS_UPMC \|
209	BRx_V;	209	BRx_V;
210	memctl->memc_mcmr = MxMR_OP_WARR;	210	memctl->memc_mcmr = MxMR_OP_WARR;
211	break;	211	break;
212		212
213	default:	213	default:
214	panic ("upmconfig passed invalid UPM number (%u)\n", upm);	214	panic ("upmconfig passed invalid UPM number (%u)\n", upm);
215	break;	215	break;
216		216
217	}	217	}
218		218
219	/*	219	/*
220	* at this point, the dummy address is set up to access the selected UPM,	220	* at this point, the dummy address is set up to access the selected UPM,
221	* the MAD pointer is zero, and the MxMR OP is set for writing to RAM	221	* the MAD pointer is zero, and the MxMR OP is set for writing to RAM
222	*	222	*
223	* now we simply load the mdr with each word and poke the dummy address.	223	* now we simply load the mdr with each word and poke the dummy address.
224	* the MAD is incremented on each access.	224	* the MAD is incremented on each access.
225	*/	225	*/
226		226
227	for (i = 0; i < size; i++) {	227	for (i = 0; i < size; i++) {
228	memctl->memc_mdr = table[i];	228	memctl->memc_mdr = table[i];
229	*dummy = 0;	229	*dummy = 0;
230	}	230	}
231		231
232	/* now kill bank 11 */	232	/* now kill bank 11 */
233	memctl->memc_br11 = 0;	233	memctl->memc_br11 = 0;
234	}	234	}
235		235
236	/* ------------------------------------------------------------------------- */	236	/* ------------------------------------------------------------------------- */
237		237
238	#if !defined(CONFIG_HAVE_OWN_RESET)	238	#if !defined(CONFIG_HAVE_OWN_RESET)
239	int	239	int
240	do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])	240	do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
241	{	241	{
242	ulong msr, addr;	242	ulong msr, addr;
243		243
244	volatile immap_t immap = (immap_t ) CFG_IMMR;	244	volatile immap_t immap = (immap_t ) CFG_IMMR;
245		245
246	immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */	246	immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
247		247
248	/* Interrupts and MMU off */	248	/* Interrupts and MMU off */
249	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);	249	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
250		250
251	msr &= ~(MSR_ME \| MSR_EE \| MSR_IR \| MSR_DR);	251	msr &= ~(MSR_ME \| MSR_EE \| MSR_IR \| MSR_DR);
252	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));	252	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
253		253
254	/*	254	/*
255	* Trying to execute the next instruction at a non-existing address	255	* Trying to execute the next instruction at a non-existing address
256	* should cause a machine check, resulting in reset	256	* should cause a machine check, resulting in reset
257	*/	257	*/
258	#ifdef CFG_RESET_ADDRESS	258	#ifdef CFG_RESET_ADDRESS
259	addr = CFG_RESET_ADDRESS;	259	addr = CFG_RESET_ADDRESS;
260	#else	260	#else
261	/*	261	/*
262	* note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE	262	* note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
263	* - sizeof (ulong) is usually a valid address. Better pick an address	263	* - sizeof (ulong) is usually a valid address. Better pick an address
264	* known to be invalid on your system and assign it to CFG_RESET_ADDRESS.	264	* known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
265	*/	265	*/
266	addr = CFG_MONITOR_BASE - sizeof (ulong);	266	addr = CFG_MONITOR_BASE - sizeof (ulong);
267	#endif	267	#endif
268	((void (*)(void)) addr) ();	268	((void (*)(void)) addr) ();
269	return 1;	269	return 1;
270		270
271	}	271	}
272	#endif /* CONFIG_HAVE_OWN_RESET */	272	#endif /* CONFIG_HAVE_OWN_RESET */
273		273
274	/* ------------------------------------------------------------------------- */	274	/* ------------------------------------------------------------------------- */
275		275
276	/*	276	/*
277	* Get timebase clock frequency (like cpu_clk in Hz)	277	* Get timebase clock frequency (like cpu_clk in Hz)
278	*	278	*
279	*/	279	*/
280	unsigned long get_tbclk (void)	280	unsigned long get_tbclk (void)
281	{	281	{
282	ulong tbclk;	282	ulong tbclk;
283		283
284	tbclk = (gd->bus_clk + 3L) / 4L;	284	tbclk = (gd->bus_clk + 3L) / 4L;
285		285
286	return (tbclk);	286	return (tbclk);
287	}	287	}
288		288
289	/* ------------------------------------------------------------------------- */	289	/* ------------------------------------------------------------------------- */
290		290
291	#if defined(CONFIG_WATCHDOG)	291	#if defined(CONFIG_WATCHDOG)
292	void watchdog_reset (void)	292	void watchdog_reset (void)
293	{	293	{
294	int re_enable = disable_interrupts ();	294	int re_enable = disable_interrupts ();
295		295
296	reset_8260_watchdog ((immap_t *) CFG_IMMR);	296	reset_8260_watchdog ((immap_t *) CFG_IMMR);
297	if (re_enable)	297	if (re_enable)
298	enable_interrupts ();	298	enable_interrupts ();
299	}	299	}
300	#endif /* CONFIG_WATCHDOG */	300	#endif /* CONFIG_WATCHDOG */
301		301
302	/* ------------------------------------------------------------------------- */	302	/* ------------------------------------------------------------------------- */
303	#if defined(CONFIG_OF_LIBFDT)	303	#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
304	void ft_cpu_setup (void blob, bd_t bd)	304	void ft_cpu_setup (void blob, bd_t bd)
305	{	305	{
306	char * cpu_path = "/cpus/" OF_CPU;	306	char * cpu_path = "/cpus/" OF_CPU;
307		307
308	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);	308	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
309	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);	309	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
310	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);	310	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
311	}	311	}
312	#endif /* CONFIG_OF_LIBFDT */	312	#endif /* CONFIG_OF_LIBFDT */
313		313

cpu/mpc8xx/cpu.c

Diff comments View file @ 75d3e8f

1	/*	1	/*
2	* (C) Copyright 2000-2002	2	* (C) Copyright 2000-2002
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License as	9	* modify it under the terms of the GNU General Public License as
10	* published by the Free Software Foundation; either version 2 of	10	* published by the Free Software Foundation; either version 2 of
11	* the License, or (at your option) any later version.	11	* the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* You should have received a copy of the GNU General Public License	18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software	19	* along with this program; if not, write to the Free Software
20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	* MA 02111-1307 USA	21	* MA 02111-1307 USA
22	*/	22	*/
23		23
24	/*	24	/*
25	* m8xx.c	25	* m8xx.c
26	*	26	*
27	* CPU specific code	27	* CPU specific code
28	*	28	*
29	* written or collected and sometimes rewritten by	29	* written or collected and sometimes rewritten by
30	* Magnus Damm <damm@bitsmart.com>	30	* Magnus Damm <damm@bitsmart.com>
31	*	31	*
32	* minor modifications by	32	* minor modifications by
33	* Wolfgang Denk <wd@denx.de>	33	* Wolfgang Denk <wd@denx.de>
34	*/	34	*/
35		35
36	#include <common.h>	36	#include <common.h>
37	#include <watchdog.h>	37	#include <watchdog.h>
38	#include <command.h>	38	#include <command.h>
39	#include <mpc8xx.h>	39	#include <mpc8xx.h>
40	#include <asm/cache.h>	40	#include <asm/cache.h>
41		41
42	#if defined(CONFIG_OF_LIBFDT)	42	#if defined(CONFIG_OF_LIBFDT)
43	#include <libfdt.h>	43	#include <libfdt.h>
44	#include <libfdt_env.h>	44	#include <libfdt_env.h>
45	#include <fdt_support.h>	45	#include <fdt_support.h>
46	#endif	46	#endif
47		47
48	DECLARE_GLOBAL_DATA_PTR;	48	DECLARE_GLOBAL_DATA_PTR;
49		49
50	static char *cpu_warning = "\n " \	50	static char *cpu_warning = "\n " \
51	"* Warning: CPU Core has Silicon Bugs -- Check the Errata *";	51	"* Warning: CPU Core has Silicon Bugs -- Check the Errata *";
52		52
53	#if ((defined(CONFIG_MPC86x) \|\| defined(CONFIG_MPC855)) && \	53	#if ((defined(CONFIG_MPC86x) \|\| defined(CONFIG_MPC855)) && \
54	!defined(CONFIG_MPC862))	54	!defined(CONFIG_MPC862))
55		55
56	static int check_CPU (long clock, uint pvr, uint immr)	56	static int check_CPU (long clock, uint pvr, uint immr)
57	{	57	{
58	char *id_str =	58	char *id_str =
59	# if defined(CONFIG_MPC855)	59	# if defined(CONFIG_MPC855)
60	"PC855";	60	"PC855";
61	# elif defined(CONFIG_MPC860P)	61	# elif defined(CONFIG_MPC860P)
62	"PC860P";	62	"PC860P";
63	# else	63	# else
64	NULL;	64	NULL;
65	# endif	65	# endif
66	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);	66	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
67	uint k, m;	67	uint k, m;
68	char buf[32];	68	char buf[32];
69	char pre = 'X';	69	char pre = 'X';
70	char *mid = "xx";	70	char *mid = "xx";
71	char *suf;	71	char *suf;
72		72
73	/* the highest 16 bits should be 0x0050 for a 860 */	73	/* the highest 16 bits should be 0x0050 for a 860 */
74		74
75	if ((pvr >> 16) != 0x0050)	75	if ((pvr >> 16) != 0x0050)
76	return -1;	76	return -1;
77		77
78	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);	78	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
79	m = 0;	79	m = 0;
80	suf = "";	80	suf = "";
81		81
82	/*	82	/*
83	* Some boards use sockets so different CPUs can be used.	83	* Some boards use sockets so different CPUs can be used.
84	* We have to check chip version in run time.	84	* We have to check chip version in run time.
85	*/	85	*/
86	switch (k) {	86	switch (k) {
87	case 0x00020001: pre = 'P'; break;	87	case 0x00020001: pre = 'P'; break;
88	case 0x00030001: break;	88	case 0x00030001: break;
89	case 0x00120003: suf = "A"; break;	89	case 0x00120003: suf = "A"; break;
90	case 0x00130003: suf = "A3"; break;	90	case 0x00130003: suf = "A3"; break;
91		91
92	case 0x00200004: suf = "B"; break;	92	case 0x00200004: suf = "B"; break;
93		93
94	case 0x00300004: suf = "C"; break;	94	case 0x00300004: suf = "C"; break;
95	case 0x00310004: suf = "C1"; m = 1; break;	95	case 0x00310004: suf = "C1"; m = 1; break;
96		96
97	case 0x00200064: mid = "SR"; suf = "B"; break;	97	case 0x00200064: mid = "SR"; suf = "B"; break;
98	case 0x00300065: mid = "SR"; suf = "C"; break;	98	case 0x00300065: mid = "SR"; suf = "C"; break;
99	case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;	99	case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
100	case 0x05010000: suf = "D3"; m = 1; break;	100	case 0x05010000: suf = "D3"; m = 1; break;
101	case 0x05020000: suf = "D4"; m = 1; break;	101	case 0x05020000: suf = "D4"; m = 1; break;
102	/* this value is not documented anywhere */	102	/* this value is not documented anywhere */
103	case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;	103	case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
104	/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */	104	/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
105	case 0x08010004: /* Rev. A.0 */	105	case 0x08010004: /* Rev. A.0 */
106	suf = "A";	106	suf = "A";
107	/* fall through */	107	/* fall through */
108	case 0x08000003: /* Rev. 0.3 */	108	case 0x08000003: /* Rev. 0.3 */
109	pre = 'M'; m = 1;	109	pre = 'M'; m = 1;
110	if (id_str == NULL)	110	if (id_str == NULL)
111	id_str =	111	id_str =
112	# if defined(CONFIG_MPC852T)	112	# if defined(CONFIG_MPC852T)
113	"PC852T";	113	"PC852T";
114	# elif defined(CONFIG_MPC859T)	114	# elif defined(CONFIG_MPC859T)
115	"PC859T";	115	"PC859T";
116	# elif defined(CONFIG_MPC859DSL)	116	# elif defined(CONFIG_MPC859DSL)
117	"PC859DSL";	117	"PC859DSL";
118	# elif defined(CONFIG_MPC866T)	118	# elif defined(CONFIG_MPC866T)
119	"PC866T";	119	"PC866T";
120	# else	120	# else
121	"PC866x"; /* Unknown chip from MPC866 family */	121	"PC866x"; /* Unknown chip from MPC866 family */
122	# endif	122	# endif
123	break;	123	break;
124	case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;	124	case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
125	if (id_str == NULL)	125	if (id_str == NULL)
126	id_str = "PC885"; /* 870/875/880/885 */	126	id_str = "PC885"; /* 870/875/880/885 */
127	break;	127	break;
128		128
129	default: suf = NULL; break;	129	default: suf = NULL; break;
130	}	130	}
131		131
132	if (id_str == NULL)	132	if (id_str == NULL)
133	id_str = "PC86x"; /* Unknown 86x chip */	133	id_str = "PC86x"; /* Unknown 86x chip */
134	if (suf)	134	if (suf)
135	printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);	135	printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
136	else	136	else
137	printf ("unknown M%s (0x%08x)", id_str, k);	137	printf ("unknown M%s (0x%08x)", id_str, k);
138		138
139		139
140	#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)	140	#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
141	printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",	141	printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
142	strmhz (buf, clock),	142	strmhz (buf, clock),
143	CFG_8xx_CPUCLK_MIN / 1000000,	143	CFG_8xx_CPUCLK_MIN / 1000000,
144	((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,	144	((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
145	CFG_8xx_CPUCLK_MAX / 1000000,	145	CFG_8xx_CPUCLK_MAX / 1000000,
146	((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000	146	((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
147	);	147	);
148	#else	148	#else
149	printf (" at %s MHz: ", strmhz (buf, clock));	149	printf (" at %s MHz: ", strmhz (buf, clock));
150	#endif	150	#endif
151	printf ("%u kB I-Cache %u kB D-Cache",	151	printf ("%u kB I-Cache %u kB D-Cache",
152	checkicache () >> 10,	152	checkicache () >> 10,
153	checkdcache () >> 10	153	checkdcache () >> 10
154	);	154	);
155		155
156	/* do we have a FEC (860T/P or 852/859/866/885)? */	156	/* do we have a FEC (860T/P or 852/859/866/885)? */
157		157
158	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;	158	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
159	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {	159	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
160	printf (" FEC present");	160	printf (" FEC present");
161	}	161	}
162		162
163	if (!m) {	163	if (!m) {
164	puts (cpu_warning);	164	puts (cpu_warning);
165	}	165	}
166		166
167	putc ('\n');	167	putc ('\n');
168		168
169	#ifdef DEBUG	169	#ifdef DEBUG
170	if(clock != measure_gclk()) {	170	if(clock != measure_gclk()) {
171	printf ("clock %ldHz != %dHz\n", clock, measure_gclk());	171	printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
172	}	172	}
173	#endif	173	#endif
174		174
175	return 0;	175	return 0;
176	}	176	}
177		177
178	#elif defined(CONFIG_MPC862)	178	#elif defined(CONFIG_MPC862)
179		179
180	static int check_CPU (long clock, uint pvr, uint immr)	180	static int check_CPU (long clock, uint pvr, uint immr)
181	{	181	{
182	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);	182	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
183	uint k, m;	183	uint k, m;
184	char buf[32];	184	char buf[32];
185	char pre = 'X';	185	char pre = 'X';
186	char *mid = "xx";	186	char *mid = "xx";
187	char *suf;	187	char *suf;
188		188
189	/* the highest 16 bits should be 0x0050 for a 8xx */	189	/* the highest 16 bits should be 0x0050 for a 8xx */
190		190
191	if ((pvr >> 16) != 0x0050)	191	if ((pvr >> 16) != 0x0050)
192	return -1;	192	return -1;
193		193
194	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);	194	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
195	m = 0;	195	m = 0;
196		196
197	switch (k) {	197	switch (k) {
198		198
199	/* this value is not documented anywhere */	199	/* this value is not documented anywhere */
200	case 0x06000000: mid = "P"; suf = "0"; break;	200	case 0x06000000: mid = "P"; suf = "0"; break;
201	case 0x06010001: mid = "P"; suf = "A"; m = 1; break;	201	case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
202	case 0x07000003: mid = "P"; suf = "B"; m = 1; break;	202	case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
203	default: suf = NULL; break;	203	default: suf = NULL; break;
204	}	204	}
205		205
206	#ifndef CONFIG_MPC857	206	#ifndef CONFIG_MPC857
207	if (suf)	207	if (suf)
208	printf ("%cPC862%sZPnn%s", pre, mid, suf);	208	printf ("%cPC862%sZPnn%s", pre, mid, suf);
209	else	209	else
210	printf ("unknown MPC862 (0x%08x)", k);	210	printf ("unknown MPC862 (0x%08x)", k);
211	#else	211	#else
212	if (suf)	212	if (suf)
213	printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */	213	printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
214	else	214	else
215	printf ("unknown MPC857 (0x%08x)", k);	215	printf ("unknown MPC857 (0x%08x)", k);
216	#endif	216	#endif
217		217
218	printf (" at %s MHz:", strmhz (buf, clock));	218	printf (" at %s MHz:", strmhz (buf, clock));
219		219
220	printf (" %u kB I-Cache", checkicache () >> 10);	220	printf (" %u kB I-Cache", checkicache () >> 10);
221	printf (" %u kB D-Cache", checkdcache () >> 10);	221	printf (" %u kB D-Cache", checkdcache () >> 10);
222		222
223	/* lets check and see if we're running on a 862T (or P?) */	223	/* lets check and see if we're running on a 862T (or P?) */
224		224
225	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;	225	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
226	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {	226	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
227	printf (" FEC present");	227	printf (" FEC present");
228	}	228	}
229		229
230	if (!m) {	230	if (!m) {
231	puts (cpu_warning);	231	puts (cpu_warning);
232	}	232	}
233		233
234	putc ('\n');	234	putc ('\n');
235		235
236	return 0;	236	return 0;
237	}	237	}
238		238
239	#elif defined(CONFIG_MPC823)	239	#elif defined(CONFIG_MPC823)
240		240
241	static int check_CPU (long clock, uint pvr, uint immr)	241	static int check_CPU (long clock, uint pvr, uint immr)
242	{	242	{
243	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);	243	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
244	uint k, m;	244	uint k, m;
245	char buf[32];	245	char buf[32];
246	char *suf;	246	char *suf;
247		247
248	/* the highest 16 bits should be 0x0050 for a 8xx */	248	/* the highest 16 bits should be 0x0050 for a 8xx */
249		249
250	if ((pvr >> 16) != 0x0050)	250	if ((pvr >> 16) != 0x0050)
251	return -1;	251	return -1;
252		252
253	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);	253	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
254	m = 0;	254	m = 0;
255		255
256	switch (k) {	256	switch (k) {
257	/* MPC823 */	257	/* MPC823 */
258	case 0x20000000: suf = "0"; break;	258	case 0x20000000: suf = "0"; break;
259	case 0x20010000: suf = "0.1"; break;	259	case 0x20010000: suf = "0.1"; break;
260	case 0x20020000: suf = "Z2/3"; break;	260	case 0x20020000: suf = "Z2/3"; break;
261	case 0x20020001: suf = "Z3"; break;	261	case 0x20020001: suf = "Z3"; break;
262	case 0x21000000: suf = "A"; break;	262	case 0x21000000: suf = "A"; break;
263	case 0x21010000: suf = "B"; m = 1; break;	263	case 0x21010000: suf = "B"; m = 1; break;
264	case 0x21010001: suf = "B2"; m = 1; break;	264	case 0x21010001: suf = "B2"; m = 1; break;
265	/* MPC823E */	265	/* MPC823E */
266	case 0x24010000: suf = NULL;	266	case 0x24010000: suf = NULL;
267	puts ("PPC823EZTnnB2");	267	puts ("PPC823EZTnnB2");
268	m = 1;	268	m = 1;
269	break;	269	break;
270	default:	270	default:
271	suf = NULL;	271	suf = NULL;
272	printf ("unknown MPC823 (0x%08x)", k);	272	printf ("unknown MPC823 (0x%08x)", k);
273	break;	273	break;
274	}	274	}
275	if (suf)	275	if (suf)
276	printf ("PPC823ZTnn%s", suf);	276	printf ("PPC823ZTnn%s", suf);
277		277
278	printf (" at %s MHz:", strmhz (buf, clock));	278	printf (" at %s MHz:", strmhz (buf, clock));
279		279
280	printf (" %u kB I-Cache", checkicache () >> 10);	280	printf (" %u kB I-Cache", checkicache () >> 10);
281	printf (" %u kB D-Cache", checkdcache () >> 10);	281	printf (" %u kB D-Cache", checkdcache () >> 10);
282		282
283	/* lets check and see if we're running on a 860T (or P?) */	283	/* lets check and see if we're running on a 860T (or P?) */
284		284
285	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;	285	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
286	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {	286	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
287	puts (" FEC present");	287	puts (" FEC present");
288	}	288	}
289		289
290	if (!m) {	290	if (!m) {
291	puts (cpu_warning);	291	puts (cpu_warning);
292	}	292	}
293		293
294	putc ('\n');	294	putc ('\n');
295		295
296	return 0;	296	return 0;
297	}	297	}
298		298
299	#elif defined(CONFIG_MPC850)	299	#elif defined(CONFIG_MPC850)
300		300
301	static int check_CPU (long clock, uint pvr, uint immr)	301	static int check_CPU (long clock, uint pvr, uint immr)
302	{	302	{
303	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);	303	volatile immap_t immap = (immap_t ) (immr & 0xFFFF0000);
304	uint k, m;	304	uint k, m;
305	char buf[32];	305	char buf[32];
306		306
307	/* the highest 16 bits should be 0x0050 for a 8xx */	307	/* the highest 16 bits should be 0x0050 for a 8xx */
308		308
309	if ((pvr >> 16) != 0x0050)	309	if ((pvr >> 16) != 0x0050)
310	return -1;	310	return -1;
311		311
312	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);	312	k = (immr << 16) \| ((ushort ) & immap->im_cpm.cp_dparam[0xB0]);
313	m = 0;	313	m = 0;
314		314
315	switch (k) {	315	switch (k) {
316	case 0x20020001:	316	case 0x20020001:
317	printf ("XPC850xxZT");	317	printf ("XPC850xxZT");
318	break;	318	break;
319	case 0x21000065:	319	case 0x21000065:
320	printf ("XPC850xxZTA");	320	printf ("XPC850xxZTA");
321	break;	321	break;
322	case 0x21010067:	322	case 0x21010067:
323	printf ("XPC850xxZTB");	323	printf ("XPC850xxZTB");
324	m = 1;	324	m = 1;
325	break;	325	break;
326	case 0x21020068:	326	case 0x21020068:
327	printf ("XPC850xxZTC");	327	printf ("XPC850xxZTC");
328	m = 1;	328	m = 1;
329	break;	329	break;
330	default:	330	default:
331	printf ("unknown MPC850 (0x%08x)", k);	331	printf ("unknown MPC850 (0x%08x)", k);
332	}	332	}
333	printf (" at %s MHz:", strmhz (buf, clock));	333	printf (" at %s MHz:", strmhz (buf, clock));
334		334
335	printf (" %u kB I-Cache", checkicache () >> 10);	335	printf (" %u kB I-Cache", checkicache () >> 10);
336	printf (" %u kB D-Cache", checkdcache () >> 10);	336	printf (" %u kB D-Cache", checkdcache () >> 10);
337		337
338	/* lets check and see if we're running on a 850T (or P?) */	338	/* lets check and see if we're running on a 850T (or P?) */
339		339
340	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;	340	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
341	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {	341	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
342	printf (" FEC present");	342	printf (" FEC present");
343	}	343	}
344		344
345	if (!m) {	345	if (!m) {
346	puts (cpu_warning);	346	puts (cpu_warning);
347	}	347	}
348		348
349	putc ('\n');	349	putc ('\n');
350		350
351	return 0;	351	return 0;
352	}	352	}
353	#else	353	#else
354	#error CPU undefined	354	#error CPU undefined
355	#endif	355	#endif
356	/* ------------------------------------------------------------------------- */	356	/* ------------------------------------------------------------------------- */
357		357
358	int checkcpu (void)	358	int checkcpu (void)
359	{	359	{
360	ulong clock = gd->cpu_clk;	360	ulong clock = gd->cpu_clk;
361	uint immr = get_immr (0); /* Return full IMMR contents */	361	uint immr = get_immr (0); /* Return full IMMR contents */
362	uint pvr = get_pvr ();	362	uint pvr = get_pvr ();
363		363
364	puts ("CPU: ");	364	puts ("CPU: ");
365		365
366	/* 850 has PARTNUM 20 */	366	/* 850 has PARTNUM 20 */
367	/* 801 has PARTNUM 10 */	367	/* 801 has PARTNUM 10 */
368	return check_CPU (clock, pvr, immr);	368	return check_CPU (clock, pvr, immr);
369	}	369	}
370		370
371	/* ------------------------------------------------------------------------- */	371	/* ------------------------------------------------------------------------- */
372	/* L1 i-cache */	372	/* L1 i-cache */
373	/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */	373	/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
374	/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */	374	/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
375		375
376	int checkicache (void)	376	int checkicache (void)
377	{	377	{
378	volatile immap_t immap = (immap_t ) CFG_IMMR;	378	volatile immap_t immap = (immap_t ) CFG_IMMR;
379	volatile memctl8xx_t *memctl = &immap->im_memctl;	379	volatile memctl8xx_t *memctl = &immap->im_memctl;
380	u32 cacheon = rd_ic_cst () & IDC_ENABLED;	380	u32 cacheon = rd_ic_cst () & IDC_ENABLED;
381		381
382	#ifdef CONFIG_IP86x	382	#ifdef CONFIG_IP86x
383	u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */	383	u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
384	#else	384	#else
385	u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */	385	u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
386	#endif	386	#endif
387	u32 m;	387	u32 m;
388	u32 lines = -1;	388	u32 lines = -1;
389		389
390	wr_ic_cst (IDC_UNALL);	390	wr_ic_cst (IDC_UNALL);
391	wr_ic_cst (IDC_INVALL);	391	wr_ic_cst (IDC_INVALL);
392	wr_ic_cst (IDC_DISABLE);	392	wr_ic_cst (IDC_DISABLE);
393	__asm__ volatile ("isync");	393	__asm__ volatile ("isync");
394		394
395	while (!((m = rd_ic_cst ()) & IDC_CERR2)) {	395	while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
396	wr_ic_adr (k);	396	wr_ic_adr (k);
397	wr_ic_cst (IDC_LDLCK);	397	wr_ic_cst (IDC_LDLCK);
398	__asm__ volatile ("isync");	398	__asm__ volatile ("isync");
399		399
400	lines++;	400	lines++;
401	k += 0x10; /* the number of bytes in a cacheline */	401	k += 0x10; /* the number of bytes in a cacheline */
402	}	402	}
403		403
404	wr_ic_cst (IDC_UNALL);	404	wr_ic_cst (IDC_UNALL);
405	wr_ic_cst (IDC_INVALL);	405	wr_ic_cst (IDC_INVALL);
406		406
407	if (cacheon)	407	if (cacheon)
408	wr_ic_cst (IDC_ENABLE);	408	wr_ic_cst (IDC_ENABLE);
409	else	409	else
410	wr_ic_cst (IDC_DISABLE);	410	wr_ic_cst (IDC_DISABLE);
411		411
412	__asm__ volatile ("isync");	412	__asm__ volatile ("isync");
413		413
414	return lines << 4;	414	return lines << 4;
415	};	415	};
416		416
417	/* ------------------------------------------------------------------------- */	417	/* ------------------------------------------------------------------------- */
418	/* L1 d-cache */	418	/* L1 d-cache */
419	/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */	419	/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
420	/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */	420	/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
421	/* call with cache disabled */	421	/* call with cache disabled */
422		422
423	int checkdcache (void)	423	int checkdcache (void)
424	{	424	{
425	volatile immap_t immap = (immap_t ) CFG_IMMR;	425	volatile immap_t immap = (immap_t ) CFG_IMMR;
426	volatile memctl8xx_t *memctl = &immap->im_memctl;	426	volatile memctl8xx_t *memctl = &immap->im_memctl;
427	u32 cacheon = rd_dc_cst () & IDC_ENABLED;	427	u32 cacheon = rd_dc_cst () & IDC_ENABLED;
428		428
429	#ifdef CONFIG_IP86x	429	#ifdef CONFIG_IP86x
430	u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */	430	u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
431	#else	431	#else
432	u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */	432	u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
433	#endif	433	#endif
434	u32 m;	434	u32 m;
435	u32 lines = -1;	435	u32 lines = -1;
436		436
437	wr_dc_cst (IDC_UNALL);	437	wr_dc_cst (IDC_UNALL);
438	wr_dc_cst (IDC_INVALL);	438	wr_dc_cst (IDC_INVALL);
439	wr_dc_cst (IDC_DISABLE);	439	wr_dc_cst (IDC_DISABLE);
440		440
441	while (!((m = rd_dc_cst ()) & IDC_CERR2)) {	441	while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
442	wr_dc_adr (k);	442	wr_dc_adr (k);
443	wr_dc_cst (IDC_LDLCK);	443	wr_dc_cst (IDC_LDLCK);
444	lines++;	444	lines++;
445	k += 0x10; /* the number of bytes in a cacheline */	445	k += 0x10; /* the number of bytes in a cacheline */
446	}	446	}
447		447
448	wr_dc_cst (IDC_UNALL);	448	wr_dc_cst (IDC_UNALL);
449	wr_dc_cst (IDC_INVALL);	449	wr_dc_cst (IDC_INVALL);
450		450
451	if (cacheon)	451	if (cacheon)
452	wr_dc_cst (IDC_ENABLE);	452	wr_dc_cst (IDC_ENABLE);
453	else	453	else
454	wr_dc_cst (IDC_DISABLE);	454	wr_dc_cst (IDC_DISABLE);
455		455
456	return lines << 4;	456	return lines << 4;
457	};	457	};
458		458
459	/* ------------------------------------------------------------------------- */	459	/* ------------------------------------------------------------------------- */
460		460
461	void upmconfig (uint upm, uint * table, uint size)	461	void upmconfig (uint upm, uint * table, uint size)
462	{	462	{
463	uint i;	463	uint i;
464	uint addr = 0;	464	uint addr = 0;
465	volatile immap_t immap = (immap_t ) CFG_IMMR;	465	volatile immap_t immap = (immap_t ) CFG_IMMR;
466	volatile memctl8xx_t *memctl = &immap->im_memctl;	466	volatile memctl8xx_t *memctl = &immap->im_memctl;
467		467
468	for (i = 0; i < size; i++) {	468	for (i = 0; i < size; i++) {
469	memctl->memc_mdr = table[i]; /* (16-15) */	469	memctl->memc_mdr = table[i]; /* (16-15) */
470	memctl->memc_mcr = addr \| upm; /* (16-16) */	470	memctl->memc_mcr = addr \| upm; /* (16-16) */
471	addr++;	471	addr++;
472	}	472	}
473	}	473	}
474		474
475	/* ------------------------------------------------------------------------- */	475	/* ------------------------------------------------------------------------- */
476		476
477	#ifndef CONFIG_LWMON	477	#ifndef CONFIG_LWMON
478		478
479	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])	479	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
480	{	480	{
481	ulong msr, addr;	481	ulong msr, addr;
482		482
483	volatile immap_t immap = (immap_t ) CFG_IMMR;	483	volatile immap_t immap = (immap_t ) CFG_IMMR;
484		484
485	immap->im_clkrst.car_plprcr \|= PLPRCR_CSR; /* Checkstop Reset enable */	485	immap->im_clkrst.car_plprcr \|= PLPRCR_CSR; /* Checkstop Reset enable */
486		486
487	/* Interrupts and MMU off */	487	/* Interrupts and MMU off */
488	__asm__ volatile ("mtspr 81, 0");	488	__asm__ volatile ("mtspr 81, 0");
489	__asm__ volatile ("mfmsr %0":"=r" (msr));	489	__asm__ volatile ("mfmsr %0":"=r" (msr));
490		490
491	msr &= ~0x1030;	491	msr &= ~0x1030;
492	__asm__ volatile ("mtmsr %0"::"r" (msr));	492	__asm__ volatile ("mtmsr %0"::"r" (msr));
493		493
494	/*	494	/*
495	* Trying to execute the next instruction at a non-existing address	495	* Trying to execute the next instruction at a non-existing address
496	* should cause a machine check, resulting in reset	496	* should cause a machine check, resulting in reset
497	*/	497	*/
498	#ifdef CFG_RESET_ADDRESS	498	#ifdef CFG_RESET_ADDRESS
499	addr = CFG_RESET_ADDRESS;	499	addr = CFG_RESET_ADDRESS;
500	#else	500	#else
501	/*	501	/*
502	* note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE	502	* note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
503	* - sizeof (ulong) is usually a valid address. Better pick an address	503	* - sizeof (ulong) is usually a valid address. Better pick an address
504	* known to be invalid on your system and assign it to CFG_RESET_ADDRESS.	504	* known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
505	* "(ulong)-1" used to be a good choice for many systems...	505	* "(ulong)-1" used to be a good choice for many systems...
506	*/	506	*/
507	addr = CFG_MONITOR_BASE - sizeof (ulong);	507	addr = CFG_MONITOR_BASE - sizeof (ulong);
508	#endif	508	#endif
509	((void (*)(void)) addr) ();	509	((void (*)(void)) addr) ();
510	return 1;	510	return 1;
511	}	511	}
512		512
513	#else /* CONFIG_LWMON */	513	#else /* CONFIG_LWMON */
514		514
515	/*	515	/*
516	* On the LWMON board, the MCLR reset input of the PIC's on the board	516	* On the LWMON board, the MCLR reset input of the PIC's on the board
517	* uses a 47K/1n RC combination which has a 47us time constant. The	517	* uses a 47K/1n RC combination which has a 47us time constant. The
518	* low signal on the HRESET pin of the CPU is only 512 clocks = 8 us	518	* low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
519	* and thus too short to reset the external hardware. So we use the	519	* and thus too short to reset the external hardware. So we use the
520	* watchdog to reset the board.	520	* watchdog to reset the board.
521	*/	521	*/
522	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])	522	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
523	{	523	{
524	/* prevent triggering the watchdog */	524	/* prevent triggering the watchdog */
525	disable_interrupts ();	525	disable_interrupts ();
526		526
527	/* make sure the watchdog is running */	527	/* make sure the watchdog is running */
528	reset_8xx_watchdog ((immap_t *) CFG_IMMR);	528	reset_8xx_watchdog ((immap_t *) CFG_IMMR);
529		529
530	/* wait for watchdog reset */	530	/* wait for watchdog reset */
531	while (1) {};	531	while (1) {};
532		532
533	/* NOTREACHED */	533	/* NOTREACHED */
534	return 1;	534	return 1;
535	}	535	}
536		536
537	#endif /* CONFIG_LWMON */	537	#endif /* CONFIG_LWMON */
538		538
539	/* ------------------------------------------------------------------------- */	539	/* ------------------------------------------------------------------------- */
540		540
541	/*	541	/*
542	* Get timebase clock frequency (like cpu_clk in Hz)	542	* Get timebase clock frequency (like cpu_clk in Hz)
543	*	543	*
544	* See sections 14.2 and 14.6 of the User's Manual	544	* See sections 14.2 and 14.6 of the User's Manual
545	*/	545	*/
546	unsigned long get_tbclk (void)	546	unsigned long get_tbclk (void)
547	{	547	{
548	uint immr = get_immr (0); /* Return full IMMR contents */	548	uint immr = get_immr (0); /* Return full IMMR contents */
549	volatile immap_t immap = (volatile immap_t )(immr & 0xFFFF0000);	549	volatile immap_t immap = (volatile immap_t )(immr & 0xFFFF0000);
550	ulong oscclk, factor, pll;	550	ulong oscclk, factor, pll;
551		551
552	if (immap->im_clkrst.car_sccr & SCCR_TBS) {	552	if (immap->im_clkrst.car_sccr & SCCR_TBS) {
553	return (gd->cpu_clk / 16);	553	return (gd->cpu_clk / 16);
554	}	554	}
555		555
556	pll = immap->im_clkrst.car_plprcr;	556	pll = immap->im_clkrst.car_plprcr;
557		557
558	#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)	558	#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
559		559
560	/*	560	/*
561	* For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication	561	* For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
562	* factor is calculated as follows:	562	* factor is calculated as follows:
563	*	563	*
564	* MFN	564	* MFN
565	* MFI + -------	565	* MFI + -------
566	* MFD + 1	566	* MFD + 1
567	* factor = -----------------	567	* factor = -----------------
568	* (PDF + 1) * 2^S	568	* (PDF + 1) * 2^S
569	*	569	*
570	* For older chips, it's just MF field of PLPRCR plus one.	570	* For older chips, it's just MF field of PLPRCR plus one.
571	*/	571	*/
572	if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */	572	if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
573	factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/	573	factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
574	(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));	574	(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
575	} else {	575	} else {
576	factor = PLPRCR_val(MF)+1;	576	factor = PLPRCR_val(MF)+1;
577	}	577	}
578		578
579	oscclk = gd->cpu_clk / factor;	579	oscclk = gd->cpu_clk / factor;
580		580
581	if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 \|\| factor > 2) {	581	if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 \|\| factor > 2) {
582	return (oscclk / 4);	582	return (oscclk / 4);
583	}	583	}
584	return (oscclk / 16);	584	return (oscclk / 16);
585	}	585	}
586		586
587	/* ------------------------------------------------------------------------- */	587	/* ------------------------------------------------------------------------- */
588		588
589	#if defined(CONFIG_WATCHDOG)	589	#if defined(CONFIG_WATCHDOG)
590	void watchdog_reset (void)	590	void watchdog_reset (void)
591	{	591	{
592	int re_enable = disable_interrupts ();	592	int re_enable = disable_interrupts ();
593		593
594	reset_8xx_watchdog ((immap_t *) CFG_IMMR);	594	reset_8xx_watchdog ((immap_t *) CFG_IMMR);
595	if (re_enable)	595	if (re_enable)
596	enable_interrupts ();	596	enable_interrupts ();
597	}	597	}
598	#endif /* CONFIG_WATCHDOG */	598	#endif /* CONFIG_WATCHDOG */
599		599
600	#if defined(CONFIG_WATCHDOG) \|\| defined(CONFIG_LWMON)	600	#if defined(CONFIG_WATCHDOG) \|\| defined(CONFIG_LWMON)
601		601
602	void reset_8xx_watchdog (volatile immap_t * immr)	602	void reset_8xx_watchdog (volatile immap_t * immr)
603	{	603	{
604	# if defined(CONFIG_LWMON)	604	# if defined(CONFIG_LWMON)
605	/*	605	/*
606	* The LWMON board uses a MAX6301 Watchdog	606	* The LWMON board uses a MAX6301 Watchdog
607	* with the trigger pin connected to port PA.7	607	* with the trigger pin connected to port PA.7
608	*	608	*
609	* (The old board version used a MAX706TESA Watchdog, which	609	* (The old board version used a MAX706TESA Watchdog, which
610	* had to be handled exactly the same.)	610	* had to be handled exactly the same.)
611	*/	611	*/
612	# define WATCHDOG_BIT 0x0100	612	# define WATCHDOG_BIT 0x0100
613	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */	613	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
614	immr->im_ioport.iop_padir \|= WATCHDOG_BIT; /* Output */	614	immr->im_ioport.iop_padir \|= WATCHDOG_BIT; /* Output */
615	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */	615	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
616		616
617	immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */	617	immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
618	# elif defined(CONFIG_KUP4K) \|\| defined(CONFIG_KUP4X)	618	# elif defined(CONFIG_KUP4K) \|\| defined(CONFIG_KUP4X)
619	/*	619	/*
620	* The KUP4 boards uses a TPS3705 Watchdog	620	* The KUP4 boards uses a TPS3705 Watchdog
621	* with the trigger pin connected to port PA.5	621	* with the trigger pin connected to port PA.5
622	*/	622	*/
623	# define WATCHDOG_BIT 0x0400	623	# define WATCHDOG_BIT 0x0400
624	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */	624	immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
625	immr->im_ioport.iop_padir \|= WATCHDOG_BIT; /* Output */	625	immr->im_ioport.iop_padir \|= WATCHDOG_BIT; /* Output */
626	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */	626	immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
627		627
628	immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */	628	immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
629	# else	629	# else
630	/*	630	/*
631	* All other boards use the MPC8xx Internal Watchdog	631	* All other boards use the MPC8xx Internal Watchdog
632	*/	632	*/
633	immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */	633	immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
634	immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */	634	immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
635	# endif /* CONFIG_LWMON */	635	# endif /* CONFIG_LWMON */
636	}	636	}
637		637
638	#endif /* CONFIG_WATCHDOG */	638	#endif /* CONFIG_WATCHDOG */
639		639
640	/* ------------------------------------------------------------------------- */	640	/* ------------------------------------------------------------------------- */
641	#if defined(CONFIG_OF_LIBFDT)	641	#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
642	void ft_cpu_setup (void blob, bd_t bd)	642	void ft_cpu_setup (void blob, bd_t bd)
643	{	643	{
644	char * cpu_path = "/cpus/" OF_CPU;	644	char * cpu_path = "/cpus/" OF_CPU;
645		645
646	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);	646	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
647	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);	647	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
648	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);	648	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
649	}	649	}
650	#endif /* CONFIG_OF_LIBFDT */	650	#endif /* CONFIG_OF_LIBFDT */
651		651

include/image.h

Diff comments View file @ 75d3e8f

 /*
  * (C) Copyright 2008 Semihalf
  *
  * (C) Copyright 2000-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
  ********************************************************************
  * NOTE: This header file defines an interface to U-Boot. Including
  * this (unmodified) header file in another file is considered normal
  * use of U-Boot, and does *not* fall under the heading of "derived
  * work".
  ********************************************************************
  */
 #ifndef __IMAGE_H__
 #define __IMAGE_H__
 #include <asm/byteorder.h>
 #include <command.h>
 #ifndef USE_HOSTCC
 #include <linux/string.h>
 #include <asm/u-boot.h>
+/* new uImage format support enabled by default */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#if defined(CONFIG_FIT) && !defined(CONFIG_OF_LIBFDT)
+#error "CONFIG_OF_LIBFDT not enabled, required by CONFIG_FIT!"
 #endif
+#endif /* USE_HOSTCC */
 /*
  * Operating System Codes
  */
 #define IH_OS_INVALID		0	/* Invalid OS	*/
 #define IH_OS_OPENBSD		1	/* OpenBSD	*/
 #define IH_OS_NETBSD		2	/* NetBSD	*/
 #define IH_OS_FREEBSD		3	/* FreeBSD	*/
 #define IH_OS_4_4BSD		4	/* 4.4BSD	*/
 #define IH_OS_LINUX		5	/* Linux	*/
 #define IH_OS_SVR4		6	/* SVR4		*/
 #define IH_OS_ESIX		7	/* Esix		*/
 #define IH_OS_SOLARIS		8	/* Solaris	*/
 #define IH_OS_IRIX		9	/* Irix		*/
 #define IH_OS_SCO		10	/* SCO		*/
 #define IH_OS_DELL		11	/* Dell		*/
 #define IH_OS_NCR		12	/* NCR		*/
 #define IH_OS_LYNXOS		13	/* LynxOS	*/
 #define IH_OS_VXWORKS		14	/* VxWorks	*/
 #define IH_OS_PSOS		15	/* pSOS		*/
 #define IH_OS_QNX		16	/* QNX		*/
 #define IH_OS_U_BOOT		17	/* Firmware	*/
 #define IH_OS_RTEMS		18	/* RTEMS	*/
 #define IH_OS_ARTOS		19	/* ARTOS	*/
 #define IH_OS_UNITY		20	/* Unity OS	*/
 /*
  * CPU Architecture Codes (supported by Linux)
  */
 #define IH_ARCH_INVALID		0	/* Invalid CPU	*/
 #define IH_ARCH_ALPHA		1	/* Alpha	*/
 #define IH_ARCH_ARM		2	/* ARM		*/
 #define IH_ARCH_I386		3	/* Intel x86	*/
 #define IH_ARCH_IA64		4	/* IA64		*/
 #define IH_ARCH_MIPS		5	/* MIPS		*/
 #define IH_ARCH_MIPS64		6	/* MIPS	 64 Bit */
 #define IH_ARCH_PPC		7	/* PowerPC	*/
 #define IH_ARCH_S390		8	/* IBM S390	*/
 #define IH_ARCH_SH		9	/* SuperH	*/
 #define IH_ARCH_SPARC		10	/* Sparc	*/
 #define IH_ARCH_SPARC64		11	/* Sparc 64 Bit */
 #define IH_ARCH_M68K		12	/* M68K		*/
 #define IH_ARCH_NIOS		13	/* Nios-32	*/
 #define IH_ARCH_MICROBLAZE	14	/* MicroBlaze   */
 #define IH_ARCH_NIOS2		15	/* Nios-II	*/
 #define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
 #define IH_ARCH_AVR32		17	/* AVR32	*/
 #define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
 /*
  * Image Types
  *
  * "Standalone Programs" are directly runnable in the environment
  *	provided by U-Boot; it is expected that (if they behave
  *	well) you can continue to work in U-Boot after return from
  *	the Standalone Program.
  * "OS Kernel Images" are usually images of some Embedded OS which
  *	will take over control completely. Usually these programs
  *	will install their own set of exception handlers, device
  *	drivers, set up the MMU, etc. - this means, that you cannot
  *	expect to re-enter U-Boot except by resetting the CPU.
  * "RAMDisk Images" are more or less just data blocks, and their
  *	parameters (address, size) are passed to an OS kernel that is
  *	being started.
  * "Multi-File Images" contain several images, typically an OS
  *	(Linux) kernel image and one or more data images like
  *	RAMDisks. This construct is useful for instance when you want
  *	to boot over the network using BOOTP etc., where the boot
  *	server provides just a single image file, but you want to get
  *	for instance an OS kernel and a RAMDisk image.
  *
  *	"Multi-File Images" start with a list of image sizes, each
  *	image size (in bytes) specified by an "uint32_t" in network
  *	byte order. This list is terminated by an "(uint32_t)0".
  *	Immediately after the terminating 0 follow the images, one by
  *	one, all aligned on "uint32_t" boundaries (size rounded up to
  *	a multiple of 4 bytes - except for the last file).
  *
  * "Firmware Images" are binary images containing firmware (like
  *	U-Boot or FPGA images) which usually will be programmed to
  *	flash memory.
  *
  * "Script files" are command sequences that will be executed by
  *	U-Boot's command interpreter; this feature is especially
  *	useful when you configure U-Boot to use a real shell (hush)
  *	as command interpreter (=> Shell Scripts).
  */
 #define IH_TYPE_INVALID		0	/* Invalid Image		*/
 #define IH_TYPE_STANDALONE	1	/* Standalone Program		*/
 #define IH_TYPE_KERNEL		2	/* OS Kernel Image		*/
 #define IH_TYPE_RAMDISK		3	/* RAMDisk Image		*/
 #define IH_TYPE_MULTI		4	/* Multi-File Image		*/
 #define IH_TYPE_FIRMWARE	5	/* Firmware Image		*/
 #define IH_TYPE_SCRIPT		6	/* Script file			*/
 #define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 /*
  * Compression Types
  */
 #define IH_COMP_NONE		0	/*  No	 Compression Used	*/
 #define IH_COMP_GZIP		1	/* gzip	 Compression Used	*/
 #define IH_COMP_BZIP2		2	/* bzip2 Compression Used	*/
 #define IH_MAGIC	0x27051956	/* Image Magic Number		*/
 #define IH_NMLEN		32	/* Image Name Length		*/
 /*
  * all data in network byte order (aka natural aka bigendian)
  */
 typedef struct image_header {
 	uint32_t	ih_magic;	/* Image Header Magic Number	*/
 	uint32_t	ih_hcrc;	/* Image Header CRC Checksum	*/
 	uint32_t	ih_time;	/* Image Creation Timestamp	*/
 	uint32_t	ih_size;	/* Image Data Size		*/
 	uint32_t	ih_load;	/* Data	 Load  Address		*/
 	uint32_t	ih_ep;		/* Entry Point Address		*/
 	uint32_t	ih_dcrc;	/* Image Data CRC Checksum	*/
 	uint8_t		ih_os;		/* Operating System		*/
 	uint8_t		ih_arch;	/* CPU architecture		*/
 	uint8_t		ih_type;	/* Image Type			*/
 	uint8_t		ih_comp;	/* Compression Type		*/
 	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
 } image_header_t;
 /*
  * Some systems (for example LWMON) have very short watchdog periods;
  * we must make sure to split long operations like memmove() or
  * crc32() into reasonable chunks.
  */
 #define CHUNKSZ (64 * 1024)
 #define image_to_cpu(x)		ntohl(x)
 #define cpu_to_image(x)		htonl(x)
 static inline uint32_t image_get_header_size (void)
 {
 	return (sizeof (image_header_t));
 }
 #define image_get_hdr_l(f) \
 	static inline uint32_t image_get_##f(image_header_t *hdr) \
 	{ \
 		return image_to_cpu (hdr->ih_##f); \
 	}
 image_get_hdr_l (magic);
 image_get_hdr_l (hcrc);
 image_get_hdr_l (time);
 image_get_hdr_l (size);
 image_get_hdr_l (load);
 image_get_hdr_l (ep);
 image_get_hdr_l (dcrc);
 #define image_get_hdr_b(f) \
 	static inline uint8_t image_get_##f(image_header_t *hdr) \
 	{ \
 		return hdr->ih_##f; \
 	}
 image_get_hdr_b (os);
 image_get_hdr_b (arch);
 image_get_hdr_b (type);
 image_get_hdr_b (comp);
 static inline char *image_get_name (image_header_t *hdr)
 {
 	return (char *)hdr->ih_name;
 }
 static inline uint32_t image_get_data_size (image_header_t *hdr)
 {
 	return image_get_size (hdr);
 }
 /**
  * image_get_data - get image payload start address
  * @hdr: image header
  *
  * image_get_data() returns address of the image payload. For single
  * component images it is image data start. For multi component
  * images it points to the null terminated table of sub-images sizes.
  *
  * returns:
  *     image payload data start address
  */
 static inline ulong image_get_data (image_header_t *hdr)
 {
 	return ((ulong)hdr + image_get_header_size ());
 }
 static inline uint32_t image_get_image_size (image_header_t *hdr)
 {
 	return (image_get_size (hdr) + image_get_header_size ());
 }
 static inline ulong image_get_image_end (image_header_t *hdr)
 {
 	return ((ulong)hdr + image_get_image_size (hdr));
 }
 #define image_set_hdr_l(f) \
 	static inline void image_set_##f(image_header_t *hdr, uint32_t val) \
 	{ \
 		hdr->ih_##f = cpu_to_image (val); \
 	}
 image_set_hdr_l (magic);
 image_set_hdr_l (hcrc);
 image_set_hdr_l (time);
 image_set_hdr_l (size);
 image_set_hdr_l (load);
 image_set_hdr_l (ep);
 image_set_hdr_l (dcrc);
 #define image_set_hdr_b(f) \
 	static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
 	{ \
 		hdr->ih_##f = val; \
 	}
 image_set_hdr_b (os);
 image_set_hdr_b (arch);
 image_set_hdr_b (type);
 image_set_hdr_b (comp);
 static inline void image_set_name (image_header_t *hdr, const char *name)
 {
 	strncpy (image_get_name (hdr), name, IH_NMLEN);
 }
 int image_check_hcrc (image_header_t *hdr);
 int image_check_dcrc (image_header_t *hdr);
 #ifndef USE_HOSTCC
 int image_check_dcrc_wd (image_header_t *hdr, ulong chunksize);
 int getenv_verify (void);
 void memmove_wd (void *to, void *from, size_t len, ulong chunksz);
 #endif
 static inline int image_check_magic (image_header_t *hdr)
 {
 	return (image_get_magic (hdr) == IH_MAGIC);
 }
 static inline int image_check_type (image_header_t *hdr, uint8_t type)
 {
 	return (image_get_type (hdr) == type);
 }
 static inline int image_check_arch (image_header_t *hdr, uint8_t arch)
 {
 	return (image_get_arch (hdr) == arch);
 }
 static inline int image_check_os (image_header_t *hdr, uint8_t os)
 {
 	return (image_get_os (hdr) == os);
 }
 ulong image_multi_count (image_header_t *hdr);
 void image_multi_getimg (image_header_t *hdr, ulong idx,
 			ulong *data, ulong *len);
 #ifndef USE_HOSTCC
 static inline int image_check_target_arch (image_header_t *hdr)
 {
 #if defined(__ARM__)
 	if (!image_check_arch (hdr, IH_ARCH_ARM))
 #elif defined(__avr32__)
 	if (!image_check_arch (hdr, IH_ARCH_AVR32))
 #elif defined(__bfin__)
 	if (!image_check_arch (hdr, IH_ARCH_BLACKFIN))
 #elif defined(__I386__)
 	if (!image_check_arch (hdr, IH_ARCH_I386))
 #elif defined(__M68K__)
 	if (!image_check_arch (hdr, IH_ARCH_M68K))
 #elif defined(__microblaze__)
 	if (!image_check_arch (hdr, IH_ARCH_MICROBLAZE))
 #elif defined(__mips__)
 	if (!image_check_arch (hdr, IH_ARCH_MIPS))
 #elif defined(__nios__)
 	if (!image_check_arch (hdr, IH_ARCH_NIOS))
 #elif defined(__nios2__)
 	if (!image_check_arch (hdr, IH_ARCH_NIOS2))
 #elif defined(__PPC__)
 	if (!image_check_arch (hdr, IH_ARCH_PPC))
 #elif defined(__sh__)
 	if (!image_check_arch (hdr, IH_ARCH_SH))
 #else
 # error Unknown CPU type
 #endif
 		return 0;
 	return 1;
 }
 const char* image_get_os_name (uint8_t os);
 const char* image_get_arch_name (uint8_t arch);
 const char* image_get_type_name (uint8_t type);
 const char* image_get_comp_name (uint8_t comp);
 image_header_t* image_get_ramdisk (cmd_tbl_t *cmdtp, int flag,
 		int argc, char *argv[],
 		ulong rd_addr, uint8_t arch, int verify);
 void get_ramdisk (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
 		image_header_t *hdr, int verify, uint8_t arch,
 		ulong *rd_start, ulong *rd_end);
 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
 ulong ramdisk_high (ulong alloc_current, ulong rd_data, ulong rd_len,
 		bd_t *kbd, ulong sp_limit, ulong sp,
 		ulong *initrd_start, ulong *initrd_end);
 ulong get_boot_sp_limit (ulong sp);
 ulong get_boot_cmdline (ulong alloc_current, ulong *cmd_start, ulong *cmd_end);
 ulong get_boot_kbd (ulong alloc_current, bd_t **kbd);
 #endif /* CONFIG_PPC || CONFIG_M68K */
 #endif /* USE_HOSTCC */
 #endif	/* __IMAGE_H__ */