From 7b055443be6b03583bdb3f3110c30803cdf872dd Mon Sep 17 00:00:00 2001 From: Eric Lee Date: Fri, 1 Nov 2019 23:09:17 +0800 Subject: [PATCH] Initial Release, U-Boot v2018.03 for SMARC-FiMX7 CPU Modules --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7d-smarcfimx7.dts | 1153 ++++++++++++++++++++ arch/arm/dts/imx7s-smarcfimx7.dts | 977 +++++++++++++++++ arch/arm/dts/imx7s.dtsi | 9 +- arch/arm/include/asm/arch-mx7/imx-rdc.h | 2 +- arch/arm/mach-imx/init.c | 4 +- arch/arm/mach-imx/mx7/Kconfig | 14 + arch/arm/mach-imx/mx7/soc.c | 2 +- board/embedian/smarcfimx7/Kconfig | 14 + board/embedian/smarcfimx7/MAINTAINERS | 14 + board/embedian/smarcfimx7/Makefile | 6 + .../smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg | 154 +++ .../smarcfimx7/ddr3l/mx7d_2x_mt41k512m16ha.cfg | 154 +++ .../smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg | 154 +++ board/embedian/smarcfimx7/plugin.S | 233 ++++ board/embedian/smarcfimx7/smarcfimx7.c | 1012 +++++++++++++++++ configs/smarcfimx7d_2g_ser0_defconfig | 93 ++ configs/smarcfimx7d_2g_ser1_defconfig | 93 ++ configs/smarcfimx7d_2g_ser2_defconfig | 93 ++ configs/smarcfimx7d_2g_ser3_defconfig | 93 ++ configs/smarcfimx7d_ser0_defconfig | 93 ++ configs/smarcfimx7d_ser1_defconfig | 93 ++ configs/smarcfimx7d_ser2_defconfig | 93 ++ configs/smarcfimx7d_ser3_defconfig | 93 ++ configs/smarcfimx7s_ser0_defconfig | 93 ++ configs/smarcfimx7s_ser1_defconfig | 93 ++ configs/smarcfimx7s_ser2_defconfig | 93 ++ configs/smarcfimx7s_ser3_defconfig | 93 ++ drivers/mmc/mmc.c | 4 +- drivers/mtd/spi/spi_flash_ids.c | 1 + drivers/ram/Kconfig | 5 + drivers/serial/Kconfig | 20 + drivers/watchdog/imx_watchdog.c | 6 +- include/configs/mx7smarc_common.h | 87 ++ include/configs/smarcfimx7.h | 415 +++++++ include/configs/smarcfimx7_androidthings.h | 52 + include/configs/smarcfimx7android.h | 38 + qspi_header | 128 +++ 38 files changed, 5764 insertions(+), 12 deletions(-) create mode 100644 arch/arm/dts/imx7d-smarcfimx7.dts create mode 100644 arch/arm/dts/imx7s-smarcfimx7.dts create mode 100644 board/embedian/smarcfimx7/Kconfig create mode 100644 board/embedian/smarcfimx7/MAINTAINERS create mode 100644 board/embedian/smarcfimx7/Makefile create mode 100644 board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg create mode 100644 board/embedian/smarcfimx7/ddr3l/mx7d_2x_mt41k512m16ha.cfg create mode 100644 board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg create mode 100644 board/embedian/smarcfimx7/plugin.S create mode 100644 board/embedian/smarcfimx7/smarcfimx7.c create mode 100644 configs/smarcfimx7d_2g_ser0_defconfig create mode 100644 configs/smarcfimx7d_2g_ser1_defconfig create mode 100644 configs/smarcfimx7d_2g_ser2_defconfig create mode 100644 configs/smarcfimx7d_2g_ser3_defconfig create mode 100644 configs/smarcfimx7d_ser0_defconfig create mode 100644 configs/smarcfimx7d_ser1_defconfig create mode 100644 configs/smarcfimx7d_ser2_defconfig create mode 100644 configs/smarcfimx7d_ser3_defconfig create mode 100644 configs/smarcfimx7s_ser0_defconfig create mode 100644 configs/smarcfimx7s_ser1_defconfig create mode 100644 configs/smarcfimx7s_ser2_defconfig create mode 100644 configs/smarcfimx7s_ser3_defconfig create mode 100644 include/configs/mx7smarc_common.h create mode 100644 include/configs/smarcfimx7.h create mode 100644 include/configs/smarcfimx7_androidthings.h create mode 100644 include/configs/smarcfimx7android.h create mode 100644 qspi_header diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c841df0..1246193 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -447,6 +447,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ imx7d-sdb-gpmi-weim.dtb \ imx7d-sdb-qspi.dtb \ imx7d-sdb-reva.dtb \ + imx7d-smarcfimx7.dtb \ + imx7s-smarcfimx7.dtb \ imx7d-12x12-lpddr3-arm2.dtb \ imx7d-12x12-lpddr3-arm2-ecspi.dtb \ imx7d-12x12-lpddr3-arm2-qspi.dtb \ diff --git a/arch/arm/dts/imx7d-smarcfimx7.dts b/arch/arm/dts/imx7d-smarcfimx7.dts new file mode 100644 index 0000000..0ba5813 --- /dev/null +++ b/arch/arm/dts/imx7d-smarcfimx7.dts @@ -0,0 +1,1153 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Embedian i.MX7D SMARC 2.0 Module"; + compatible = "fsl,imx7d-smarcfimx7", "fsl,imx7d"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + aliases { + ethernet1 = &fec2; /* Let eth1addr mac address pass from U-Boot EEPROM */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_aud_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "aud-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ + pwms = <&pwm2 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + sound { + compatible = "fsl,imx7d-smarcfimx7-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +/* SPI0 */ +&ecspi1 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>, <&gpio4 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + dmas = <&sdma 36 4 0>, <&sdma 37 4 0>; + dma-names = "rx", "tx"; + status = "okay"; + + spidev1: spidev@0 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <0>; + }; + spidev2: spidev@1 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <1>; + }; +}; + +/* SPINOR */ +&ecspi2 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + dmas = <&sdma 38 4 0>, <&sdma 39 4 0>; + dma-names = "rx", "tx"; + status = "okay"; + + flash: mx25u3235f@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25u3235f", "jedec,spi-nor"; + spi-max-frequency = <24000000>; + reg = <0>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "U-Boot Environment"; + reg = <0x100000 0x080000>; + }; + + partition@180000 { + label = "Flattened Device Tree"; + reg = <0x180000 0x200000>; + }; + + }; +}; + +/* ECSPI */ +&ecspi3 { + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; + cs-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>, <&gpio5 9 GPIO_ACTIVE_HIGH>; + dmas = <&sdma 40 4 0>, <&sdma 41 4 0>; + dma-names = "rx", "tx"; + status = "okay"; + + spidev3: spidev@0 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <0>; + }; + spidev4: spidev@4 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <1>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&csi1 { + csi-mux-mipi = <&gpr 0x14 4>; + fsl,mipi-mode; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; + }; + }; +}; + +&epxp { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&mipi_csi { + clock-frequency = <240000000>; + status = "okay"; + port { + mipi_sensor_ep: endpoint1 { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi_mipi_ep: endpoint2 { + remote-endpoint = <&csi_ep>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_vref_1v8>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_vref_1v8>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + + cape_eeprom0: cape_eeprom@57 { + compatible = "at,24c256"; + reg = <0x57>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; + VDDA-supply = <®_aud_3v3>; + VDDIO-supply = <®_vref_1v8>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* GPIO0 */ + AVDD-supply = <&vgen6_reg>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + enable-gpios = <&gpio3 4 0>; /* Enable LCD_VDD_EN pin */ + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + /*timing0: g070vw01 {*/ + timing0: timing0 { + clock-frequency = <33300000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <64>; + hback-porch = <64>; + hsync-len = <128>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pcie_phy{ + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + reset-gpio = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>; + + imx7d-smarcfimx7 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x30 + >; + }; + + pinctrl_usbotg2_pwr_2: usbotg2-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; + + pinctrl_enet2_epdc0_en: enet2_epdc0_grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x80000000 + >; + }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; + }; +}; + +/* SER0/UART6 */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* SER1/UART2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +/* SER2/UART7 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* SER3/UART3 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + gpios = <&gpio1 4 2>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + gpios = <&gpio1 6 2>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + vmmc-supply = <®_sd1_vmmc>; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-smarcfimx7 { + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__GPIO5_IO13 0x80000000 /* lvds channel select */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pcie_wake# */ + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x80000000 /* GPIO0 */ + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x80000000 /* GPIO1 */ + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x80000000 /* GPIO2 */ + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x80000000 /* GPIO3 */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x80000000 /* GPIO4 */ + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x80000000 /* GPIO6 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x80000000 /* GPIO7 */ + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x80000000 /* GPIO8 */ + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x80000000 /* GPIO9 */ + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x80000000 /* GPIO10 */ + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x80000000 /* GPIO11 */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x80000000 /* SLEEP# */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x80000000 /* CHARGER_PRSNT# */ + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x80000000 /* CHARGING# */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x80000000 /* CARRIER_STBY# */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x80000000 /* BATLOW# */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x80000000 /* SDIO_PWR_EN */ + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x80000000 /* LCD POWER */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x80000000 /* RESET_OUT# */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x80000000 /* ENET1_INT# */ + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x80000000 /* ENET2_INT# */ + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* WDT_TIME_OUT# */ + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d /* eMMC_Reset# */ + >; + }; + + pinctrl_ecspi1_cs: ecspi1_cs_grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x14 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_ecspi2_cs: ecspi2_cs_grp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x2 + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x2 + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x2 + >; + }; + + pinctrl_ecspi3_cs: ecspi3_cs_grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x14 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x14 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4grp_gpio { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x7f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x7f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai1_mclk: sai1grp_mclk { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x79 + MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x79 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x79 + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x79 + MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + >; + }; + + pinctrl_usbotg2_pwr_1: usbotg2-1 { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + }; +}; diff --git a/arch/arm/dts/imx7s-smarcfimx7.dts b/arch/arm/dts/imx7s-smarcfimx7.dts new file mode 100644 index 0000000..a47fc4b --- /dev/null +++ b/arch/arm/dts/imx7s-smarcfimx7.dts @@ -0,0 +1,977 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "imx7s.dtsi" + +/ { + model = "Embedian i.MX7S SMARC 2.0 Module"; + compatible = "fsl,imx7s-smarcfimx7", "fsl,imx7s"; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_aud_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "aud-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ + pwms = <&pwm2 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; + + sound { + compatible = "fsl,imx7d-smarcfimx7-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +/* SPI0 */ +&ecspi1 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>, <&gpio4 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + dmas = <&sdma 36 4 0>, <&sdma 37 4 0>; + dma-names = "rx", "tx"; + status = "okay"; + + spidev1: spidev@0 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <0>; + }; + spidev2: spidev@1 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <1>; + }; +}; + +/* SPINOR */ +&ecspi2 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + dmas = <&sdma 38 4 0>, <&sdma 39 4 0>; + dma-names = "rx", "tx"; + status = "okay"; + + flash: mx25u3235f@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25u3235f", "jedec,spi-nor"; + spi-max-frequency = <24000000>; + reg = <0>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "U-Boot Environment"; + reg = <0x100000 0x080000>; + }; + + partition@180000 { + label = "Flattened Device Tree"; + reg = <0x180000 0x200000>; + }; + + }; +}; + +/* ECSPI */ +&ecspi3 { + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; + cs-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>, <&gpio5 9 GPIO_ACTIVE_HIGH>; + dmas = <&sdma 40 4 0>, <&sdma 41 4 0>; + dma-names = "rx", "tx"; + status = "okay"; + + spidev3: spidev@0 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <0>; + }; + spidev4: spidev@4 { + compatible = "spidev"; + spi-max-frequency = <24000000>; + reg = <1>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_vref_1v8>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_vref_1v8>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + + cape_eeprom0: cape_eeprom@57 { + compatible = "at,24c256"; + reg = <0x57>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; + VDDA-supply = <®_aud_3v3>; + VDDIO-supply = <®_vref_1v8>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + enable-gpios = <&gpio3 4 0>; /* Enable LCD_VDD_EN pin */ + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + /*timing0: g070vw01 {*/ + timing0: timing0 { + clock-frequency = <33300000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <64>; + hback-porch = <64>; + hsync-len = <128>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-smarcfimx7 { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x30 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; + }; +}; + +/* SER0/UART6 */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* SER1/UART2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +/* SER2/UART7 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* SER3/UART3 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + gpios = <&gpio1 4 2>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + vmmc-supply = <®_sd1_vmmc>; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-smarcfimx7 { + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__GPIO5_IO13 0x80000000 /* lvds channel select */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pcie_wake# */ + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x80000000 /* GPIO0 */ + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x80000000 /* GPIO1 */ + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x80000000 /* GPIO2 */ + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x80000000 /* GPIO3 */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x80000000 /* GPIO4 */ + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x80000000 /* GPIO6 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x80000000 /* GPIO7 */ + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x80000000 /* GPIO8 */ + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x80000000 /* GPIO9 */ + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x80000000 /* GPIO10 */ + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x80000000 /* GPIO11 */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x80000000 /* SLEEP# */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x80000000 /* CHARGER_PRSNT# */ + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x80000000 /* CHARGING# */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x80000000 /* CARRIER_STBY# */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x80000000 /* BATLOW# */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x80000000 /* SDIO_PWR_EN */ + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x80000000 /* LCD POWER */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x80000000 /* RESET_OUT# */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x80000000 /* ENET1_INT# */ + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x80000000 /* ENET2_INT# */ + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* WDT_TIME_OUT# */ + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d /* eMMC_Reset# */ + >; + }; + + pinctrl_ecspi1_cs: ecspi1_cs_grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x14 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_ecspi2_cs: ecspi2_cs_grp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x2 + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x2 + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x2 + >; + }; + + pinctrl_ecspi3_cs: ecspi3_cs_grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x14 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x14 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4grp_gpio { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x7f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x7f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai1_mclk: sai1grp_mclk { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x79 + MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x79 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x79 + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x79 + MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + }; +}; diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index 5c5f27a..4c8db68 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -80,11 +80,10 @@ serial4 = &uart5; serial5 = &uart6; serial6 = &uart7; - spi1 = &qspi1; - spi2 = &ecspi1; - spi3 = &ecspi2; - spi4 = &ecspi3; - spi5 = &ecspi4; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; usb0 = &usbotg1; }; diff --git a/arch/arm/include/asm/arch-mx7/imx-rdc.h b/arch/arm/include/asm/arch-mx7/imx-rdc.h index dbeed56..2d65977 100644 --- a/arch/arm/include/asm/arch-mx7/imx-rdc.h +++ b/arch/arm/include/asm/arch-mx7/imx-rdc.h @@ -7,7 +7,7 @@ #ifndef __IMX_RDC_H__ #define __IMX_RDC_H__ -#if defined(CONFIG_MX7D) +#if defined(CONFIG_MX7D) || defined(CONFIG_MX7S) #include "mx7d_rdc.h" #else #error "Please select cpu" diff --git a/arch/arm/mach-imx/init.c b/arch/arm/mach-imx/init.c index 0aa8295..5607e97 100644 --- a/arch/arm/mach-imx/init.c +++ b/arch/arm/mach-imx/init.c @@ -70,7 +70,7 @@ void imx_wdog_disable_powerdown(void) struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; -#ifdef CONFIG_MX7D +#if defined(CONFIG_MX7D) || defined(CONFIG_MX7S) struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR; #endif @@ -80,7 +80,7 @@ void imx_wdog_disable_powerdown(void) if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7()) writew(0, &wdog3->wmcr); -#ifdef CONFIG_MX7D +#if defined(CONFIG_MX7D) || defined(CONFIG_MX7S) writew(0, &wdog4->wmcr); #endif } diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 242be59..726993f 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -16,6 +16,12 @@ config MX7D imply CMD_FUSE bool +config MX7S + select HAS_CAAM + select ROM_UNIFIED_SECTIONS + imply CMD_FUSE + bool + config IMX_TAMPER bool "Enable commands for SNVS tamper pin configuration and test" help @@ -39,6 +45,13 @@ config TARGET_MX7DSABRESD select DM select DM_THERMAL +config TARGET_SMARCFIMX7 + bool "smarcfimx7" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + config TARGET_MX7D_12X12_LPDDR3_ARM2 bool "Support mx7d_12x12_lpddr3_arm2" select BOARD_LATE_INIT @@ -107,6 +120,7 @@ endchoice config SYS_SOC default "mx7" +source "board/embedian/smarcfimx7/Kconfig" source "board/compulab/cl-som-imx7/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig" diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 4c95b30..8db141a 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -323,7 +323,7 @@ void reset_misc(void) } #ifdef CONFIG_IMX_TRUSTY_OS -#ifdef CONFIG_MX7D +#ifdef (CONFIG_MX7D)||(CONFIG_MX7S) void smp_set_core_boot_addr(unsigned long addr, int corenr) { return; diff --git a/board/embedian/smarcfimx7/Kconfig b/board/embedian/smarcfimx7/Kconfig new file mode 100644 index 0000000..6831ca8 --- /dev/null +++ b/board/embedian/smarcfimx7/Kconfig @@ -0,0 +1,14 @@ +if TARGET_SMARCFIMX7 + +config SYS_BOARD + default "smarcfimx7" + +config SYS_VENDOR + default "embedian" + +config SYS_CONFIG_NAME + default "smarcfimx7" + +config SYS_TEXT_BASE + default 0x87800000 +endif diff --git a/board/embedian/smarcfimx7/MAINTAINERS b/board/embedian/smarcfimx7/MAINTAINERS new file mode 100644 index 0000000..597b5f4 --- /dev/null +++ b/board/embedian/smarcfimx7/MAINTAINERS @@ -0,0 +1,14 @@ +SMARCFIMX7D BOARD +M: Eric Lee +S: Maintained +F: board/embedian/smarcfimx7 +F: include/configs/smarcfimx7.h +F: include/configs/mx7smarc_common.h +F: configs/smarcfimx7d_ser0_defconfig +F: configs/smarcfimx7d_ser1_defconfig +F: configs/smarcfimx7d_ser2_defconfig +F: configs/smarcfimx7d_ser3_defconfig +F: configs/smarcfimx7s_ser0_defconfig +F: configs/smarcfimx7s_ser1_defconfig +F: configs/smarcfimx7s_ser2_defconfig +F: configs/smarcfimx7s_ser3_defconfig diff --git a/board/embedian/smarcfimx7/Makefile b/board/embedian/smarcfimx7/Makefile new file mode 100644 index 0000000..e142357 --- /dev/null +++ b/board/embedian/smarcfimx7/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ../../freescale/common/mmc.o smarcfimx7.o diff --git a/board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg b/board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg new file mode 100644 index 0000000..aaeeb05 --- /dev/null +++ b/board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM spi + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* IOMUXC_GPR_GPR1 */ +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000002 +/* DDRC_MSTR */ +DATA 4 0x307a0000 0x01040001 +/* DDRC_DFIUPD0 */ +DATA 4 0x307a01a0 0x80400003 +/* DDRC_DFIUPD1 */ +DATA 4 0x307a01a4 0x00100020 +/* DDRC_DFIUPD2 */ +DATA 4 0x307a01a8 0x80100004 +/* DDRC_RFSHTMG */ +DATA 4 0x307a0064 0x00400046 +/* DDRC_MP_PCTRL_0 */ +DATA 4 0x307a0490 0x00000001 +/* DDRC_INIT0 */ +DATA 4 0x307a00d0 0x00020083 +/* DDRC_INIT1 */ +DATA 4 0x307a00d4 0x00690000 +/* DDRC_INIT3 MR0/MR1 */ +DATA 4 0x307a00dc 0x09300004 +/* DDRC_INIT4 MR2/MR3 */ +DATA 4 0x307a00e0 0x04080000 +/* DDRC_INIT5 */ +DATA 4 0x307a00e4 0x00100004 +/* DDRC_RANKCTL */ +DATA 4 0x307a00f4 0x0000033f +/* DDRC_DRAMTMG0 */ +DATA 4 0x307a0100 0x09081109 +/* DDRC_DRAMTMG1 */ +DATA 4 0x307a0104 0x0007020d +/* DDRC_DRAMTMG2 */ +DATA 4 0x307a0108 0x03040407 +/* DDRC_DRAMTMG3 */ +DATA 4 0x307a010c 0x00002006 +/* DDRC_DRAMTMG4 */ +DATA 4 0x307a0110 0x04020205 +/* DDRC_DRAMTMG5 */ +DATA 4 0x307a0114 0x03030202 +/* DDRC_DRAMTMG8 */ +DATA 4 0x307a0120 0x00000803 +/* DDRC_ZQCTL0 */ +DATA 4 0x307a0180 0x00800020 +/* DDRC_ZQCTL1 */ +DATA 4 0x307a0184 0x02001000 +/* DDRC_DFITMG0 */ +DATA 4 0x307a0190 0x02098204 +/* DDRC_DFITMG1 */ +DATA 4 0x307a0194 0x00030303 +/* DDRC_ADDRMAP0 */ +DATA 4 0x307a0200 0x0000001f +/* DDRC_ADDRMAP1 */ +DATA 4 0x307a0204 0x00080808 +/* DDRC_ADDRMAP4 */ +DATA 4 0x307a0210 0x00000f0f +/* DDRC_ADDRMAP5 */ +DATA 4 0x307a0214 0x07070707 +/* DDRC_ADDRMAP6 */ +DATA 4 0x307a0218 0x0f070707 +/* DDRC_ODTCFG */ +DATA 4 0x307a0240 0x06000604 +/* DDRC_ODTMAP */ +DATA 4 0x307a0244 0x00000001 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000000 +/* DDR_PHY_PHY_CON0 */ +DATA 4 0x30790000 0x17420f40 +/* DDR_PHY_PHY_CON1 */ +DATA 4 0x30790004 0x10210100 +/* DDR_PHY_PHY_CON4 */ +DATA 4 0x30790010 0x00060807 +/* DDR_PHY_MDLL_CON0 */ +DATA 4 0x307900b0 0x1010007e +/* DDR_PHY_DRVDS_CON0 */ +DATA 4 0x3079009c 0x00000d6e +/* DDR_PHY_OFFSET_RD_CON0 */ +DATA 4 0x30790020 0x0a0a0a0a +/* DDR_PHY_OFFSET_WR_CON0 */ +DATA 4 0x30790030 0x04040404 +/* DDR_PHY_OFFSETD_CON0 */ +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +/* DDR_PHY_ZQ_CON1 */ +CHECK_BITS_SET 4 0x307900c4 0x1 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000000 +/* IOMUXC_GPR_GPR8 */ +DATA 4 0x30340020 0x00000178 +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000002 +/* DDR_PHY_LP_CON0 */ +DATA 4 0x30790018 0x0000000f + +/* DDRC_STAT */ +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/embedian/smarcfimx7/ddr3l/mx7d_2x_mt41k512m16ha.cfg b/board/embedian/smarcfimx7/ddr3l/mx7d_2x_mt41k512m16ha.cfg new file mode 100644 index 0000000..78467b7 --- /dev/null +++ b/board/embedian/smarcfimx7/ddr3l/mx7d_2x_mt41k512m16ha.cfg @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM spi + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* IOMUXC_GPR_GPR1 */ +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000002 +/* DDRC_MSTR */ +DATA 4 0x307a0000 0x01040001 +/* DDRC_DFIUPD0 */ +DATA 4 0x307a01a0 0x80400003 +/* DDRC_DFIUPD1 */ +DATA 4 0x307a01a4 0x00100020 +/* DDRC_DFIUPD2 */ +DATA 4 0x307a01a8 0x80100004 +/* DDRC_RFSHTMG */ +DATA 4 0x307a0064 0x0040005e +/* DDRC_MP_PCTRL_0 */ +DATA 4 0x307a0490 0x00000001 +/* DDRC_INIT0 */ +DATA 4 0x307a00d0 0x00020083 +/* DDRC_INIT1 */ +DATA 4 0x307a00d4 0x00690000 +/* DDRC_INIT2 */ +DATA 4 0x307a00d8 0x00000000 +/* DDRC_INIT3 MR0/MR1 */ +DATA 4 0x307a00dc 0x09300004 +/* DDRC_INIT4 MR2/MR3 */ +DATA 4 0x307a00e0 0x04080000 +/* DDRC_INIT5 */ +DATA 4 0x307a00e4 0x00100004 +/* DDRC_RANKCTL */ +DATA 4 0x307a00f4 0x0000033f +/* DDRC_DRAMTMG0 */ +DATA 4 0x307a0100 0x090a1109 +/* DDRC_DRAMTMG1 */ +DATA 4 0x307a0104 0x0007020d +/* DDRC_DRAMTMG2 */ +DATA 4 0x307a0108 0x03040407 +/* DDRC_DRAMTMG3 */ +DATA 4 0x307a010c 0x00002006 +/* DDRC_DRAMTMG4 */ +DATA 4 0x307a0110 0x04020205 +/* DDRC_DRAMTMG5 */ +DATA 4 0x307a0114 0x03030202 +/* DDRC_DRAMTMG8 */ +DATA 4 0x307a0120 0x00000803 +/* DDRC_ZQCTL0 */ +DATA 4 0x307a0180 0x00800020 +/* DDRC_DFITMG0 */ +DATA 4 0x307a0190 0x02098204 +/* DDRC_DFITMG1 */ +DATA 4 0x307a0194 0x00030303 +/* DDRC_ADDRMAP0 */ +DATA 4 0x307a0200 0x0000001f +/* DDRC_ADDRMAP1 */ +DATA 4 0x307a0204 0x00181818 +/* DDRC_ADDRMAP4 */ +DATA 4 0x307a0210 0x00000f0f +/* DDRC_ADDRMAP5 */ +DATA 4 0x307a0214 0x04040404 +/* DDRC_ADDRMAP6 */ +DATA 4 0x307a0218 0x04040404 +/* DDRC_ODTCFG */ +DATA 4 0x307a0240 0x06000604 +/* DDRC_ODTMAP */ +DATA 4 0x307a0244 0x00000001 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000000 +/* DDR_PHY_PHY_CON0 */ +DATA 4 0x30790000 0x17420f40 +/* DDR_PHY_PHY_CON1 */ +DATA 4 0x30790004 0x10210100 +/* DDR_PHY_PHY_CON4 */ +DATA 4 0x30790010 0x00060807 +/* DDR_PHY_MDLL_CON0 */ +DATA 4 0x307900b0 0x1010007e +/* DDR_PHY_DRVDS_CON0 */ +DATA 4 0x3079009c 0x00000d6e +/* DDR_PHY_OFFSET_RD_CON0 */ +DATA 4 0x30790020 0x0c0c0c0c +/* DDR_PHY_OFFSET_WR_CON0 */ +DATA 4 0x30790030 0x04040404 +/* DDR_PHY_OFFSETD_CON0 */ +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +/* DDR_PHY_ZQ_CON1 */ +CHECK_BITS_SET 4 0x307900c4 0x1 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000000 +/* IOMUXC_GPR_GPR8 */ +DATA 4 0x30340020 0x00000178 +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000002 +/* DDR_PHY_LP_CON0 */ +DATA 4 0x30790018 0x0000000f + +/* DDRC_STAT */ +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg b/board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg new file mode 100644 index 0000000..44e6f38 --- /dev/null +++ b/board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM spi + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* IOMUXC_GPR_GPR1 */ +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000002 +/* DDRC_MSTR */ +DATA 4 0x307a0000 0x01040001 +/* DDRC_DFIUPD0 */ +DATA 4 0x307a01a0 0x80400003 +/* DDRC_DFIUPD1 */ +DATA 4 0x307a01a4 0x00100020 +/* DDRC_DFIUPD2 */ +DATA 4 0x307a01a8 0x80100004 +/* DDRC_RFSHTMG */ +DATA 4 0x307a0064 0x00400046 +/* DDRC_MP_PCTRL_0 */ +DATA 4 0x307a0490 0x00000001 +/* DDRC_INIT0 */ +DATA 4 0x307a00d0 0x00020083 +/* DDRC_INIT1 */ +DATA 4 0x307a00d4 0x00690000 +/* DDRC_INIT3 MR0/MR1 */ +DATA 4 0x307a00dc 0x09300004 +/* DDRC_INIT4 MR2/MR3 */ +DATA 4 0x307a00e0 0x04080000 +/* DDRC_INIT5 */ +DATA 4 0x307a00e4 0x00100004 +/* DDRC_RANKCTL */ +DATA 4 0x307a00f4 0x0000033f +/* DDRC_DRAMTMG0 */ +DATA 4 0x307a0100 0x09081109 +/* DDRC_DRAMTMG1 */ +DATA 4 0x307a0104 0x0007020d +/* DDRC_DRAMTMG2 */ +DATA 4 0x307a0108 0x03040407 +/* DDRC_DRAMTMG3 */ +DATA 4 0x307a010c 0x00002006 +/* DDRC_DRAMTMG4 */ +DATA 4 0x307a0110 0x04020205 +/* DDRC_DRAMTMG5 */ +DATA 4 0x307a0114 0x03030202 +/* DDRC_DRAMTMG8 */ +DATA 4 0x307a0120 0x00000803 +/* DDRC_ZQCTL0 */ +DATA 4 0x307a0180 0x00800020 +/* DDRC_ZQCTL1 */ +DATA 4 0x307a0184 0x02001000 +/* DDRC_DFITMG0 */ +DATA 4 0x307a0190 0x02098204 +/* DDRC_DFITMG1 */ +DATA 4 0x307a0194 0x00030303 +/* DDRC_ADDRMAP0 */ +DATA 4 0x307a0200 0x0000001f +/* DDRC_ADDRMAP1 */ +DATA 4 0x307a0204 0x00080808 +/* DDRC_ADDRMAP4 */ +DATA 4 0x307a0210 0x00000f0f +/* DDRC_ADDRMAP5 */ +DATA 4 0x307a0214 0x07070707 +/* DDRC_ADDRMAP6 */ +DATA 4 0x307a0218 0x0f070707 +/* DDRC_ODTCFG */ +DATA 4 0x307a0240 0x06000604 +/* DDRC_ODTMAP */ +DATA 4 0x307a0244 0x00000001 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000000 +/* DDR_PHY_PHY_CON0 */ +DATA 4 0x30790000 0x17420f40 +/* DDR_PHY_PHY_CON1 */ +DATA 4 0x30790004 0x10210100 +/* DDR_PHY_PHY_CON4 */ +DATA 4 0x30790010 0x00060807 +/* DDR_PHY_MDLL_CON0 */ +DATA 4 0x307900b0 0x1010007e +/* DDR_PHY_DRVDS_CON0 */ +DATA 4 0x3079009c 0x00000d6e +/* DDR_PHY_OFFSET_RD_CON0 */ +DATA 4 0x30790020 0x0c0c0c0c +/* DDR_PHY_OFFSET_WR_CON0 */ +DATA 4 0x30790030 0x04040404 +/* DDR_PHY_OFFSETD_CON0 */ +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +/* DDR_PHY_ZQ_CON1 */ +CHECK_BITS_SET 4 0x307900c4 0x1 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000000 +/* IOMUXC_GPR_GPR8 */ +DATA 4 0x30340020 0x00000178 +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000002 +/* DDR_PHY_LP_CON0 */ +DATA 4 0x30790018 0x0000000f + +/* DDRC_STAT */ +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/embedian/smarcfimx7/plugin.S b/board/embedian/smarcfimx7/plugin.S new file mode 100644 index 0000000..1f64e46 --- /dev/null +++ b/board/embedian/smarcfimx7/plugin.S @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_sabresd_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x30340024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_sabresd_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/embedian/smarcfimx7/smarcfimx7.c b/board/embedian/smarcfimx7/smarcfimx7.c new file mode 100644 index 0000000..8ca6573 --- /dev/null +++ b/board/embedian/smarcfimx7/smarcfimx7.c @@ -0,0 +1,1012 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../freescale/common/pfuze.h" +#include +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define EPDC_PAD_CTRL 0x0 + +#define WEAK_PULLUP (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +#ifdef CONFIG_MXC_SPI +/* SPI2 (SPINOR) */ +static iomux_v3_cfg_t const ecspi2_pads[] = { + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + gpio_request(IMX_GPIO_NR(4, 23), "espi2_cs0"); + return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 23)) : -1; +} + +static void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); +} +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* SER0/UART6 */ +static iomux_v3_cfg_t const uart6_pads[] = { + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* SER1/UART2 */ +static iomux_v3_cfg_t const uart2_pads[] = { + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* SER2/UART7 */ +static iomux_v3_cfg_t const uart7_pads[] = { + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* SER3/UART3 Debug Port */ +static iomux_v3_cfg_t const uart3_pads[] = { + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* RESET_OUT# */ +static iomux_v3_cfg_t const reset_out_pads[] = { + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* SPI0 */ +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ + MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ +}; + +/* ESPI */ +static iomux_v3_cfg_t const ecspi3_pads[] = { + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ + MX7D_PAD_SD2_CD_B__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ +}; + +/* CAN0/FLEXCAN1 */ +static iomux_v3_cfg_t const flexcan1_pads[] = { + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP), + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP), +}; + +/* CAN1/FLEXCAN2 */ +static iomux_v3_cfg_t const flexcan2_pads[] = { + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP), + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP), +}; + +/* GPIOs */ +static iomux_v3_cfg_t const gpios_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */ + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */ + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */ + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */ + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */ + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */ + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */ + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */ + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */ +}; + +/* LVDS channel selection, set low as single channel LVDS and high as dual channel LVDS */ +static iomux_v3_cfg_t const lvds_ch_sel_pads[] = { + MX7D_PAD_SD2_CMD__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), /* LVDS_CH_SEL */ +}; + +/* Misc. pins */ +static iomux_v3_cfg_t const misc_pads[] = { + MX7D_PAD_SD2_DATA0__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* SLEEP# */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGER_PRSNT# */ + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGING# */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_STBY# */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* BATLOW# */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_RST# */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_WAKE# */ + MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WDT_TIME_OUT# */ +}; + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* NAND_USDHC_BUS_CLK is set in rom */ + set_clk_nand(); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight Enable for RGB: S127 */ + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), + + /* PWM Backlight Control: S141. Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + + /* Reset LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Turn on Backlight */ + gpio_request(IMX_GPIO_NR(6, 17), "backlight_enable"); + gpio_direction_output(IMX_GPIO_NR(6, 17), 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 2), "backlight_pwm"); + gpio_direction_output(IMX_GPIO_NR(1, 2) , 1); +} + +/* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */ +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "G070VW01", + .xres = 800, + .yres = 480, + .pixclock = 31069, + .left_margin = 64, + .right_margin = 64, + .upper_margin = 12, + .lower_margin = 4, + .hsync_len = 128, + .vsync_len = 12, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +static void setup_iomux_uart6(void) +{ + imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads)); +} + +static void setup_iomux_uart2(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +static void setup_iomux_uart7(void) +{ + imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads)); +} + +static void setup_iomux_uart3(void) +{ + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} + +static void setup_iomux_reset_out(void) +{ + imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); + + /* Set CPU RESET_OUT as Output */ + gpio_request(IMX_GPIO_NR(2, 29), "reset_out"); + gpio_direction_output(IMX_GPIO_NR(2, 29) , 0); +} + +static void setup_iomux_spi1(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 19), "spi1_cs0"); + gpio_direction_output(IMX_GPIO_NR(4, 19), 0); + gpio_request(IMX_GPIO_NR(4, 0), "spi1_cs1"); + gpio_direction_output(IMX_GPIO_NR(4, 0), 0); +} + +static void setup_iomux_spi3(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); + gpio_request(IMX_GPIO_NR(6, 22), "spi3_cs0"); + gpio_direction_output(IMX_GPIO_NR(6, 22), 0); + gpio_request(IMX_GPIO_NR(5, 9), "spi3_cs2"); + gpio_direction_output(IMX_GPIO_NR(5, 9), 0); +} + +static void setup_iomux_gpios(void) +{ + imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads)); + gpio_request(IMX_GPIO_NR(2, 0), "GPIO0"); + gpio_direction_output(IMX_GPIO_NR(2, 0), 0); + gpio_request(IMX_GPIO_NR(2, 1), "GPIO1"); + gpio_direction_output(IMX_GPIO_NR(2, 1), 0); + gpio_request(IMX_GPIO_NR(2, 2), "GPIO2"); + gpio_direction_output(IMX_GPIO_NR(2, 2), 0); + gpio_request(IMX_GPIO_NR(2, 3), "GPIO3"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 0); + gpio_request(IMX_GPIO_NR(2, 4), "GPIO4"); + gpio_direction_output(IMX_GPIO_NR(2, 4), 0); + gpio_request(IMX_GPIO_NR(2, 5), "GPIO6"); + gpio_direction_input(IMX_GPIO_NR(2, 5)); + gpio_request(IMX_GPIO_NR(2, 7), "GPIO7"); + gpio_direction_input(IMX_GPIO_NR(2, 7)); + gpio_request(IMX_GPIO_NR(2, 6), "GPIO8"); + gpio_direction_input(IMX_GPIO_NR(2, 6)); + gpio_request(IMX_GPIO_NR(4, 1), "GPIO9"); + gpio_direction_input(IMX_GPIO_NR(4, 1)); + gpio_request(IMX_GPIO_NR(4, 6), "GPIO10"); + gpio_direction_input(IMX_GPIO_NR(4, 6)); + gpio_request(IMX_GPIO_NR(4, 7), "GPIO11"); + gpio_direction_input(IMX_GPIO_NR(4, 7)); +} + +static void setup_iomux_lvds_ch_sel(void) +{ + imx_iomux_v3_setup_multiple_pads(lvds_ch_sel_pads, ARRAY_SIZE(lvds_ch_sel_pads)); + gpio_request(IMX_GPIO_NR(5, 13), "LVDS_CH_SEL"); + gpio_direction_output(IMX_GPIO_NR(5, 13), 0); +} + +static void setup_iomux_misc(void) +{ + imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); + gpio_request(IMX_GPIO_NR(5, 14), "SLEEP#"); + gpio_direction_input(IMX_GPIO_NR(5, 14)); + gpio_request(IMX_GPIO_NR(1, 8), "CHARGING#"); + gpio_direction_input(IMX_GPIO_NR(1, 8)); + gpio_request(IMX_GPIO_NR(1, 9), "CHARGER_PRSNT#"); + gpio_direction_input(IMX_GPIO_NR(1, 9)); + gpio_request(IMX_GPIO_NR(5, 11), "BATLOW#"); + gpio_direction_input(IMX_GPIO_NR(5, 11)); + gpio_request(IMX_GPIO_NR(6, 16), "CARRIER_STBY#"); + gpio_direction_output(IMX_GPIO_NR(6, 16), 1); + gpio_request(IMX_GPIO_NR(2, 28), "PCIE_RST#"); + gpio_direction_output(IMX_GPIO_NR(2, 28), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(2, 28), 1); + gpio_request(IMX_GPIO_NR(2, 31), "PCIE_WAKE#"); + gpio_direction_input(IMX_GPIO_NR(2, 31)); + /* Set WDT_TIME_OUT# as Output High */ + gpio_request(IMX_GPIO_NR(7, 14), "WDT_TIME_OUT#"); + gpio_direction_output(IMX_GPIO_NR(7, 14), 1); +} + +static void setup_iomux_flexcan1(void) +{ + imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads)); +} + +static void setup_iomux_flexcan2(void) +{ + imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads)); +} + +int board_mmc_get_env_dev(int devno) +{ + if (devno == 2) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (dev_no == 1) + dev_no++; + + return dev_no; +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + if (0 == fec_id) { + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + } else { + /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + } + + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + /*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/ + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); +#endif + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_EPDC +iomux_v3_cfg_t const epdc_en_pads[] = { + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 31)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom"); + gpio_direction_output(IMX_GPIO_NR(4, 14), 1); + + /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 23), "epdc_pmic"); + gpio_direction_output(IMX_GPIO_NR(2, 23), 1); + + /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 30), "epdc_pwr_ctl0"); + gpio_direction_output(IMX_GPIO_NR(2, 30), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 30), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 23), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 23), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 30), 0); +} +#endif + +static void setup_usb(void) +{ + /* OTG1 Over Current */ + gpio_request(IMX_GPIO_NR(1, 4), "OTG1_OC"); + gpio_direction_input(IMX_GPIO_NR(1, 4)); + gpio_request(IMX_GPIO_NR(1, 5), "OTG1_PWR"); + gpio_direction_output(IMX_GPIO_NR(1, 5), 1); + /* OTG2 */ + gpio_request(IMX_GPIO_NR(1, 6), "OTG2_OC"); + gpio_direction_input(IMX_GPIO_NR(1, 6)); + gpio_request(IMX_GPIO_NR(1, 7), "OTG2_PWR"); + gpio_direction_output(IMX_GPIO_NR(1, 7), 1); +} + +int board_early_init_f(void) +{ + setup_iomux_uart6(); + setup_iomux_uart2(); + setup_iomux_uart7(); + setup_iomux_uart3(); + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + + setup_iomux_flexcan1(); + setup_iomux_flexcan2(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_EPDC + setup_epdc(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + /* TODO: Nand */ + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id; + u32 sw3mode; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + + /* change sw3 mode to avoid DDR power off */ + sw3mode = pmic_reg_read(dev, PFUZE3000_SW3MODE); + ret = pmic_reg_write(dev, PFUZE3000_SW3MODE, sw3mode | 0x20); + if (ret < 0) + printf("PMIC: PFUZE3000 change sw3 mode failed\n"); + + return 0; +} +#endif + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); + + puts("---------Embedian SMARC-FiMX7------------\n"); + /* Read Module Information from on module EEPROM and pass + * mac address to kernel + */ + struct udevice *dev; + int ret; + u8 name[8]; + u8 serial[12]; + u8 revision[4]; + u8 mac[6]; + u8 mac1[6]; + + ret = i2c_get_chip_for_busnum(1, 0x50, 2, &dev); + if (ret) { + debug("failed to get eeprom\n"); + return 0; + } + + /* Board ID */ + ret = dm_i2c_read(dev, 0x4, name, 8); + if (ret) { + debug("failed to read board ID from EEPROM\n"); + return 0; + } + printf(" Board ID: %c%c%c%c%c%c%c%c\n", + name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); + + /* Board Hardware Revision */ + ret = dm_i2c_read(dev, 0xc, revision, 4); + if (ret) { + debug("failed to read hardware revison from EEPROM\n"); + return 0; + } + printf(" Hardware Revision: %c%c%c%c\n", + revision[0], revision[1], revision[2], revision[3]); + + /* Serial number */ + ret = dm_i2c_read(dev, 0x10, serial, 12); + if (ret) { + debug("failed to read srial number from EEPROM\n"); + return 0; + } + printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", + serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); + + /*MAC address*/ + ret = dm_i2c_read(dev, 0x3c, mac, 6); + if (ret) { + debug("failed to read eth0 mac address from EEPROM\n"); + return 0; + } + + if (is_valid_ethaddr(mac)) + printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + eth_env_set_enetaddr("ethaddr", mac); +#ifdef CONFIG_MX7D + ret = dm_i2c_read(dev, 0x42, mac1, 6); + if (ret) { + debug("failed to read eth1 mac address from EEPROM\n"); + return 0; + } + + if (is_valid_ethaddr(mac1)) + printf(" MAC1 Address: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac1[0], mac1[1], mac1[2], mac1[3], mac1[4], mac1[5]); + eth_env_set_enetaddr("eth1addr", mac1); +#endif + puts("-----------------------------------------\n"); + +/* RESET_OUT Pin */ + setup_iomux_reset_out(); +/* ECSPI1 CS Pins */ + setup_iomux_spi1(); +/* ECSPI3 CS Pins */ + setup_iomux_spi3(); +/* USB Power Control Pins */ + setup_usb(); +/* GPIO Pins */ + setup_iomux_gpios(); +/* LVDS Channel Selection Pin */ + setup_iomux_lvds_ch_sel(); +/* MISC Pins */ + setup_iomux_misc(); + +/* SDCARD POWER Enable */ + gpio_request(IMX_GPIO_NR(5, 2), "SDIO_PWR_EN"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + +/* eMMC Power Reset */ +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); + gpio_direction_output(USDHC3_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + +/* SMARC BOOT_SEL*/ + gpio_request(IMX_GPIO_NR(5, 15), "BOOT_SEL_1"); + gpio_request(IMX_GPIO_NR(5, 16), "BOOT_SEL_2"); + gpio_request(IMX_GPIO_NR(5, 17), "BOOT_SEL_3"); + + if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) { + puts("BOOT_SEL Detected: OFF OFF OFF, unsupported boot up device: SATA...\n"); + hang(); + } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) { + puts("BOOT_SEL Detected: OFF OFF ON, unsupported boot up device: NAND...\n"); + hang(); + } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) { + puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier eSPI...\n"); + hang(); + } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) { + puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); + env_set_ulong("mmcdev", 0); + env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;"); + } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) { + puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); + env_set_ulong("mmcdev", 1); + env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;"); + } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) { + puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); + env_set("bootcmd", "run netboot;"); + } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) { + puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier SPI...\n"); + hang(); + } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) { + puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); + env_set_ulong("mmcdev", 1); + env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;"); + } else { + puts("unsupported boot devices\n"); + hang(); + } + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +/* Use LID# for recovery key */ +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10) +iomux_v3_cfg_t const recovery_key_pads[] = { + (MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + + /* Check Recovery Combo Button press or not. */ + imx_iomux_v3_setup_multiple_pads(recovery_key_pads, + ARRAY_SIZE(recovery_key_pads)); + + gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/configs/smarcfimx7d_2g_ser0_defconfig b/configs/smarcfimx7d_2g_ser0_defconfig new file mode 100644 index 0000000..f124a51 --- /dev/null +++ b/configs/smarcfimx7d_2g_ser0_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D,2GDDR3" +CONFIG_CONSOLE_SER0=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7d_2g_ser1_defconfig b/configs/smarcfimx7d_2g_ser1_defconfig new file mode 100644 index 0000000..bb91d58 --- /dev/null +++ b/configs/smarcfimx7d_2g_ser1_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D,2GDDR3" +CONFIG_CONSOLE_SER1=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7d_2g_ser2_defconfig b/configs/smarcfimx7d_2g_ser2_defconfig new file mode 100644 index 0000000..7b48d70 --- /dev/null +++ b/configs/smarcfimx7d_2g_ser2_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D,2GDDR3" +CONFIG_CONSOLE_SER2=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7d_2g_ser3_defconfig b/configs/smarcfimx7d_2g_ser3_defconfig new file mode 100644 index 0000000..bda0016 --- /dev/null +++ b/configs/smarcfimx7d_2g_ser3_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D,2GDDR3" +CONFIG_CONSOLE_SER3=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7d_ser0_defconfig b/configs/smarcfimx7d_ser0_defconfig new file mode 100644 index 0000000..f0072eb --- /dev/null +++ b/configs/smarcfimx7d_ser0_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D" +CONFIG_CONSOLE_SER0=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7d_ser1_defconfig b/configs/smarcfimx7d_ser1_defconfig new file mode 100644 index 0000000..a5b3671 --- /dev/null +++ b/configs/smarcfimx7d_ser1_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D" +CONFIG_CONSOLE_SER1=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7d_ser2_defconfig b/configs/smarcfimx7d_ser2_defconfig new file mode 100644 index 0000000..5854967 --- /dev/null +++ b/configs/smarcfimx7d_ser2_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D" +CONFIG_CONSOLE_SER2=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7d_ser3_defconfig b/configs/smarcfimx7d_ser3_defconfig new file mode 100644 index 0000000..91be7e1 --- /dev/null +++ b/configs/smarcfimx7d_ser3_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7d-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg,MX7D" +CONFIG_CONSOLE_SER3=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7s_ser0_defconfig b/configs/smarcfimx7s_ser0_defconfig new file mode 100644 index 0000000..9425b24 --- /dev/null +++ b/configs/smarcfimx7s_ser0_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7s-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7s-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg,MX7S" +CONFIG_CONSOLE_SER0=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7s_ser1_defconfig b/configs/smarcfimx7s_ser1_defconfig new file mode 100644 index 0000000..46c2301 --- /dev/null +++ b/configs/smarcfimx7s_ser1_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7s-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7s-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg,MX7S" +CONFIG_CONSOLE_SER1=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7s_ser2_defconfig b/configs/smarcfimx7s_ser2_defconfig new file mode 100644 index 0000000..13ba5c7 --- /dev/null +++ b/configs/smarcfimx7s_ser2_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7s-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7s-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg,MX7S" +CONFIG_CONSOLE_SER2=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/configs/smarcfimx7s_ser3_defconfig b/configs/smarcfimx7s_ser3_defconfig new file mode 100644 index 0000000..d9e259a --- /dev/null +++ b/configs/smarcfimx7s_ser3_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_SMARCFIMX7=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_SYS_PROMPT="U-Boot# " +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7s-smarcfimx7" +CONFIG_DEFAULT_FDT_FILE="imx7s-smarcfimx7.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg,MX7S" +CONFIG_CONSOLE_SER3=y +CONFIG_SPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DOS_PARTITION=y +CONFIG_FS_EXT4=y +CONFIG_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_EFI_PARTITION=y diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 85762b8..6e8ec36 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -449,8 +449,8 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, if ((start + blkcnt) > block_dev->lba) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", - start + blkcnt, block_dev->lba); + /*pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", + start + blkcnt, block_dev->lba);*/ #endif return 0; } diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 9121332..a3276d2 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -80,6 +80,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, + {"mx25u3235f", INFO(0xc22536, 0x0, 64 * 1024, 64, 0 | SECT_4K) }, {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 47969f3..4cb234d 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -33,3 +33,8 @@ config STM32_SDRAM STM32F7 family devices support flexible memory controller(FMC) to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the FMC. + +config 2GDDR3 + bool "SMARC-FiMX7 with 2GB DDR3L Memory" + help + Select this if the board is SMARC-FiMX7-D-2G diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index e52a7e0..f4ed543 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -567,6 +567,26 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config CONSOLE_SER0 + bool "SMARC-FiMX7 default console serial output port" + help + Select this to enable a debug UART port from SER0 of SMARC-FiMX7. + +config CONSOLE_SER1 + bool "SMARC-FiMX7 default console serial output port" + help + Select this to enable a debug UART port from SER1 of SMARC-FiMX7. + +config CONSOLE_SER2 + bool "SMARC-FiMX7 default console serial output port" + help + Select this to enable a debug UART port from SER2 of SMARC-FiMX7. + +config CONSOLE_SER3 + bool "SMARC-FiMX7 default console serial output port" + help + Select this to enable a debug UART port from SER3 of SMARC-FiMX7. + config STI_ASC_SERIAL bool "STMicroelectronics on-chip UART" depends on DM_SERIAL && ARCH_STI diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 3f826d1..5fcec46 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -9,6 +9,7 @@ #include #include #include +#include #ifdef CONFIG_IMX_WATCHDOG void hw_watchdog_reset(void) @@ -43,7 +44,10 @@ void __attribute__((weak)) reset_cpu(ulong addr) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); + if ((is_cpu_type(MXC_CPU_MX7D) || is_cpu_type(MXC_CPU_MX7S))) + clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, (WCR_WDE | WCR_SRS)); + else + clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); writew(0x5555, &wdog->wsr); writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ diff --git a/include/configs/mx7smarc_common.h b/include/configs/mx7smarc_common.h new file mode 100644 index 0000000..949c887 --- /dev/null +++ b/include/configs/mx7smarc_common.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7SMARC_COMMON_H +#define __MX7SMARC_COMMON_H + +#include +#include +#include + +#ifndef CONFIG_MX7 +#define CONFIG_MX7 +#endif + +/* Timer settings */ +#define CONFIG_MXC_GPT_HCLK +#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +/* Enable iomux-lpsr support */ +#define CONFIG_IOMUX_LPSR + +#define CONFIG_LOADADDR 0x80800000 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#ifndef CONFIG_SYS_DCACHE_OFF +#endif + +/* UART */ +#define CONFIG_MXC_UART +#if defined(CONFIG_CONSOLE_SER0) +#define CONFIG_MXC_UART_BASE UART6_IPS_BASE_ADDR +#define CONSOLE_DEV "ttymxc5" +#endif +#if defined(CONFIG_COMSOLE_SER1) +#define CONFIG_MXC_UART_BASE UART2_IPS_BASE_ADDR +#define CONSOLE_DEV "ttymxc1" +#endif +#if defined(CONFIG_CONSOLE_SER2) +#define CONFIG_MXC_UART_BASE UART7_IPS_BASE_ADDR +#define CONSOLE_DEV "ttymxc6" +#endif +#if defined(CONFIG_CONSOLE_SER3) +#define CONFIG_MXC_UART_BASE UART3_IPS_BASE_ADDR +#define CONSOLE_DEV "ttymxc2" +#endif + +/* MMC */ +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +/* Fuses */ +#define CONFIG_MXC_OCOTP + +#define CONFIG_ARMV7_SECURE_BASE 0x00900000 + +#define CONFIG_ARMV7_PSCI_1_0 + +/* Secure boot (HAB) support */ +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x4000 +#endif + +#ifdef CONFIG_IMX_OPTEE +#define TEE_ENV "tee=yes\0" +#else +#define TEE_ENV "tee=no\0" +#endif +#endif diff --git a/include/configs/smarcfimx7.h b/include/configs/smarcfimx7.h new file mode 100644 index 0000000..868a764 --- /dev/null +++ b/include/configs/smarcfimx7.h @@ -0,0 +1,415 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * Configuration settings for the Freescale i.MX7D SABRESD board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SMARCFIMX7_CONFIG_H +#define __SMARCFIMX7_CONFIG_H + +#include "mx7smarc_common.h" +#include "imx_env.h" + +#define CONFIG_DBG_MONITOR + +#if defined(CONFIG_MX7D) +#if defined(CONFIG_2GDDR3) +#define PHYS_SDRAM_SIZE SZ_2G +#else +#define PHYS_SDRAM_SIZE SZ_1G +#endif +#else +#define PHYS_SDRAM_SIZE SZ_512M +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* Network */ +#ifdef CONFIG_DM_ETH +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_ENET_DEV 0 + +#define CONFIG_PHY_ATHEROS +/* ENET1 */ +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x6 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x7 +#define CONFIG_ETHPRIME "eth1" +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR +#endif + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#define CONFIG_CMD_IMPORTENV + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_NAND_BOOT +#define CONFIG_NAND_MXS +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 /* Use SPI2 SS0 as chip select */ +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#ifdef CONFIG_IMX_BOOTAUX + +#ifdef CONFIG_FSL_QSPI +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 1:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x100000 ${fw_sz}; " \ + "sf write ${loadaddr} 0x100000 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)" ${m4image}\0" \ + "m4boot=run loadm4image; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#endif +#else +#define UPDATE_M4_ENV "" +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0"\ + "sd_dev=0\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=image raw 0 0x800000;"\ + "u-boot raw 0 0x4000;"\ + "bootimg part 0 1;"\ + "rootfs part 0 2\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${teeaddr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + CONFIG_DFU_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=" CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-7dsdb\0" \ + "ethprime=eth0\0" \ + "ipaddr=192.168.1.60\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "panel=G070VW01\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "${optargs} " \ + "rootfstype=${mmcrootfstype} " \ + "root=${mmcroot}\0" \ + "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadzimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi; " \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx7d-sdb.dtb; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "run importbootenv;" \ + "fi;" \ + "echo Checking if uenvcmd is set ...;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "echo Running default loadzimage ...;" \ + "if run loadzimage; then " \ + "run loadfdt;" \ + "run mmcboot;" \ + "fi;" \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ +#define CONFIG_ENV_SIZE SZ_8K + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60100000 /* Set to QSPI1 A flash, offset 1M */ +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x7F8000 /* Set to TCML address */ +#endif +/* + * If want to use nand, define CONFIG_CMD_NAND and rework board + * to support nand, since emmc has pin conflicts with nand + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */ + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#define CONFIG_IMX_THERMAL + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI) +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!" +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 1 /* SOFT SPI occupies the BUS 0, so change the QSPI1 to BUS 1*/ +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR +#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "smarcfimx7android.h" +#elif defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "smarcfimx7_androidthings.h" +#else +#define CONFIG_USBD_HS +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/smarcfimx7_androidthings.h b/include/configs/smarcfimx7_androidthings.h new file mode 100644 index 0000000..a2387c2 --- /dev/null +++ b/include/configs/smarcfimx7_androidthings.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SMARCFIMX7_ANDROIDTHINGS_H +#define __SMARCFIMX7_ANDROIDTHINGS_H +#include "mx_android_common.h" + +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_ANDROID_AB_SUPPORT +#define FASTBOOT_ENCRYPT_LOCK + +#define CONFIG_SHA1 +#define CONFIG_SHA256 + + +#ifdef CONFIG_SYS_MMC_ENV_DEV +#undef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#endif + +#ifdef CONFIG_SYS_MMC_ENV_PART +#undef CONFIG_SYS_MMC_ENV_PART +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */ +#endif + +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +/* infact 7D have no enough bits + * set this size to 0 will disable + * program/read FUSE */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 0 +#define CONFIG_AVB_FUSE_BANK_START 0 +#define CONFIG_AVB_FUSE_BANK_END 0 +#endif + +#endif + diff --git a/include/configs/smarcfimx7android.h b/include/configs/smarcfimx7android.h new file mode 100644 index 0000000..06d8933 --- /dev/null +++ b/include/configs/smarcfimx7android.h @@ -0,0 +1,38 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SMARCFIMX7_ANDROID_H +#define __SMARCFIMX7_ANDROID_H +#include "mx_android_common.h" + +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +/* lock/unlock stuff */ +#define FASTBOOT_ENCRYPT_LOCK +#define CONFIG_FASTBOOT_LOCK +#define FSL_FASTBOOT_FB_DEV "mmc" +#define CONFIG_SHA1 + +#define CONFIG_AVB_SUPPORT +#ifdef CONFIG_AVB_SUPPORT +#define CONFIG_ANDROID_RECOVERY + +#ifdef CONFIG_SYS_CBSIZE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 +#endif + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (96 * SZ_1M) +#endif + +#endif /* CONFIG_AVB_SUPPORT */ + +#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED + +#endif /* __SMARCFIMX7_ANDROID_H */ diff --git a/qspi_header b/qspi_header new file mode 100644 index 0000000..d4f3c12 --- /dev/null +++ b/qspi_header @@ -0,0 +1,128 @@ +0 /*dqs_loopback=0 or 1*/ +0 /*hold_delay=0 to 3*/ +0 /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/ +0 /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/ +0 /*device_quad_mode_en=1 to enable sending command to SPI device*/ +0 /*device_cmd=command to device for enableing Quad I/O mode*/ +0 /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/ +2000000 /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/ +3 /*cs_hold_time=0 to 0xF*/ +3 /*cs_setup_time=0 to 0xF*/ +8000000 /*sflash_A1_size=size in byte(hex)*/ +0 /*sflash_A2_size=size in byte(hex)*/ +8000000 /*sflash_B1_size=size in byte(hex)*/ +0 /*sflash_B2_size=size in byte(hex)*/ +0 /*sclk_freq=0 to 6*/ +0 /*busy_bit_offset=bit position of device BUSY in device status register*/ +1 /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/ +0 /*sflash_port=0 or 1 (Port B used)*/ +0 /*ddr_mode_enable=0 or 1*/ +0 /*dqs_enable=0 or 1*/ +0 /*parallel_mode_enable=0 or 1*/ +0 /*portA_cs1=0 or 1*/ +0 /*portB_cs1=0 or 1*/ +0 /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/ +0 /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/ +0 /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/ +08180403 /*lut[0] command sequence*/ +24001c00 /*lut[1] command sequence*/ +0 /*lut[2] command sequence*/ +0 /*lut[3] command sequence*/ +0 /*lut[4] command sequence*/ +0 /*lut[5] command sequence*/ +0 /*lut[6] command sequence*/ +0 /*lut[7] command sequence*/ +0 /*lut[8] command sequence*/ +0 /*lut[9] command sequence*/ +0 /*lut[10] command sequence*/ +0 /*lut[11] command sequence*/ +0 /*lut[12] command sequence*/ +0 /*lut[13] command sequence*/ +0 /*lut[14] command sequence*/ +0 /*lut[15] command sequence*/ +0 /*lut[16] command sequence*/ +0 /*lut[17] command sequence*/ +0 /*lut[18] command sequence*/ +0 /*lut[19] command sequence*/ +0 /*lut[20] command sequence*/ +0 /*lut[21] command sequence*/ +0 /*lut[22] command sequence*/ +0 /*lut[23] command sequence*/ +0 /*lut[24] command sequence*/ +0 /*lut[25] command sequence*/ +0 /*lut[26] command sequence*/ +0 /*lut[27] command sequence*/ +0 /*lut[28] command sequence*/ +0 /*lut[29] command sequence*/ +0 /*lut[30] command sequence*/ +0 /*lut[31] command sequence*/ +0 /*lut[32] command sequence*/ +0 /*lut[33] command sequence*/ +0 /*lut[34] command sequence*/ +0 /*lut[35] command sequence*/ +0 /*lut[36] command sequence*/ +0 /*lut[37] command sequence*/ +0 /*lut[38] command sequence*/ +0 /*lut[39] command sequence*/ +0 /*lut[40] command sequence*/ +0 /*lut[41] command sequence*/ +0 /*lut[42] command sequence*/ +0 /*lut[43] command sequence*/ +0 /*lut[44] command sequence*/ +0 /*lut[45] command sequence*/ +0 /*lut[46] command sequence*/ +0 /*lut[47] command sequence*/ +0 /*lut[48] command sequence*/ +0 /*lut[49] command sequence*/ +0 /*lut[50] command sequence*/ +0 /*lut[51] command sequence*/ +0 /*lut[52] command sequence*/ +0 /*lut[53] command sequence*/ +0 /*lut[54] command sequence*/ +0 /*lut[55] command sequence*/ +0 /*lut[56] command sequence*/ +0 /*lut[57] command sequence*/ +0 /*lut[58] command sequence*/ +0 /*lut[59] command sequence*/ +0 /*lut[60] command sequence*/ +0 /*lut[61] command sequence*/ +0 /*lut[62] command sequence*/ +0 /*lut[63] command sequence*/ +1000001 /*read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/ +0 /*enable_dqs_phase=0 or 1*/ +0 /*config_cmds_en, enable config command*/ +0 /*config_cmds[0]*/ +0 /*config_cmds[1]*/ +0 /*config_cmds[2]*/ +0 /*config_cmds[3]*/ +0 /*config_cmds_args[0]*/ +0 /*config_cmds_args[1]*/ +0 /*config_cmds_args[2]*/ +0 /*config_cmds_args[3]*/ +0 /*io_pad_override_setting QSPI pins override setting*/ +0 /*reserve[0], 25 byte reserved area*/ +0 /*reserve[1], 25 byte reserved area*/ +0 /*reserve[2], 25 byte reserved area*/ +0 /*reserve[3], 25 byte reserved area*/ +0 /*reserve[4], 25 byte reserved area*/ +0 /*reserve[5], 25 byte reserved area*/ +0 /*reserve[6], 25 byte reserved area*/ +0 /*reserve[7], 25 byte reserved area*/ +0 /*reserve[8], 25 byte reserved area*/ +0 /*reserve[9], 25 byte reserved area*/ +0 /*reserve[10], 25 byte reserved area*/ +0 /*reserve[11], 25 byte reserved area*/ +0 /*reserve[12], 25 byte reserved area*/ +0 /*reserve[13], 25 byte reserved area*/ +0 /*reserve[14], 25 byte reserved area*/ +0 /*reserve[15], 25 byte reserved area*/ +0 /*reserve[16], 25 byte reserved area*/ +0 /*reserve[17], 25 byte reserved area*/ +0 /*reserve[18], 25 byte reserved area*/ +0 /*reserve[19], 25 byte reserved area*/ +0 /*reserve[20], 25 byte reserved area*/ +0 /*reserve[21], 25 byte reserved area*/ +0 /*reserve[22], 25 byte reserved area*/ +0 /*reserve[23], 25 byte reserved area*/ +0 /*reserve[24], 25 byte reserved area*/ +c0ffee01 /*tag, QSPI configuration tag, should be 0xc0ffee01*/ -- 1.9.1