MLK-18577-3 armv8: xen: add console write hypercall

Introduce console write hypercall to let Uboot could directly output with xen console, this needs CONFIG_VERBOSE_DEBUG enabled in xen. Because input is not a must requirement in android VM, and develop pvconsole needs more efforts, so let's use this hypercall first. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 8836c3104a1edfe542e0c1cef6690bc9d3d842a0) (cherry picked from commit aea71150857d4617009730683c95d858acb43392) (cherry picked from commit 3173d3ac39bed27a3197829ea13ffce5a89b07ac) (cherry picked from commit 8ece41f15c8d9c407ab0946fa28ba7365419c030)

MLK-18577-3 armv8: xen: add console write hypercall
Introduce console write hypercall to let Uboot could directly output with xen console, this needs CONFIG_VERBOSE_DEBUG enabled in xen. Because input is not a must requirement in android VM, and develop pvconsole needs more efforts, so let's use this hypercall first. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 8836c3104a1edfe542e0c1cef6690bc9d3d842a0) (cherry picked from commit aea71150857d4617009730683c95d858acb43392) (cherry picked from commit 3173d3ac39bed27a3197829ea13ffce5a89b07ac) (cherry picked from commit 8ece41f15c8d9c407ab0946fa28ba7365419c030)
Peng Fan
1 parent 77c8c40a60
Showing 6 changed files with 464 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv8/Makefile
arch/arm/cpu/armv8/xen/Makefile
arch/arm/cpu/armv8/xen/hypercall.S
arch/arm/cpu/armv8/xen/print.c
include/hypercall.h
include/xen.h
@@ -35,4 +35,5 @@
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
 obj-$(CONFIG_ARMV8_PSCI) += psci.o
 obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
+obj-$(CONFIG_XEN) += xen/
+obj-y += hypercall.o print.o
+/*
+ * Copyright 2018 NXP
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <xen.h>
+
+.globl HYPERVISOR_console_io;
+.align 4;
+HYPERVISOR_console_io:
+	mov x16, __HYPERVISOR_console_io;
+	hvc 0xEA1;
+	ret;
+/*
+ * Copyright 2018 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <hypercall.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <xen.h>
+
+/*
+ * To non privileged domain, need CONFIG_VERBOSE_DEBUG in XEN to 
+ * get output.
+ */
+void xenprintf(const char *buf)
+{
+	(void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(buf), buf);
+	return;
+}
+
+void xenprintc(const char c)
+{
+	(void)HYPERVISOR_console_io(CONSOLEIO_write, 1, &c);
+	return;
+}
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+ 
+ */
+
+int HYPERVISOR_console_io(int cmd, int count, const char *str);
+/******************************************************************************
+ * xen.h
+ *
+ * Guest OS interface to Xen.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Copyright (c) 2004, K A Fraser
+ */
+
+#ifndef __XEN_PUBLIC_XEN_H__
+#define __XEN_PUBLIC_XEN_H__
+
+//#include <asm/xen/interface.h>
+
+/*
+ * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
+ */
+
+/*
+ * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5.
+ *         EAX = return value
+ *         (argument registers may be clobbered on return)
+ * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6.
+ *         RAX = return value
+ *         (argument registers not clobbered on return; RCX, R11 are)
+ */
+#define __HYPERVISOR_set_trap_table        0
+#define __HYPERVISOR_mmu_update            1
+#define __HYPERVISOR_set_gdt               2
+#define __HYPERVISOR_stack_switch          3
+#define __HYPERVISOR_set_callbacks         4
+#define __HYPERVISOR_fpu_taskswitch        5
+#define __HYPERVISOR_sched_op_compat       6
+#define __HYPERVISOR_platform_op           7
+#define __HYPERVISOR_set_debugreg          8
+#define __HYPERVISOR_get_debugreg          9
+#define __HYPERVISOR_update_descriptor    10
+#define __HYPERVISOR_memory_op            12
+#define __HYPERVISOR_multicall            13
+#define __HYPERVISOR_update_va_mapping    14
+#define __HYPERVISOR_set_timer_op         15
+#define __HYPERVISOR_event_channel_op_compat 16
+#define __HYPERVISOR_xen_version          17
+#define __HYPERVISOR_console_io           18
+#define __HYPERVISOR_physdev_op_compat    19
+#define __HYPERVISOR_grant_table_op       20
+#define __HYPERVISOR_vm_assist            21
+#define __HYPERVISOR_update_va_mapping_otherdomain 22
+#define __HYPERVISOR_iret                 23 /* x86 only */
+#define __HYPERVISOR_vcpu_op              24
+#define __HYPERVISOR_set_segment_base     25 /* x86/64 only */
+#define __HYPERVISOR_mmuext_op            26
+#define __HYPERVISOR_xsm_op               27
+#define __HYPERVISOR_nmi_op               28
+#define __HYPERVISOR_sched_op             29
+#define __HYPERVISOR_callback_op          30
+#define __HYPERVISOR_xenoprof_op          31
+#define __HYPERVISOR_event_channel_op     32
+#define __HYPERVISOR_physdev_op           33
+#define __HYPERVISOR_hvm_op               34
+#define __HYPERVISOR_sysctl               35
+#define __HYPERVISOR_domctl               36
+#define __HYPERVISOR_kexec_op             37
+#define __HYPERVISOR_tmem_op              38
+#define __HYPERVISOR_xc_reserved_op       39 /* reserved for XenClient */
+#define __HYPERVISOR_xenpmu_op            40
+
+/* Architecture-specific hypercall definitions. */
+#define __HYPERVISOR_arch_0               48
+#define __HYPERVISOR_arch_1               49
+#define __HYPERVISOR_arch_2               50
+#define __HYPERVISOR_arch_3               51
+#define __HYPERVISOR_arch_4               52
+#define __HYPERVISOR_arch_5               53
+#define __HYPERVISOR_arch_6               54
+#define __HYPERVISOR_arch_7               55
+
+/*
+ * VIRTUAL INTERRUPTS
+ *
+ * Virtual interrupts that a guest OS may receive from Xen.
+ * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
+ * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
+ * The latter can be allocated only once per guest: they must initially be
+ * allocated to VCPU0 but can subsequently be re-bound.
+ */
+#define VIRQ_TIMER      0  /* V. Timebase update, and/or requested timeout.  */
+#define VIRQ_DEBUG      1  /* V. Request guest to dump debug info.           */
+#define VIRQ_CONSOLE    2  /* G. (DOM0) Bytes received on emergency console. */
+#define VIRQ_DOM_EXC    3  /* G. (DOM0) Exceptional event for some domain.   */
+#define VIRQ_TBUF       4  /* G. (DOM0) Trace buffer has records available.  */
+#define VIRQ_DEBUGGER   6  /* G. (DOM0) A domain has paused for debugging.   */
+#define VIRQ_XENOPROF   7  /* V. XenOprofile interrupt: new sample available */
+#define VIRQ_CON_RING   8  /* G. (DOM0) Bytes received on console            */
+#define VIRQ_PCPU_STATE 9  /* G. (DOM0) PCPU state changed                   */
+#define VIRQ_MEM_EVENT  10 /* G. (DOM0) A memory event has occured           */
+#define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient                     */
+#define VIRQ_ENOMEM     12 /* G. (DOM0) Low on heap memory       */
+#define VIRQ_XENPMU     13  /* PMC interrupt                                 */
+
+/* Architecture-specific VIRQ definitions. */
+#define VIRQ_ARCH_0    16
+#define VIRQ_ARCH_1    17
+#define VIRQ_ARCH_2    18
+#define VIRQ_ARCH_3    19
+#define VIRQ_ARCH_4    20
+#define VIRQ_ARCH_5    21
+#define VIRQ_ARCH_6    22
+#define VIRQ_ARCH_7    23
+
+#define NR_VIRQS       24
+
+/*
+ * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[],
+ *                                         unsigned count, unsigned *done_out,
+ *                                         unsigned foreigndom)
+ * @reqs is an array of mmu_update_t structures ((ptr, val) pairs).
+ * @count is the length of the above array.
+ * @pdone is an output parameter indicating number of completed operations
+ * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this
+ *                    hypercall invocation. Can be DOMID_SELF.
+ * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced
+ *                     in this hypercall invocation. The value of this field
+ *                     (x) encodes the PFD as follows:
+ *                     x == 0 => PFD == DOMID_SELF
+ *                     x != 0 => PFD == x - 1
+ *
+ * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
+ * -------------
+ * ptr[1:0] == MMU_NORMAL_PT_UPDATE:
+ * Updates an entry in a page table belonging to PFD. If updating an L1 table,
+ * and the new table entry is valid/present, the mapped frame must belong to
+ * FD. If attempting to map an I/O page then the caller assumes the privilege
+ * of the FD.
+ * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller.
+ * FD == DOMID_XEN: Map restricted areas of Xen's heap space.
+ * ptr[:2]  -- Machine address of the page-table entry to modify.
+ * val      -- Value to write.
+ *
+ * There also certain implicit requirements when using this hypercall. The
+ * pages that make up a pagetable must be mapped read-only in the guest.
+ * This prevents uncontrolled guest updates to the pagetable. Xen strictly
+ * enforces this, and will disallow any pagetable update which will end up
+ * mapping pagetable page RW, and will disallow using any writable page as a
+ * pagetable. In practice it means that when constructing a page table for a
+ * process, thread, etc, we MUST be very dilligient in following these rules:
+ *  1). Start with top-level page (PGD or in Xen language: L4). Fill out
+ *      the entries.
+ *  2). Keep on going, filling out the upper (PUD or L3), and middle (PMD
+ *      or L2).
+ *  3). Start filling out the PTE table (L1) with the PTE entries. Once
+ *      done, make sure to set each of those entries to RO (so writeable bit
+ *      is unset). Once that has been completed, set the PMD (L2) for this
+ *      PTE table as RO.
+ *  4). When completed with all of the PMD (L2) entries, and all of them have
+ *      been set to RO, make sure to set RO the PUD (L3). Do the same
+ *      operation on PGD (L4) pagetable entries that have a PUD (L3) entry.
+ *  5). Now before you can use those pages (so setting the cr3), you MUST also
+ *      pin them so that the hypervisor can verify the entries. This is done
+ *      via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame
+ *      number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op(
+ *      MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be
+ *      issued.
+ * For 32-bit guests, the L4 is not used (as there is less pagetables), so
+ * instead use L3.
+ * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE
+ * hypercall. Also if so desired the OS can also try to write to the PTE
+ * and be trapped by the hypervisor (as the PTE entry is RO).
+ *
+ * To deallocate the pages, the operations are the reverse of the steps
+ * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the
+ * pagetable MUST not be in use (meaning that the cr3 is not set to it).
+ *
+ * ptr[1:0] == MMU_MACHPHYS_UPDATE:
+ * Updates an entry in the machine->pseudo-physical mapping table.
+ * ptr[:2]  -- Machine address within the frame whose mapping to modify.
+ *             The frame must belong to the FD, if one is specified.
+ * val      -- Value to write into the mapping entry.
+ *
+ * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
+ * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
+ * with those in @val.
+ *
+ * @val is usually the machine frame number along with some attributes.
+ * The attributes by default follow the architecture defined bits. Meaning that
+ * if this is a X86_64 machine and four page table layout is used, the layout
+ * of val is:
+ *  - 63 if set means No execute (NX)
+ *  - 46-13 the machine frame number
+ *  - 12 available for guest
+ *  - 11 available for guest
+ *  - 10 available for guest
+ *  - 9 available for guest
+ *  - 8 global
+ *  - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages)
+ *  - 6 dirty
+ *  - 5 accessed
+ *  - 4 page cached disabled
+ *  - 3 page write through
+ *  - 2 userspace accessible
+ *  - 1 writeable
+ *  - 0 present
+ *
+ *  The one bits that does not fit with the default layout is the PAGE_PSE
+ *  also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the
+ *  HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB
+ *  (or 2MB) instead of using the PAGE_PSE bit.
+ *
+ *  The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen
+ *  using it as the Page Attribute Table (PAT) bit - for details on it please
+ *  refer to Intel SDM 10.12. The PAT allows to set the caching attributes of
+ *  pages instead of using MTRRs.
+ *
+ *  The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits):
+ *                    PAT4                 PAT0
+ *  +-----+-----+----+----+----+-----+----+----+
+ *  | UC  | UC- | WC | WB | UC | UC- | WC | WB |  <= Linux
+ *  +-----+-----+----+----+----+-----+----+----+
+ *  | UC  | UC- | WT | WB | UC | UC- | WT | WB |  <= BIOS (default when machine boots)
+ *  +-----+-----+----+----+----+-----+----+----+
+ *  | rsv | rsv | WP | WC | UC | UC- | WT | WB |  <= Xen
+ *  +-----+-----+----+----+----+-----+----+----+
+ *
+ *  The lookup of this index table translates to looking up
+ *  Bit 7, Bit 4, and Bit 3 of val entry:
+ *
+ *  PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3).
+ *
+ *  If all bits are off, then we are using PAT0. If bit 3 turned on,
+ *  then we are using PAT1, if bit 3 and bit 4, then PAT2..
+ *
+ *  As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means
+ *  that if a guest that follows Linux's PAT setup and would like to set Write
+ *  Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is
+ *  set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the
+ *  caching as:
+ *
+ *   WB = none (so PAT0)
+ *   WC = PWT (bit 3 on)
+ *   UC = PWT | PCD (bit 3 and 4 are on).
+ *
+ * To make it work with Xen, it needs to translate the WC bit as so:
+ *
+ *  PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3
+ *
+ * And to translate back it would:
+ *
+ * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7.
+ */
+#define MMU_NORMAL_PT_UPDATE      0 /* checked '*ptr = val'. ptr is MA.       */
+#define MMU_MACHPHYS_UPDATE       1 /* ptr = MA of frame to modify entry for  */
+#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */
+
+/*
+ * MMU EXTENDED OPERATIONS
+ *
+ * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[],
+ *                                        unsigned int count,
+ *                                        unsigned int *pdone,
+ *                                        unsigned int foreigndom)
+ */
+/* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures.
+ * A foreigndom (FD) can be specified (or DOMID_SELF for none).
+ * Where the FD has some effect, it is described below.
+ *
+ * cmd: MMUEXT_(UN)PIN_*_TABLE
+ * mfn: Machine frame number to be (un)pinned as a p.t. page.
+ *      The frame must belong to the FD, if one is specified.
+ *
+ * cmd: MMUEXT_NEW_BASEPTR
+ * mfn: Machine frame number of new page-table base to install in MMU.
+ *
+ * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only]
+ * mfn: Machine frame number of new page-table base to install in MMU
+ *      when in user space.
+ *
+ * cmd: MMUEXT_TLB_FLUSH_LOCAL
+ * No additional arguments. Flushes local TLB.
+ *
+ * cmd: MMUEXT_INVLPG_LOCAL
+ * linear_addr: Linear address to be flushed from the local TLB.
+ *
+ * cmd: MMUEXT_TLB_FLUSH_MULTI
+ * vcpumask: Pointer to bitmap of VCPUs to be flushed.
+ *
+ * cmd: MMUEXT_INVLPG_MULTI
+ * linear_addr: Linear address to be flushed.
+ * vcpumask: Pointer to bitmap of VCPUs to be flushed.
+ *
+ * cmd: MMUEXT_TLB_FLUSH_ALL
+ * No additional arguments. Flushes all VCPUs' TLBs.
+ *
+ * cmd: MMUEXT_INVLPG_ALL
+ * linear_addr: Linear address to be flushed from all VCPUs' TLBs.
+ *
+ * cmd: MMUEXT_FLUSH_CACHE
+ * No additional arguments. Writes back and flushes cache contents.
+ *
+ * cmd: MMUEXT_FLUSH_CACHE_GLOBAL
+ * No additional arguments. Writes back and flushes cache contents
+ * on all CPUs in the system.
+ *
+ * cmd: MMUEXT_SET_LDT
+ * linear_addr: Linear address of LDT base (NB. must be page-aligned).
+ * nr_ents: Number of entries in LDT.
+ *
+ * cmd: MMUEXT_CLEAR_PAGE
+ * mfn: Machine frame number to be cleared.
+ *
+ * cmd: MMUEXT_COPY_PAGE
+ * mfn: Machine frame number of the destination page.
+ * src_mfn: Machine frame number of the source page.
+ *
+ * cmd: MMUEXT_[UN]MARK_SUPER
+ * mfn: Machine frame number of head of superpage to be [un]marked.
+ */
+#define MMUEXT_PIN_L1_TABLE      0
+#define MMUEXT_PIN_L2_TABLE      1
+#define MMUEXT_PIN_L3_TABLE      2
+#define MMUEXT_PIN_L4_TABLE      3
+#define MMUEXT_UNPIN_TABLE       4
+#define MMUEXT_NEW_BASEPTR       5
+#define MMUEXT_TLB_FLUSH_LOCAL   6
+#define MMUEXT_INVLPG_LOCAL      7
+#define MMUEXT_TLB_FLUSH_MULTI   8
+#define MMUEXT_INVLPG_MULTI      9
+#define MMUEXT_TLB_FLUSH_ALL    10
+#define MMUEXT_INVLPG_ALL       11
+#define MMUEXT_FLUSH_CACHE      12
+#define MMUEXT_SET_LDT          13
+#define MMUEXT_NEW_USER_BASEPTR 15
+#define MMUEXT_CLEAR_PAGE       16
+#define MMUEXT_COPY_PAGE        17
+#define MMUEXT_FLUSH_CACHE_GLOBAL 18
+#define MMUEXT_MARK_SUPER       19
+#define MMUEXT_UNMARK_SUPER     20
+
+
+/* These are passed as 'flags' to update_va_mapping. They can be ORed. */
+/* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap.   */
+/* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer.         */
+#define UVMF_NONE               (0UL<<0) /* No flushing at all.   */
+#define UVMF_TLB_FLUSH          (1UL<<0) /* Flush entire TLB(s).  */
+#define UVMF_INVLPG             (2UL<<0) /* Flush only one entry. */
+#define UVMF_FLUSHTYPE_MASK     (3UL<<0)
+#define UVMF_MULTI              (0UL<<2) /* Flush subset of TLBs. */
+#define UVMF_LOCAL              (0UL<<2) /* Flush local TLB.      */
+#define UVMF_ALL                (1UL<<2) /* Flush all TLBs.       */
+
+/*
+ * Commands to HYPERVISOR_console_io().
+ */
+#define CONSOLEIO_write         0
+#define CONSOLEIO_read          1
+
+/*
+ * Commands to HYPERVISOR_vm_assist().
+ */
+#define VMASST_CMD_enable                0
+#define VMASST_CMD_disable               1
+
+/* x86/32 guests: simulate full 4GB segment limits. */
+#define VMASST_TYPE_4gb_segments         0
+
+/* x86/32 guests: trap (vector 15) whenever above vmassist is used. */
+#define VMASST_TYPE_4gb_segments_notify  1
+
+/*
+ * x86 guests: support writes to bottom-level PTEs.
+ * NB1. Page-directory entries cannot be written.
+ * NB2. Guest must continue to remove all writable mappings of PTEs.
+ */
+#define VMASST_TYPE_writable_pagetables  2
+
+/* x86/PAE guests: support PDPTs above 4GB. */
+#define VMASST_TYPE_pae_extended_cr3     3
+
+/*
+ * x86 guests: Sane behaviour for virtual iopl
+ *  - virtual iopl updated from do_iret() hypercalls.
+ *  - virtual iopl reported in bounce frames.
+ *  - guest kernels assumed to be level 0 for the purpose of iopl checks.
+ */
+#define VMASST_TYPE_architectural_iopl   4
+
+/*
+ * All guests: activate update indicator in vcpu_runstate_info
+ * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped
+ * vcpu_runstate_info during updates of the runstate information.
+ */
+#define VMASST_TYPE_runstate_update_flag 5
+
+#define MAX_VMASST_TYPE 5
+
+#endif /* __XEN_PUBLIC_XEN_H__ */
...	...	@@ -35,4 +35,5 @@
35	35	obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
36	36	obj-$(CONFIG_ARMV8_PSCI) += psci.o
37	37	obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
	38	+obj-$(CONFIG_XEN) += xen/
	1	+/*
	2	+ * Copyright 2018 NXP
	3	+
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <xen.h>
	8	+
	9	+.globl HYPERVISOR_console_io;
	10	+.align 4;
	11	+HYPERVISOR_console_io:
	12	+ mov x16, __HYPERVISOR_console_io;
	13	+ hvc 0xEA1;
	14	+ ret;
	1	+/*
	2	+ * Copyright 2018 NXP
	3	+ *
	4	+ * Peng Fan <peng.fan@nxp.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <hypercall.h>
	10	+#include <linux/types.h>
	11	+#include <linux/string.h>
	12	+#include <linux/ctype.h>
	13	+#include <xen.h>
	14	+
	15	+/*
	16	+ * To non privileged domain, need CONFIG_VERBOSE_DEBUG in XEN to
	17	+ * get output.
	18	+ */
	19	+void xenprintf(const char *buf)
	20	+{
	21	+ (void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(buf), buf);
	22	+ return;
	23	+}
	24	+
	25	+void xenprintc(const char c)
	26	+{
	27	+ (void)HYPERVISOR_console_io(CONSOLEIO_write, 1, &c);
	28	+ return;
	29	+}
	1	+/******************************************************************************
	2	+ * xen.h
	3	+ *
	4	+ * Guest OS interface to Xen.
	5	+ *
	6	+ * Permission is hereby granted, free of charge, to any person obtaining a copy
	7	+ * of this software and associated documentation files (the "Software"), to
	8	+ * deal in the Software without restriction, including without limitation the
	9	+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
	10	+ * sell copies of the Software, and to permit persons to whom the Software is
	11	+ * furnished to do so, subject to the following conditions:
	12	+ *
	13	+ * The above copyright notice and this permission notice shall be included in
	14	+ * all copies or substantial portions of the Software.
	15	+ *
	16	+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	19	+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	+ * DEALINGS IN THE SOFTWARE.
	23	+ *
	24	+ * Copyright (c) 2004, K A Fraser
	25	+ */
	26	+
	27	+#ifndef __XEN_PUBLIC_XEN_H__
	28	+#define __XEN_PUBLIC_XEN_H__
	29	+
	30	+//#include <asm/xen/interface.h>
	31	+
	32	+/*
	33	+ * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
	34	+ */
	35	+
	36	+/*
	37	+ * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5.
	38	+ * EAX = return value
	39	+ * (argument registers may be clobbered on return)
	40	+ * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6.
	41	+ * RAX = return value
	42	+ * (argument registers not clobbered on return; RCX, R11 are)
	43	+ */
	44	+#define __HYPERVISOR_set_trap_table 0
	45	+#define __HYPERVISOR_mmu_update 1
	46	+#define __HYPERVISOR_set_gdt 2
	47	+#define __HYPERVISOR_stack_switch 3
	48	+#define __HYPERVISOR_set_callbacks 4
	49	+#define __HYPERVISOR_fpu_taskswitch 5
	50	+#define __HYPERVISOR_sched_op_compat 6
	51	+#define __HYPERVISOR_platform_op 7
	52	+#define __HYPERVISOR_set_debugreg 8
	53	+#define __HYPERVISOR_get_debugreg 9
	54	+#define __HYPERVISOR_update_descriptor 10
	55	+#define __HYPERVISOR_memory_op 12
	56	+#define __HYPERVISOR_multicall 13
	57	+#define __HYPERVISOR_update_va_mapping 14
	58	+#define __HYPERVISOR_set_timer_op 15
	59	+#define __HYPERVISOR_event_channel_op_compat 16
	60	+#define __HYPERVISOR_xen_version 17
	61	+#define __HYPERVISOR_console_io 18
	62	+#define __HYPERVISOR_physdev_op_compat 19
	63	+#define __HYPERVISOR_grant_table_op 20
	64	+#define __HYPERVISOR_vm_assist 21
	65	+#define __HYPERVISOR_update_va_mapping_otherdomain 22
	66	+#define __HYPERVISOR_iret 23 /* x86 only */
	67	+#define __HYPERVISOR_vcpu_op 24
	68	+#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */
	69	+#define __HYPERVISOR_mmuext_op 26
	70	+#define __HYPERVISOR_xsm_op 27
	71	+#define __HYPERVISOR_nmi_op 28
	72	+#define __HYPERVISOR_sched_op 29
	73	+#define __HYPERVISOR_callback_op 30
	74	+#define __HYPERVISOR_xenoprof_op 31
	75	+#define __HYPERVISOR_event_channel_op 32
	76	+#define __HYPERVISOR_physdev_op 33
	77	+#define __HYPERVISOR_hvm_op 34
	78	+#define __HYPERVISOR_sysctl 35
	79	+#define __HYPERVISOR_domctl 36
	80	+#define __HYPERVISOR_kexec_op 37
	81	+#define __HYPERVISOR_tmem_op 38
	82	+#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */
	83	+#define __HYPERVISOR_xenpmu_op 40
	84	+
	85	+/* Architecture-specific hypercall definitions. */
	86	+#define __HYPERVISOR_arch_0 48
	87	+#define __HYPERVISOR_arch_1 49
	88	+#define __HYPERVISOR_arch_2 50
	89	+#define __HYPERVISOR_arch_3 51
	90	+#define __HYPERVISOR_arch_4 52
	91	+#define __HYPERVISOR_arch_5 53
	92	+#define __HYPERVISOR_arch_6 54
	93	+#define __HYPERVISOR_arch_7 55
	94	+
	95	+/*
	96	+ * VIRTUAL INTERRUPTS
	97	+ *
	98	+ * Virtual interrupts that a guest OS may receive from Xen.
	99	+ * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
	100	+ * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
	101	+ * The latter can be allocated only once per guest: they must initially be
	102	+ * allocated to VCPU0 but can subsequently be re-bound.
	103	+ */
	104	+#define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */
	105	+#define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */
	106	+#define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */
	107	+#define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */
	108	+#define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */
	109	+#define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */
	110	+#define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */
	111	+#define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */
	112	+#define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */
	113	+#define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */
	114	+#define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */
	115	+#define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */
	116	+#define VIRQ_XENPMU 13 /* PMC interrupt */
	117	+
	118	+/* Architecture-specific VIRQ definitions. */
	119	+#define VIRQ_ARCH_0 16
	120	+#define VIRQ_ARCH_1 17
	121	+#define VIRQ_ARCH_2 18
	122	+#define VIRQ_ARCH_3 19
	123	+#define VIRQ_ARCH_4 20
	124	+#define VIRQ_ARCH_5 21
	125	+#define VIRQ_ARCH_6 22
	126	+#define VIRQ_ARCH_7 23
	127	+
	128	+#define NR_VIRQS 24
	129	+
	130	+/*
	131	+ * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[],
	132	+ * unsigned count, unsigned *done_out,
	133	+ * unsigned foreigndom)
	134	+ * @reqs is an array of mmu_update_t structures ((ptr, val) pairs).
	135	+ * @count is the length of the above array.
	136	+ * @pdone is an output parameter indicating number of completed operations
	137	+ * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this
	138	+ * hypercall invocation. Can be DOMID_SELF.
	139	+ * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced
	140	+ * in this hypercall invocation. The value of this field
	141	+ * (x) encodes the PFD as follows:
	142	+ * x == 0 => PFD == DOMID_SELF
	143	+ * x != 0 => PFD == x - 1
	144	+ *
	145	+ * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
	146	+ * -------------
	147	+ * ptr[1:0] == MMU_NORMAL_PT_UPDATE:
	148	+ * Updates an entry in a page table belonging to PFD. If updating an L1 table,
	149	+ * and the new table entry is valid/present, the mapped frame must belong to
	150	+ * FD. If attempting to map an I/O page then the caller assumes the privilege
	151	+ * of the FD.
	152	+ * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller.
	153	+ * FD == DOMID_XEN: Map restricted areas of Xen's heap space.
	154	+ * ptr[:2] -- Machine address of the page-table entry to modify.
	155	+ * val -- Value to write.
	156	+ *
	157	+ * There also certain implicit requirements when using this hypercall. The
	158	+ * pages that make up a pagetable must be mapped read-only in the guest.
	159	+ * This prevents uncontrolled guest updates to the pagetable. Xen strictly
	160	+ * enforces this, and will disallow any pagetable update which will end up
	161	+ * mapping pagetable page RW, and will disallow using any writable page as a
	162	+ * pagetable. In practice it means that when constructing a page table for a
	163	+ * process, thread, etc, we MUST be very dilligient in following these rules:
	164	+ * 1). Start with top-level page (PGD or in Xen language: L4). Fill out
	165	+ * the entries.
	166	+ * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD
	167	+ * or L2).
	168	+ * 3). Start filling out the PTE table (L1) with the PTE entries. Once
	169	+ * done, make sure to set each of those entries to RO (so writeable bit
	170	+ * is unset). Once that has been completed, set the PMD (L2) for this
	171	+ * PTE table as RO.
	172	+ * 4). When completed with all of the PMD (L2) entries, and all of them have
	173	+ * been set to RO, make sure to set RO the PUD (L3). Do the same
	174	+ * operation on PGD (L4) pagetable entries that have a PUD (L3) entry.
	175	+ * 5). Now before you can use those pages (so setting the cr3), you MUST also
	176	+ * pin them so that the hypervisor can verify the entries. This is done
	177	+ * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame
	178	+ * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op(
	179	+ * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be
	180	+ * issued.
	181	+ * For 32-bit guests, the L4 is not used (as there is less pagetables), so
	182	+ * instead use L3.
	183	+ * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE
	184	+ * hypercall. Also if so desired the OS can also try to write to the PTE
	185	+ * and be trapped by the hypervisor (as the PTE entry is RO).
	186	+ *
	187	+ * To deallocate the pages, the operations are the reverse of the steps
	188	+ * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the
	189	+ * pagetable MUST not be in use (meaning that the cr3 is not set to it).
	190	+ *
	191	+ * ptr[1:0] == MMU_MACHPHYS_UPDATE:
	192	+ * Updates an entry in the machine->pseudo-physical mapping table.
	193	+ * ptr[:2] -- Machine address within the frame whose mapping to modify.
	194	+ * The frame must belong to the FD, if one is specified.
	195	+ * val -- Value to write into the mapping entry.
	196	+ *
	197	+ * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
	198	+ * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
	199	+ * with those in @val.
	200	+ *
	201	+ * @val is usually the machine frame number along with some attributes.
	202	+ * The attributes by default follow the architecture defined bits. Meaning that
	203	+ * if this is a X86_64 machine and four page table layout is used, the layout
	204	+ * of val is:
	205	+ * - 63 if set means No execute (NX)
	206	+ * - 46-13 the machine frame number
	207	+ * - 12 available for guest
	208	+ * - 11 available for guest
	209	+ * - 10 available for guest
	210	+ * - 9 available for guest
	211	+ * - 8 global
	212	+ * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages)
	213	+ * - 6 dirty
	214	+ * - 5 accessed
	215	+ * - 4 page cached disabled
	216	+ * - 3 page write through
	217	+ * - 2 userspace accessible
	218	+ * - 1 writeable
	219	+ * - 0 present
	220	+ *
	221	+ * The one bits that does not fit with the default layout is the PAGE_PSE
	222	+ * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the
	223	+ * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB
	224	+ * (or 2MB) instead of using the PAGE_PSE bit.
	225	+ *
	226	+ * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen
	227	+ * using it as the Page Attribute Table (PAT) bit - for details on it please
	228	+ * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of
	229	+ * pages instead of using MTRRs.
	230	+ *
	231	+ * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits):
	232	+ * PAT4 PAT0
	233	+ * +-----+-----+----+----+----+-----+----+----+
	234	+ * \| UC \| UC- \| WC \| WB \| UC \| UC- \| WC \| WB \| <= Linux
	235	+ * +-----+-----+----+----+----+-----+----+----+
	236	+ * \| UC \| UC- \| WT \| WB \| UC \| UC- \| WT \| WB \| <= BIOS (default when machine boots)
	237	+ * +-----+-----+----+----+----+-----+----+----+
	238	+ * \| rsv \| rsv \| WP \| WC \| UC \| UC- \| WT \| WB \| <= Xen
	239	+ * +-----+-----+----+----+----+-----+----+----+
	240	+ *
	241	+ * The lookup of this index table translates to looking up
	242	+ * Bit 7, Bit 4, and Bit 3 of val entry:
	243	+ *
	244	+ * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3).
	245	+ *
	246	+ * If all bits are off, then we are using PAT0. If bit 3 turned on,
	247	+ * then we are using PAT1, if bit 3 and bit 4, then PAT2..
	248	+ *
	249	+ * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means
	250	+ * that if a guest that follows Linux's PAT setup and would like to set Write
	251	+ * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is
	252	+ * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the
	253	+ * caching as:
	254	+ *
	255	+ * WB = none (so PAT0)
	256	+ * WC = PWT (bit 3 on)
	257	+ * UC = PWT \| PCD (bit 3 and 4 are on).
	258	+ *
	259	+ * To make it work with Xen, it needs to translate the WC bit as so:
	260	+ *
	261	+ * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3
	262	+ *
	263	+ * And to translate back it would:
	264	+ *
	265	+ * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7.
	266	+ */
	267	+#define MMU_NORMAL_PT_UPDATE 0 /* checked 'ptr = val'. ptr is MA. /
	268	+#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */
	269	+#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: ptr = val \| (ptr&(A\|D)) */
	270	+
	271	+/*
	272	+ * MMU EXTENDED OPERATIONS
	273	+ *
	274	+ * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[],
	275	+ * unsigned int count,
	276	+ * unsigned int *pdone,
	277	+ * unsigned int foreigndom)
	278	+ */
	279	+/* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures.
	280	+ * A foreigndom (FD) can be specified (or DOMID_SELF for none).
	281	+ * Where the FD has some effect, it is described below.
	282	+ *
	283	+ * cmd: MMUEXT_(UN)PIN_*_TABLE
	284	+ * mfn: Machine frame number to be (un)pinned as a p.t. page.
	285	+ * The frame must belong to the FD, if one is specified.
	286	+ *
	287	+ * cmd: MMUEXT_NEW_BASEPTR
	288	+ * mfn: Machine frame number of new page-table base to install in MMU.
	289	+ *
	290	+ * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only]
	291	+ * mfn: Machine frame number of new page-table base to install in MMU
	292	+ * when in user space.
	293	+ *
	294	+ * cmd: MMUEXT_TLB_FLUSH_LOCAL
	295	+ * No additional arguments. Flushes local TLB.
	296	+ *
	297	+ * cmd: MMUEXT_INVLPG_LOCAL
	298	+ * linear_addr: Linear address to be flushed from the local TLB.
	299	+ *
	300	+ * cmd: MMUEXT_TLB_FLUSH_MULTI
	301	+ * vcpumask: Pointer to bitmap of VCPUs to be flushed.
	302	+ *
	303	+ * cmd: MMUEXT_INVLPG_MULTI
	304	+ * linear_addr: Linear address to be flushed.
	305	+ * vcpumask: Pointer to bitmap of VCPUs to be flushed.
	306	+ *
	307	+ * cmd: MMUEXT_TLB_FLUSH_ALL
	308	+ * No additional arguments. Flushes all VCPUs' TLBs.
	309	+ *
	310	+ * cmd: MMUEXT_INVLPG_ALL
	311	+ * linear_addr: Linear address to be flushed from all VCPUs' TLBs.
	312	+ *
	313	+ * cmd: MMUEXT_FLUSH_CACHE
	314	+ * No additional arguments. Writes back and flushes cache contents.
	315	+ *
	316	+ * cmd: MMUEXT_FLUSH_CACHE_GLOBAL
	317	+ * No additional arguments. Writes back and flushes cache contents
	318	+ * on all CPUs in the system.
	319	+ *
	320	+ * cmd: MMUEXT_SET_LDT
	321	+ * linear_addr: Linear address of LDT base (NB. must be page-aligned).
	322	+ * nr_ents: Number of entries in LDT.
	323	+ *
	324	+ * cmd: MMUEXT_CLEAR_PAGE
	325	+ * mfn: Machine frame number to be cleared.
	326	+ *
	327	+ * cmd: MMUEXT_COPY_PAGE
	328	+ * mfn: Machine frame number of the destination page.
	329	+ * src_mfn: Machine frame number of the source page.
	330	+ *
	331	+ * cmd: MMUEXT_[UN]MARK_SUPER
	332	+ * mfn: Machine frame number of head of superpage to be [un]marked.
	333	+ */
	334	+#define MMUEXT_PIN_L1_TABLE 0
	335	+#define MMUEXT_PIN_L2_TABLE 1
	336	+#define MMUEXT_PIN_L3_TABLE 2
	337	+#define MMUEXT_PIN_L4_TABLE 3
	338	+#define MMUEXT_UNPIN_TABLE 4
	339	+#define MMUEXT_NEW_BASEPTR 5
	340	+#define MMUEXT_TLB_FLUSH_LOCAL 6
	341	+#define MMUEXT_INVLPG_LOCAL 7
	342	+#define MMUEXT_TLB_FLUSH_MULTI 8
	343	+#define MMUEXT_INVLPG_MULTI 9
	344	+#define MMUEXT_TLB_FLUSH_ALL 10
	345	+#define MMUEXT_INVLPG_ALL 11
	346	+#define MMUEXT_FLUSH_CACHE 12
	347	+#define MMUEXT_SET_LDT 13
	348	+#define MMUEXT_NEW_USER_BASEPTR 15
	349	+#define MMUEXT_CLEAR_PAGE 16
	350	+#define MMUEXT_COPY_PAGE 17
	351	+#define MMUEXT_FLUSH_CACHE_GLOBAL 18
	352	+#define MMUEXT_MARK_SUPER 19
	353	+#define MMUEXT_UNMARK_SUPER 20
	354	+
	355	+
	356	+/* These are passed as 'flags' to update_va_mapping. They can be ORed. */
	357	+/* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */
	358	+/* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */
	359	+#define UVMF_NONE (0UL<<0) /* No flushing at all. */
	360	+#define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */
	361	+#define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */
	362	+#define UVMF_FLUSHTYPE_MASK (3UL<<0)
	363	+#define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */
	364	+#define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */
	365	+#define UVMF_ALL (1UL<<2) /* Flush all TLBs. */
	366	+
	367	+/*
	368	+ * Commands to HYPERVISOR_console_io().
	369	+ */
	370	+#define CONSOLEIO_write 0
	371	+#define CONSOLEIO_read 1
	372	+
	373	+/*
	374	+ * Commands to HYPERVISOR_vm_assist().
	375	+ */
	376	+#define VMASST_CMD_enable 0
	377	+#define VMASST_CMD_disable 1
	378	+
	379	+/* x86/32 guests: simulate full 4GB segment limits. */
	380	+#define VMASST_TYPE_4gb_segments 0
	381	+
	382	+/* x86/32 guests: trap (vector 15) whenever above vmassist is used. */
	383	+#define VMASST_TYPE_4gb_segments_notify 1
	384	+
	385	+/*
	386	+ * x86 guests: support writes to bottom-level PTEs.
	387	+ * NB1. Page-directory entries cannot be written.
	388	+ * NB2. Guest must continue to remove all writable mappings of PTEs.
	389	+ */
	390	+#define VMASST_TYPE_writable_pagetables 2
	391	+
	392	+/* x86/PAE guests: support PDPTs above 4GB. */
	393	+#define VMASST_TYPE_pae_extended_cr3 3
	394	+
	395	+/*
	396	+ * x86 guests: Sane behaviour for virtual iopl
	397	+ * - virtual iopl updated from do_iret() hypercalls.
	398	+ * - virtual iopl reported in bounce frames.
	399	+ * - guest kernels assumed to be level 0 for the purpose of iopl checks.
	400	+ */
	401	+#define VMASST_TYPE_architectural_iopl 4
	402	+
	403	+/*
	404	+ * All guests: activate update indicator in vcpu_runstate_info
	405	+ * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped
	406	+ * vcpu_runstate_info during updates of the runstate information.
	407	+ */
	408	+#define VMASST_TYPE_runstate_update_flag 5
	409	+
	410	+#define MAX_VMASST_TYPE 5
	411	+
	412	+#endif /* __XEN_PUBLIC_XEN_H__ */