Eric Lee / smarc-uboot

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Commit 85f84661b01acf4e7002b752a3a05c7bfadfc8b4

Authored by Eric Lee
1 parent d41ce506b4
Exists in smarc-8mm-p9.0.0_2.0.0_ga and in 1 other branch smarc-8m-p9.0.0_2.0.0_ga

Fix console port switching problem

Showing 3 changed files with 17 additions and 8 deletions Inline Diff

arch/arm/dts/fsl-smarcimx8mq.dts
Diff comments   View file @ 85f8466
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 /dts-v1/; 16 /dts-v1/;
17 17
18 /* First 128KB is for PSCI ATF. */ 18 /* First 128KB is for PSCI ATF. */
19 /memreserve/ 0x40000000 0x00020000; 19 /memreserve/ 0x40000000 0x00020000;
20 20
21 #include "fsl-imx8mq.dtsi" 21 #include "fsl-imx8mq.dtsi"
22 22
23 / { 23 / {
24 model = "Embedian SMARC-iMX8M Computer on Module"; 24 model = "Embedian SMARC-iMX8M Computer on Module";
25 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq"; 25 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";
26 26
27 chosen {
28 bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
29 stdout-path = &uart1;
30 };
31
32 regulators { 27 regulators {
33 compatible = "simple-bus"; 28 compatible = "simple-bus";
34 #address-cells = <1>; 29 #address-cells = <1>;
35 #size-cells = <0>; 30 #size-cells = <0>;
36 31
37 reg_usdhc2_vmmc: usdhc2_vmmc { 32 reg_usdhc2_vmmc: usdhc2_vmmc {
38 compatible = "regulator-fixed"; 33 compatible = "regulator-fixed";
39 regulator-name = "VSD_3V3"; 34 regulator-name = "VSD_3V3";
40 regulator-min-microvolt = <3300000>; 35 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>;
42 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
43 enable-active-high; 38 enable-active-high;
44 }; 39 };
45 }; 40 };
46 41
47 backlight: backlight { 42 backlight: backlight {
48 compatible = "pwm-backlight"; 43 compatible = "pwm-backlight";
49 pwms = <&pwm1 0 1000000 0>; 44 pwms = <&pwm1 0 1000000 0>;
50 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 45 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
51 10 11 12 13 14 15 16 17 18 19 46 10 11 12 13 14 15 16 17 18 19
52 20 21 22 23 24 25 26 27 28 29 47 20 21 22 23 24 25 26 27 28 29
53 30 31 32 33 34 35 36 37 38 39 48 30 31 32 33 34 35 36 37 38 39
54 40 41 42 43 44 45 46 47 48 49 49 40 41 42 43 44 45 46 47 48 49
55 50 51 52 53 54 55 56 57 58 59 50 50 51 52 53 54 55 56 57 58 59
56 60 61 62 63 64 65 66 67 68 69 51 60 61 62 63 64 65 66 67 68 69
57 70 71 72 73 74 75 76 77 78 79 52 70 71 72 73 74 75 76 77 78 79
58 80 81 82 83 84 85 86 87 88 89 53 80 81 82 83 84 85 86 87 88 89
59 90 91 92 93 94 95 96 97 98 99 54 90 91 92 93 94 95 96 97 98 99
60 100>; 55 100>;
61 default-brightness-level = <80>; 56 default-brightness-level = <80>;
62 status = "disabled"; 57 status = "disabled";
63 }; 58 };
64 }; 59 };
65 60
66 &iomuxc { 61 &iomuxc {
67 pinctrl-names = "default"; 62 pinctrl-names = "default";
68 63
69 smarc-imx8mq { 64 smarc-imx8mq {
70 pinctrl_fec1: fec1grp { 65 pinctrl_fec1: fec1grp {
71 fsl,pins = < 66 fsl,pins = <
72 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 67 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
73 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 68 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
74 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 69 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
75 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 70 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
76 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 71 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
77 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 72 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
78 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 73 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
79 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 74 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
80 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 75 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
81 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 76 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
82 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 77 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
83 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 78 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
84 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 79 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
85 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 80 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
86 >; 81 >;
87 }; 82 };
88 83
89 pinctrl_i2c1: i2c1grp { 84 pinctrl_i2c1: i2c1grp {
90 fsl,pins = < 85 fsl,pins = <
91 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 86 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
92 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 87 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
93 >; 88 >;
94 }; 89 };
95 90
96 pinctrl_i2c2: i2c2grp { 91 pinctrl_i2c2: i2c2grp {
97 fsl,pins = < 92 fsl,pins = <
98 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 93 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
99 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 94 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
100 >; 95 >;
101 }; 96 };
102 97
103 pinctrl_i2c3: i2c3grp { 98 pinctrl_i2c3: i2c3grp {
104 fsl,pins = < 99 fsl,pins = <
105 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 100 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
106 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 101 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
107 >; 102 >;
108 }; 103 };
109 104
110 pinctrl_i2c4: i2c4grp { 105 pinctrl_i2c4: i2c4grp {
111 fsl,pins = < 106 fsl,pins = <
112 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f 107 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
113 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f 108 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
114 >; 109 >;
115 }; 110 };
116 111
117 112
118 pinctrl_pcie0: pcie0grp { 113 pinctrl_pcie0: pcie0grp {
119 fsl,pins = < 114 fsl,pins = <
120 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16 115 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16
121 >; 116 >;
122 }; 117 };
123 118
124 pinctrl_pcie1: pcie1grp { 119 pinctrl_pcie1: pcie1grp {
125 fsl,pins = < 120 fsl,pins = <
126 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16 121 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16
127 >; 122 >;
128 }; 123 };
129 124
130 pinctrl_pwm1: pwm1grp { 125 pinctrl_pwm1: pwm1grp {
131 fsl,pins = < 126 fsl,pins = <
132 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 127 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
133 >; 128 >;
134 }; 129 };
135 130
136 pinctrl_qspi: qspigrp { 131 pinctrl_qspi: qspigrp {
137 fsl,pins = < 132 fsl,pins = <
138 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 133 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
139 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 134 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
140 MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 135 MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82
141 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 136 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
142 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 137 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
143 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 138 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
144 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 139 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
145 140
146 >; 141 >;
147 }; 142 };
148 143
149 pinctrl_uart1: uart1grp { 144 pinctrl_uart1: uart1grp {
150 fsl,pins = < 145 fsl,pins = <
151 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 146 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
152 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 147 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
153 >; 148 >;
154 }; 149 };
155 150
156 pinctrl_uart2: uart2grp { 151 pinctrl_uart2: uart2grp {
157 fsl,pins = < 152 fsl,pins = <
158 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79 153 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79
159 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79 154 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79
160 MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */ 155 MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */
161 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */ 156 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */
162 157
163 >; 158 >;
164 }; 159 };
165 160
166 pinctrl_uart3: uart3grp { 161 pinctrl_uart3: uart3grp {
167 fsl,pins = < 162 fsl,pins = <
168 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 163 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79
169 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 164 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79
170 >; 165 >;
171 }; 166 };
172 167
173 pinctrl_uart4: uart4grp { 168 pinctrl_uart4: uart4grp {
174 fsl,pins = < 169 fsl,pins = <
175 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79 170 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79
176 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79 171 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79
177 >; 172 >;
178 }; 173 };
179 174
180 pinctrl_usdhc1: usdhc1grp { 175 pinctrl_usdhc1: usdhc1grp {
181 fsl,pins = < 176 fsl,pins = <
182 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 177 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
183 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 178 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
184 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 179 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
185 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 180 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
186 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 181 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
187 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 182 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
188 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 183 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
189 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 184 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
190 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 185 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
191 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 186 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
192 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 187 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
193 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 188 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
194 >; 189 >;
195 }; 190 };
196 191
197 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 192 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
198 fsl,pins = < 193 fsl,pins = <
199 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 194 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
200 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 195 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
201 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 196 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
202 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 197 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
203 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 198 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
204 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 199 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
205 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 200 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
206 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 201 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
207 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 202 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
208 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 203 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
209 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 204 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
210 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 205 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
211 >; 206 >;
212 }; 207 };
213 208
214 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 209 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
215 fsl,pins = < 210 fsl,pins = <
216 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 211 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
217 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 212 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
218 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 213 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
219 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 214 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
220 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 215 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
221 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 216 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
222 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 217 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
223 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 218 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
224 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 219 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
225 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 220 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
226 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 221 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
227 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 222 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
228 >; 223 >;
229 }; 224 };
230 225
231 pinctrl_usdhc2_gpio: usdhc2grpgpio { 226 pinctrl_usdhc2_gpio: usdhc2grpgpio {
232 fsl,pins = < 227 fsl,pins = <
233 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 228 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41
234 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 229 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
235 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 230 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
236 >; 231 >;
237 }; 232 };
238 233
239 pinctrl_usdhc2: usdhc2grp { 234 pinctrl_usdhc2: usdhc2grp {
240 fsl,pins = < 235 fsl,pins = <
241 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 236 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
242 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 237 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
243 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 238 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
244 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 239 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
245 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 240 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
246 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 241 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
247 >; 242 >;
248 }; 243 };
249 244
250 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 245 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
251 fsl,pins = < 246 fsl,pins = <
252 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 247 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
253 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 248 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
254 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 249 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
255 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 250 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
256 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 251 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
257 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 252 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
258 >; 253 >;
259 }; 254 };
260 255
261 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 256 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
262 fsl,pins = < 257 fsl,pins = <
263 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 258 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
264 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf 259 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
265 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf 260 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
266 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf 261 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
267 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf 262 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
268 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf 263 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
269 >; 264 >;
270 }; 265 };
271 266
272 pinctrl_sai2: sai2grp { 267 pinctrl_sai2: sai2grp {
273 fsl,pins = < 268 fsl,pins = <
274 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 269 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
275 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 270 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
276 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 271 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
277 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 272 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
278 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 273 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
279 >; 274 >;
280 }; 275 };
281 276
282 pinctrl_wdog: wdoggrp { 277 pinctrl_wdog: wdoggrp {
283 fsl,pins = < 278 fsl,pins = <
284 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 279 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
285 >; 280 >;
286 }; 281 };
287 }; 282 };
288 }; 283 };
289 284
290 &fec1 { 285 &fec1 {
291 pinctrl-names = "default"; 286 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_fec1>; 287 pinctrl-0 = <&pinctrl_fec1>;
293 phy-mode = "rgmii-id"; 288 phy-mode = "rgmii-id";
294 phy-handle = <&ethphy0>; 289 phy-handle = <&ethphy0>;
295 fsl,magic-packet; 290 fsl,magic-packet;
296 interrupt-parent = <&gpio1>; 291 interrupt-parent = <&gpio1>;
297 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 292 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
298 status = "okay"; 293 status = "okay";
299 294
300 mdio { 295 mdio {
301 #address-cells = <1>; 296 #address-cells = <1>;
302 #size-cells = <0>; 297 #size-cells = <0>;
303 298
304 ethphy0: ethernet-phy@0 { 299 ethphy0: ethernet-phy@0 {
305 compatible = "ethernet-phy-ieee802.3-c22"; 300 compatible = "ethernet-phy-ieee802.3-c22";
306 reg = <0>; 301 reg = <0>;
307 at803x,led-act-blind-workaround; 302 at803x,led-act-blind-workaround;
308 at803x,eee-disabled; 303 at803x,eee-disabled;
309 }; 304 };
310 }; 305 };
311 }; 306 };
312 307
313 &i2c1 { 308 &i2c1 {
314 clock-frequency = <100000>; 309 clock-frequency = <100000>;
315 pinctrl-names = "default"; 310 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_i2c1>; 311 pinctrl-0 = <&pinctrl_i2c1>;
317 status = "okay"; 312 status = "okay";
318 313
319 pmic: pfuze100@08 { 314 pmic: pfuze100@08 {
320 compatible = "fsl,pfuze100"; 315 compatible = "fsl,pfuze100";
321 reg = <0x08>; 316 reg = <0x08>;
322 317
323 regulators { 318 regulators {
324 sw1a_reg: sw1ab { 319 sw1a_reg: sw1ab {
325 regulator-min-microvolt = <300000>; 320 regulator-min-microvolt = <300000>;
326 regulator-max-microvolt = <1875000>; 321 regulator-max-microvolt = <1875000>;
327 regulator-always-on; 322 regulator-always-on;
328 }; 323 };
329 324
330 sw1c_reg: sw1c { 325 sw1c_reg: sw1c {
331 regulator-min-microvolt = <300000>; 326 regulator-min-microvolt = <300000>;
332 regulator-max-microvolt = <1875000>; 327 regulator-max-microvolt = <1875000>;
333 regulator-always-on; 328 regulator-always-on;
334 }; 329 };
335 330
336 sw2_reg: sw2 { 331 sw2_reg: sw2 {
337 regulator-min-microvolt = <800000>; 332 regulator-min-microvolt = <800000>;
338 regulator-max-microvolt = <3300000>; 333 regulator-max-microvolt = <3300000>;
339 regulator-always-on; 334 regulator-always-on;
340 }; 335 };
341 336
342 sw3a_reg: sw3ab { 337 sw3a_reg: sw3ab {
343 regulator-min-microvolt = <400000>; 338 regulator-min-microvolt = <400000>;
344 regulator-max-microvolt = <1975000>; 339 regulator-max-microvolt = <1975000>;
345 regulator-always-on; 340 regulator-always-on;
346 }; 341 };
347 342
348 sw4_reg: sw4 { 343 sw4_reg: sw4 {
349 regulator-min-microvolt = <800000>; 344 regulator-min-microvolt = <800000>;
350 regulator-max-microvolt = <3300000>; 345 regulator-max-microvolt = <3300000>;
351 regulator-always-on; 346 regulator-always-on;
352 }; 347 };
353 348
354 swbst_reg: swbst { 349 swbst_reg: swbst {
355 regulator-min-microvolt = <5000000>; 350 regulator-min-microvolt = <5000000>;
356 regulator-max-microvolt = <5150000>; 351 regulator-max-microvolt = <5150000>;
357 }; 352 };
358 353
359 snvs_reg: vsnvs { 354 snvs_reg: vsnvs {
360 regulator-min-microvolt = <1000000>; 355 regulator-min-microvolt = <1000000>;
361 regulator-max-microvolt = <3000000>; 356 regulator-max-microvolt = <3000000>;
362 regulator-always-on; 357 regulator-always-on;
363 }; 358 };
364 359
365 vref_reg: vrefddr { 360 vref_reg: vrefddr {
366 regulator-always-on; 361 regulator-always-on;
367 }; 362 };
368 363
369 vgen1_reg: vgen1 { 364 vgen1_reg: vgen1 {
370 regulator-min-microvolt = <800000>; 365 regulator-min-microvolt = <800000>;
371 regulator-max-microvolt = <1550000>; 366 regulator-max-microvolt = <1550000>;
372 }; 367 };
373 368
374 vgen2_reg: vgen2 { 369 vgen2_reg: vgen2 {
375 regulator-min-microvolt = <800000>; 370 regulator-min-microvolt = <800000>;
376 regulator-max-microvolt = <1550000>; 371 regulator-max-microvolt = <1550000>;
377 regulator-always-on; 372 regulator-always-on;
378 }; 373 };
379 374
380 vgen3_reg: vgen3 { 375 vgen3_reg: vgen3 {
381 regulator-min-microvolt = <1800000>; 376 regulator-min-microvolt = <1800000>;
382 regulator-max-microvolt = <3300000>; 377 regulator-max-microvolt = <3300000>;
383 regulator-always-on; 378 regulator-always-on;
384 }; 379 };
385 380
386 vgen4_reg: vgen4 { 381 vgen4_reg: vgen4 {
387 regulator-min-microvolt = <1800000>; 382 regulator-min-microvolt = <1800000>;
388 regulator-max-microvolt = <3300000>; 383 regulator-max-microvolt = <3300000>;
389 regulator-always-on; 384 regulator-always-on;
390 }; 385 };
391 386
392 vgen5_reg: vgen5 { 387 vgen5_reg: vgen5 {
393 regulator-min-microvolt = <1800000>; 388 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <3300000>; 389 regulator-max-microvolt = <3300000>;
395 regulator-always-on; 390 regulator-always-on;
396 }; 391 };
397 392
398 vgen6_reg: vgen6 { 393 vgen6_reg: vgen6 {
399 regulator-min-microvolt = <1800000>; 394 regulator-min-microvolt = <1800000>;
400 regulator-max-microvolt = <3300000>; 395 regulator-max-microvolt = <3300000>;
401 regulator-always-on; 396 regulator-always-on;
402 }; 397 };
403 }; 398 };
404 }; 399 };
405 400
406 s35390a: s35390a@30 { 401 s35390a: s35390a@30 {
407 compatible = "s35390a"; 402 compatible = "s35390a";
408 reg = <0x30>; 403 reg = <0x30>;
409 }; 404 };
410 405
411 cape_eeprom0: cape_eeprom@57 { 406 cape_eeprom0: cape_eeprom@57 {
412 compatible = "at,24c256"; 407 compatible = "at,24c256";
413 reg = <0x57>; 408 reg = <0x57>;
414 }; 409 };
415 }; 410 };
416 411
417 &i2c2 { 412 &i2c2 {
418 clock-frequency = <100000>; 413 clock-frequency = <100000>;
419 pinctrl-names = "default"; 414 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_i2c2>; 415 pinctrl-0 = <&pinctrl_i2c2>;
421 status = "okay"; 416 status = "okay";
422 417
423 baseboard_eeprom: baseboard_eeprom@50 { 418 baseboard_eeprom: baseboard_eeprom@50 {
424 compatible = "at,24c256"; 419 compatible = "at,24c256";
425 reg = <0x50>; 420 reg = <0x50>;
426 }; 421 };
427 422
428 dsi_lvds_bridge: sn65dsi84@2c { 423 dsi_lvds_bridge: sn65dsi84@2c {
429 status = "disabled"; 424 status = "disabled";
430 reg = <0x2c>; 425 reg = <0x2c>;
431 compatible = "ti,sn65dsi84"; 426 compatible = "ti,sn65dsi84";
432 enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; 427 enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
433 interrupt-parent = <&gpio4>; 428 interrupt-parent = <&gpio4>;
434 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 429 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
435 430
436 /* AUO G070VW01 7-inch 800x480 LVDS Display */ 431 /* AUO G070VW01 7-inch 800x480 LVDS Display */
437 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 432 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
438 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 433 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
439 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 434 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
440 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 435 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
441 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 436 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
442 0x3C 0x3D 0x3E 0xE0 0x0D>; 437 0x3C 0x3D 0x3E 0xE0 0x0D>;
443 438
444 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00 439 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
445 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00 440 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
446 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 441 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
447 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 442 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
448 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 443 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
449 0x00 0x00 0x00 0x01 0x01>; 444 0x00 0x00 0x00 0x01 0x01>;
450 445
451 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */ 446 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
452 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 447 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
453 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 448 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
454 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 449 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
455 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 450 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
456 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 451 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
457 0x3C 0x3D 0x3E 0xE0 0x0D>; 452 0x3C 0x3D 0x3E 0xE0 0x0D>;
458 453
459 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00 454 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
460 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00 455 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
461 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 456 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
462 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00 457 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
463 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 458 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
464 0x00 0x00 0x00 0x01 0x01>;*/ 459 0x00 0x00 0x00 0x01 0x01>;*/
465 460
466 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */ 461 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
467 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 462 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
468 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 463 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
469 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 464 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
470 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 465 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
471 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 466 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
472 0x3C 0x3D 0x3E 0xE0 0x0D>; 467 0x3C 0x3D 0x3E 0xE0 0x0D>;
473 468
474 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00 469 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
475 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00 470 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
476 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00 471 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
477 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00 472 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
478 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00 473 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
479 0x00 0x00 0x00 0x01 0x01>;*/ 474 0x00 0x00 0x00 0x01 0x01>;*/
480 }; 475 };
481 }; 476 };
482 477
483 &i2c3 { 478 &i2c3 {
484 clock-frequency = <100000>; 479 clock-frequency = <100000>;
485 pinctrl-names = "default"; 480 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_i2c3>; 481 pinctrl-0 = <&pinctrl_i2c3>;
487 status = "okay"; 482 status = "okay";
488 }; 483 };
489 484
490 &i2c4 { 485 &i2c4 {
491 clock-frequency = <100000>; 486 clock-frequency = <100000>;
492 pinctrl-names = "default"; 487 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_i2c4>; 488 pinctrl-0 = <&pinctrl_i2c4>;
494 status = "okay"; 489 status = "okay";
495 }; 490 };
496 491
497 &pcie0{ 492 &pcie0{
498 pinctrl-names = "default"; 493 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_pcie0>; 494 pinctrl-0 = <&pinctrl_pcie0>;
500 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; 495 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
501 status = "okay"; 496 status = "okay";
502 }; 497 };
503 498
504 &pcie1{ 499 &pcie1{
505 pinctrl-names = "default"; 500 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_pcie1>; 501 pinctrl-0 = <&pinctrl_pcie1>;
507 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; 502 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
508 status = "okay"; 503 status = "okay";
509 }; 504 };
510 505
511 &pwm1 { 506 &pwm1 {
512 pinctrl-names = "default"; 507 pinctrl-names = "default";
513 pinctrl-0 = <&pinctrl_pwm1>; 508 pinctrl-0 = <&pinctrl_pwm1>;
514 status = "okay"; 509 status = "okay";
515 }; 510 };
516 511
517 &uart1 { /* console */ 512 &uart1 { /* console */
518 pinctrl-names = "default"; 513 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_uart1>; 514 pinctrl-0 = <&pinctrl_uart1>;
520 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; 515 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
521 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 516 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
522 status = "okay"; 517 status = "okay";
523 }; 518 };
524 519
525 &lcdif { 520 &lcdif {
526 status = "okay"; 521 status = "okay";
527 disp-dev = "mipi_dsi_northwest"; 522 disp-dev = "mipi_dsi_northwest";
528 display = <&display0>; 523 display = <&display0>;
529 524
530 display0: display@0 { 525 display0: display@0 {
531 bits-per-pixel = <24>; 526 bits-per-pixel = <24>;
532 bus-width = <24>; 527 bus-width = <24>;
533 528
534 display-timings { 529 display-timings {
535 native-mode = <&timing0>; 530 native-mode = <&timing0>;
536 timing0: timing0 { 531 timing0: timing0 {
537 clock-frequency = <9200000>; 532 clock-frequency = <9200000>;
538 hactive = <480>; 533 hactive = <480>;
539 vactive = <272>; 534 vactive = <272>;
540 hfront-porch = <8>; 535 hfront-porch = <8>;
541 hback-porch = <4>; 536 hback-porch = <4>;
542 hsync-len = <41>; 537 hsync-len = <41>;
543 vback-porch = <2>; 538 vback-porch = <2>;
544 vfront-porch = <4>; 539 vfront-porch = <4>;
545 vsync-len = <10>; 540 vsync-len = <10>;
546 541
547 hsync-active = <0>; 542 hsync-active = <0>;
548 vsync-active = <0>; 543 vsync-active = <0>;
549 de-active = <1>; 544 de-active = <1>;
550 pixelclk-active = <0>; 545 pixelclk-active = <0>;
551 }; 546 };
552 }; 547 };
553 }; 548 };
554 port@0 { 549 port@0 {
555 lcdif_mipi_dsi: mipi-dsi-endpoint { 550 lcdif_mipi_dsi: mipi-dsi-endpoint {
556 remote-endpoint = <&mipi_dsi_in>; 551 remote-endpoint = <&mipi_dsi_in>;
557 }; 552 };
558 }; 553 };
559 }; 554 };
560 555
561 &qspi { 556 &qspi {
562 pinctrl-names = "default"; 557 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_qspi>; 558 pinctrl-0 = <&pinctrl_qspi>;
564 status = "okay"; 559 status = "okay";
565 }; 560 };
566 561
567 &mipi_dsi { 562 &mipi_dsi {
568 reset = <&src>; 563 reset = <&src>;
569 mux-sel = <&gpr>; /* lcdif or dcss */ 564 mux-sel = <&gpr>; /* lcdif or dcss */
570 status = "okay"; 565 status = "okay";
571 566
572 port@1 { 567 port@1 {
573 mipi_dsi_in: endpoint { 568 mipi_dsi_in: endpoint {
574 remote-endpoint = <&lcdif_mipi_dsi>; 569 remote-endpoint = <&lcdif_mipi_dsi>;
575 }; 570 };
576 }; 571 };
577 }; 572 };
578 573
579 &uart2 { 574 &uart2 {
580 pinctrl-names = "default"; 575 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_uart2>; 576 pinctrl-0 = <&pinctrl_uart2>;
582 assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>; 577 assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
583 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 578 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
584 fsl,uart-has-rtscts; 579 fsl,uart-has-rtscts;
585 status = "okay"; 580 status = "okay";
586 }; 581 };
587 582
588 &uart3 { 583 &uart3 {
589 pinctrl-names = "default"; 584 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart3>; 585 pinctrl-0 = <&pinctrl_uart3>;
591 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; 586 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
592 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 587 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
593 status = "okay"; 588 status = "okay";
594 }; 589 };
595 590
596 &uart4 { 591 &uart4 {
597 pinctrl-names = "default"; 592 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_uart4>; 593 pinctrl-0 = <&pinctrl_uart4>;
599 assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>; 594 assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
600 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 595 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
601 fsl,uart-has-rtscts; 596 fsl,uart-has-rtscts;
602 status = "okay"; 597 status = "okay";
603 }; 598 };
604 599
605 &usdhc1 { 600 &usdhc1 {
606 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 601 pinctrl-names = "default", "state_100mhz", "state_200mhz";
607 pinctrl-0 = <&pinctrl_usdhc1>; 602 pinctrl-0 = <&pinctrl_usdhc1>;
608 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 603 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
609 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 604 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
610 bus-width = <8>; 605 bus-width = <8>;
611 non-removable; 606 non-removable;
612 status = "okay"; 607 status = "okay";
613 }; 608 };
614 609
615 &usdhc2 { 610 &usdhc2 {
616 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 611 pinctrl-names = "default", "state_100mhz", "state_200mhz";
617 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 612 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
618 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 613 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
619 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 614 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
620 bus-width = <4>; 615 bus-width = <4>;
621 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 616 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
622 vmmc-supply = <&reg_usdhc2_vmmc>; 617 vmmc-supply = <&reg_usdhc2_vmmc>;
623 status = "okay"; 618 status = "okay";
624 }; 619 };
625 620
626 &usb3_phy0 { 621 &usb3_phy0 {
627 status = "okay"; 622 status = "okay";
628 }; 623 };
629 624
630 &usb3_0 { 625 &usb3_0 {
631 status = "okay"; 626 status = "okay";
632 }; 627 };
633 628
634 &usb_dwc3_0 { 629 &usb_dwc3_0 {
635 status = "okay"; 630 status = "okay";
636 dr_mode = "peripheral"; 631 dr_mode = "peripheral";
637 }; 632 };
638 633
639 &usb3_phy1 { 634 &usb3_phy1 {
640 status = "okay"; 635 status = "okay";
641 }; 636 };
642 637
643 &usb3_1 { 638 &usb3_1 {
644 status = "okay"; 639 status = "okay";
645 }; 640 };
646 641
647 &usb_dwc3_1 { 642 &usb_dwc3_1 {
648 status = "okay"; 643 status = "okay";
649 dr_mode = "host"; 644 dr_mode = "host";
650 }; 645 };
651 646
652 &sai2 { 647 &sai2 {
653 pinctrl-names = "default"; 648 pinctrl-names = "default";
654 pinctrl-0 = <&pinctrl_sai2>; 649 pinctrl-0 = <&pinctrl_sai2>;
655 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, 650 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
656 <&clk IMX8MQ_AUDIO_PLL1>, 651 <&clk IMX8MQ_AUDIO_PLL1>,
657 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, 652 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>,
658 <&clk IMX8MQ_CLK_SAI2_DIV>; 653 <&clk IMX8MQ_CLK_SAI2_DIV>;
659 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 654 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
660 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; 655 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>;
661 status = "okay"; 656 status = "okay";
662 }; 657 };
663 658
664 &gpu { 659 &gpu {
665 status = "okay"; 660 status = "okay";
666 }; 661 };
667 662
668 &vpu { 663 &vpu {
669 status = "okay"; 664 status = "okay";
670 }; 665 };
671 666
672 &wdog1 { 667 &wdog1 {
673 pinctrl-names = "default"; 668 pinctrl-names = "default";
674 pinctrl-0 = <&pinctrl_wdog>; 669 pinctrl-0 = <&pinctrl_wdog>;
675 fsl,ext-reset-output; 670 fsl,ext-reset-output;
676 status = "okay"; 671 status = "okay";
677 }; 672 };
678 673
board/embedian/smarcimx8mq/smarcimx8mq.c
Diff comments   View file @ 85f8466
1 /* 1 /*
2 * Copyright 2016 Freescale Semiconductor, Inc. 2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP 3 * Copyright 2017-2018 NXP
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <malloc.h> 9 #include <malloc.h>
10 #include <errno.h> 10 #include <errno.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <miiphy.h> 12 #include <miiphy.h>
13 #include <netdev.h> 13 #include <netdev.h>
14 #include <asm/mach-imx/iomux-v3.h> 14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm-generic/gpio.h> 15 #include <asm-generic/gpio.h>
16 #include <fsl_esdhc.h> 16 #include <fsl_esdhc.h>
17 #include <mmc.h> 17 #include <mmc.h>
18 #include <asm/arch/imx8mq_pins.h> 18 #include <asm/arch/imx8mq_pins.h>
19 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/gpio.h> 20 #include <asm/mach-imx/gpio.h>
21 #include <asm/mach-imx/mxc_i2c.h> 21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/arch/clock.h> 22 #include <asm/arch/clock.h>
23 #include <asm/mach-imx/video.h> 23 #include <asm/mach-imx/video.h>
24 #include <asm/arch/video_common.h> 24 #include <asm/arch/video_common.h>
25 #include <spl.h> 25 #include <spl.h>
26 #include <power/pmic.h> 26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h> 27 #include <power/pfuze100_pmic.h>
28 #include <dm.h> 28 #include <dm.h>
29 #include "../../freescale/common/tcpc.h" 29 #include "../../freescale/common/tcpc.h"
30 #include "../../freescale/common/pfuze.h" 30 #include "../../freescale/common/pfuze.h"
31 #include "../../freescale/common/mmc.c" 31 #include "../../freescale/common/mmc.c"
32 #include <usb.h> 32 #include <usb.h>
33 #include <dwc3-uboot.h> 33 #include <dwc3-uboot.h>
34 34
35 DECLARE_GLOBAL_DATA_PTR; 35 DECLARE_GLOBAL_DATA_PTR;
36 36
37 #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) 37 #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
38 38
39 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) 39 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
40 40
41 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 41 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
42 42
43 #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 43 #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
44 44
45 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 45 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
46 46
47 static iomux_v3_cfg_t const wdog_pads[] = { 47 static iomux_v3_cfg_t const wdog_pads[] = {
48 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), 48 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
49 }; 49 };
50 50
51 #ifdef CONFIG_FSL_QSPI 51 #ifdef CONFIG_FSL_QSPI
52 static iomux_v3_cfg_t const qspi_pads[] = { 52 static iomux_v3_cfg_t const qspi_pads[] = {
53 IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), 53 IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
54 IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), 54 IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
55 55
56 IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 56 IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
57 IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 57 IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
58 IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 58 IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
59 IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 59 IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
60 }; 60 };
61 61
62 int board_qspi_init(void) 62 int board_qspi_init(void)
63 { 63 {
64 imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); 64 imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
65 65
66 set_clk_qspi(); 66 set_clk_qspi();
67 67
68 return 0; 68 return 0;
69 } 69 }
70 #endif 70 #endif
71 71
72 #ifdef CONFIG_CONSOLE_SER3 72 #ifdef CONFIG_CONSOLE_SER3
73 static iomux_v3_cfg_t const uart1_pads[] = { 73 static iomux_v3_cfg_t const uart1_pads[] = {
74 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 74 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
75 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 75 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
76 }; 76 };
77 #endif 77 #endif
78 78
79 #ifdef CONFIG_CONSOLE_SER2 79 #ifdef CONFIG_CONSOLE_SER2
80 static iomux_v3_cfg_t const uart2_pads[] = { 80 static iomux_v3_cfg_t const uart2_pads[] = {
81 IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 81 IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
82 IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 82 IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
83 }; 83 };
84 #endif 84 #endif
85 85
86 #ifdef CONFIG_CONSOLE_SER1 86 #ifdef CONFIG_CONSOLE_SER1
87 static iomux_v3_cfg_t const uart3_pads[] = { 87 static iomux_v3_cfg_t const uart3_pads[] = {
88 IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 88 IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
89 IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 89 IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
90 }; 90 };
91 #endif 91 #endif
92 92
93 #ifdef CONFIG_CONSOLE_SER0 93 #ifdef CONFIG_CONSOLE_SER0
94 static iomux_v3_cfg_t const uart4_pads[] = { 94 static iomux_v3_cfg_t const uart4_pads[] = {
95 IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 95 IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
96 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 96 IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
97 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 97 IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
98 IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 98 IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
99 }; 99 };
100 #endif 100 #endif
101 101
102 /* SPI0*/ 102 /* SPI0*/
103 static iomux_v3_cfg_t const ecspi1_pads[] = { 103 static iomux_v3_cfg_t const ecspi1_pads[] = {
104 IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(QSPI_PAD_CTRL), 104 IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(QSPI_PAD_CTRL),
105 IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(QSPI_PAD_CTRL), 105 IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(QSPI_PAD_CTRL),
106 IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), 106 IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
107 107
108 IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ 108 IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/
109 IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ 109 IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/
110 IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ 110 IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/
111 IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ 111 IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/
112 }; 112 };
113 113
114 /* MISC PINs */ 114 /* MISC PINs */
115 static iomux_v3_cfg_t const misc_pads[] = { 115 static iomux_v3_cfg_t const misc_pads[] = {
116 IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE*/ 116 IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE*/
117 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /*S148, LID#*/ 117 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /*S148, LID#*/
118 IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), /*S149, SLEEP#*/ 118 IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), /*S149, SLEEP#*/
119 IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/ 119 IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/
120 IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), /*S152, CHARGER_PRSNT#*/ 120 IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), /*S152, CHARGER_PRSNT#*/
121 IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /*S153, CARRIER_STBY#*/ 121 IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /*S153, CARRIER_STBY#*/
122 IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP), /*S156, BATLOW#*/ 122 IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP), /*S156, BATLOW#*/
123 IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN0_INT#*/ 123 IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN0_INT#*/
124 IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN1_INT#*/ 124 IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN1_INT#*/
125 }; 125 };
126 126
127 static void setup_iomux_misc(void) 127 static void setup_iomux_misc(void)
128 { 128 {
129 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); 129 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
130 130
131 /* Set CARRIER_LID# as Input*/ 131 /* Set CARRIER_LID# as Input*/
132 gpio_request(IMX_GPIO_NR(1, 9), "LID#"); 132 gpio_request(IMX_GPIO_NR(1, 9), "LID#");
133 gpio_direction_input(IMX_GPIO_NR(1, 9)); 133 gpio_direction_input(IMX_GPIO_NR(1, 9));
134 /* Set CARRIER_SLEEP# as Input*/ 134 /* Set CARRIER_SLEEP# as Input*/
135 gpio_request(IMX_GPIO_NR(1, 10), "SLEEP#"); 135 gpio_request(IMX_GPIO_NR(1, 10), "SLEEP#");
136 gpio_direction_input(IMX_GPIO_NR(1, 10)); 136 gpio_direction_input(IMX_GPIO_NR(1, 10));
137 /* Set CARRIER_CHARGING# as Input*/ 137 /* Set CARRIER_CHARGING# as Input*/
138 gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#"); 138 gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#");
139 gpio_direction_input(IMX_GPIO_NR(1, 01)); 139 gpio_direction_input(IMX_GPIO_NR(1, 01));
140 /* Set CARRIER_CHARGER_PRSNT# as Input*/ 140 /* Set CARRIER_CHARGER_PRSNT# as Input*/
141 gpio_request(IMX_GPIO_NR(1, 12), "CHARGER_PRSNT#"); 141 gpio_request(IMX_GPIO_NR(1, 12), "CHARGER_PRSNT#");
142 gpio_direction_input(IMX_GPIO_NR(1, 12)); 142 gpio_direction_input(IMX_GPIO_NR(1, 12));
143 /* Set CARRIER_STBY# as Output High*/ 143 /* Set CARRIER_STBY# as Output High*/
144 gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#"); 144 gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#");
145 gpio_direction_output(IMX_GPIO_NR(5, 02) , 1); 145 gpio_direction_output(IMX_GPIO_NR(5, 02) , 1);
146 /* Set CARRIER_BATLOW# as Input*/ 146 /* Set CARRIER_BATLOW# as Input*/
147 gpio_request(IMX_GPIO_NR(1, 8), "BATLOW#"); 147 gpio_request(IMX_GPIO_NR(1, 8), "BATLOW#");
148 gpio_direction_input(IMX_GPIO_NR(1, 8)); 148 gpio_direction_input(IMX_GPIO_NR(1, 8));
149 /* Set PCIE_WAKE# as Input*/ 149 /* Set PCIE_WAKE# as Input*/
150 gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#"); 150 gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#");
151 gpio_direction_input(IMX_GPIO_NR(3, 5)); 151 gpio_direction_input(IMX_GPIO_NR(3, 5));
152 /* Set CAN0_INT# as Input*/ 152 /* Set CAN0_INT# as Input*/
153 gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#"); 153 gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#");
154 gpio_direction_input(IMX_GPIO_NR(3, 18)); 154 gpio_direction_input(IMX_GPIO_NR(3, 18));
155 /* Set CAN1_INT# as Input*/ 155 /* Set CAN1_INT# as Input*/
156 gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#"); 156 gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#");
157 gpio_direction_input(IMX_GPIO_NR(3, 16)); 157 gpio_direction_input(IMX_GPIO_NR(3, 16));
158 } 158 }
159 159
160 /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/ 160 /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/
161 static iomux_v3_cfg_t const gpio_pads[] = { 161 static iomux_v3_cfg_t const gpio_pads[] = {
162 IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP), /*P108, GPIO0*/ 162 IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP), /*P108, GPIO0*/
163 IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), /*P109, GPIO1*/ 163 IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), /*P109, GPIO1*/
164 IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P110, GPIO2*/ 164 IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P110, GPIO2*/
165 IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*P111, GPIO3*/ 165 IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*P111, GPIO3*/
166 IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*P112, GPIO4*/ 166 IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*P112, GPIO4*/
167 IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /*P113, GPIO5*/ 167 IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /*P113, GPIO5*/
168 IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO6*/ 168 IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO6*/
169 IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO7*/ 169 IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO7*/
170 IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO8*/ 170 IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO8*/
171 IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO9*/ 171 IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO9*/
172 IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO10*/ 172 IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO10*/
173 IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO11*/ 173 IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO11*/
174 }; 174 };
175 175
176 static void setup_iomux_gpio(void) 176 static void setup_iomux_gpio(void)
177 { 177 {
178 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); 178 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
179 179
180 /* Set GPIO0 as Output Low*/ 180 /* Set GPIO0 as Output Low*/
181 gpio_request(IMX_GPIO_NR(3, 25), "GPIO0"); 181 gpio_request(IMX_GPIO_NR(3, 25), "GPIO0");
182 gpio_direction_output(IMX_GPIO_NR(3, 25), 0); 182 gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
183 /* Set GPIO1 as Output Low*/ 183 /* Set GPIO1 as Output Low*/
184 gpio_request(IMX_GPIO_NR(3, 19), "GPIO1"); 184 gpio_request(IMX_GPIO_NR(3, 19), "GPIO1");
185 gpio_direction_output(IMX_GPIO_NR(3, 19), 0); 185 gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
186 /* Set GPIO2 as Output Low*/ 186 /* Set GPIO2 as Output Low*/
187 gpio_request(IMX_GPIO_NR(3, 20), "GPIO2"); 187 gpio_request(IMX_GPIO_NR(3, 20), "GPIO2");
188 gpio_direction_output(IMX_GPIO_NR(3, 20), 0); 188 gpio_direction_output(IMX_GPIO_NR(3, 20), 0);
189 /* Set GPIO3 as Output Low*/ 189 /* Set GPIO3 as Output Low*/
190 gpio_request(IMX_GPIO_NR(3, 21), "GPIO3"); 190 gpio_request(IMX_GPIO_NR(3, 21), "GPIO3");
191 gpio_direction_output(IMX_GPIO_NR(3, 21), 0); 191 gpio_direction_output(IMX_GPIO_NR(3, 21), 0);
192 /* Set GPIO4 as Output Low*/ 192 /* Set GPIO4 as Output Low*/
193 gpio_request(IMX_GPIO_NR(3, 22), "GPIO4"); 193 gpio_request(IMX_GPIO_NR(3, 22), "GPIO4");
194 gpio_direction_output(IMX_GPIO_NR(3, 22), 0); 194 gpio_direction_output(IMX_GPIO_NR(3, 22), 0);
195 /* Set GPIO5 as Output Low*/ 195 /* Set GPIO5 as Output Low*/
196 gpio_request(IMX_GPIO_NR(5, 3), "GPIO5"); 196 gpio_request(IMX_GPIO_NR(5, 3), "GPIO5");
197 gpio_direction_output(IMX_GPIO_NR(5, 3), 0); 197 gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
198 /* Set GPIO6 as Input*/ 198 /* Set GPIO6 as Input*/
199 gpio_request(IMX_GPIO_NR(5, 4), "GPIO6"); 199 gpio_request(IMX_GPIO_NR(5, 4), "GPIO6");
200 gpio_direction_input(IMX_GPIO_NR(5, 4)); 200 gpio_direction_input(IMX_GPIO_NR(5, 4));
201 /* Set GPIO7 as Input*/ 201 /* Set GPIO7 as Input*/
202 gpio_request(IMX_GPIO_NR(3, 23), "GPIO7"); 202 gpio_request(IMX_GPIO_NR(3, 23), "GPIO7");
203 gpio_direction_input(IMX_GPIO_NR(3, 23)); 203 gpio_direction_input(IMX_GPIO_NR(3, 23));
204 /* Set GPIO8 as Input*/ 204 /* Set GPIO8 as Input*/
205 gpio_request(IMX_GPIO_NR(3, 24), "GPIO8"); 205 gpio_request(IMX_GPIO_NR(3, 24), "GPIO8");
206 gpio_direction_input(IMX_GPIO_NR(3, 24)); 206 gpio_direction_input(IMX_GPIO_NR(3, 24));
207 /* Set GPIO9 as Input*/ 207 /* Set GPIO9 as Input*/
208 gpio_request(IMX_GPIO_NR(4, 11), "GPIO9"); 208 gpio_request(IMX_GPIO_NR(4, 11), "GPIO9");
209 gpio_direction_input(IMX_GPIO_NR(4, 11)); 209 gpio_direction_input(IMX_GPIO_NR(4, 11));
210 /* Set GPIO10 as Input*/ 210 /* Set GPIO10 as Input*/
211 gpio_request(IMX_GPIO_NR(4, 10), "GPIO10"); 211 gpio_request(IMX_GPIO_NR(4, 10), "GPIO10");
212 gpio_direction_input(IMX_GPIO_NR(4, 10)); 212 gpio_direction_input(IMX_GPIO_NR(4, 10));
213 /* Set GPIO11 as Input*/ 213 /* Set GPIO11 as Input*/
214 gpio_request(IMX_GPIO_NR(4, 20), "GPIO11"); 214 gpio_request(IMX_GPIO_NR(4, 20), "GPIO11");
215 gpio_direction_input(IMX_GPIO_NR(4, 20)); 215 gpio_direction_input(IMX_GPIO_NR(4, 20));
216 } 216 }
217 217
218 218
219 int board_early_init_f(void) 219 int board_early_init_f(void)
220 { 220 {
221 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 221 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
222 222
223 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 223 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
224 224
225 set_wdog_reset(wdog); 225 set_wdog_reset(wdog);
226 226
227 #ifdef CONFIG_CONSOLE_SER0 227 #ifdef CONFIG_CONSOLE_SER0
228 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 228 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
229 #endif 229 #endif
230 #ifdef CONFIG_CONSOLE_SER1 230 #ifdef CONFIG_CONSOLE_SER1
231 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 231 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
232 #endif 232 #endif
233 #ifdef CONFIG_CONSOLE_SER2 233 #ifdef CONFIG_CONSOLE_SER2
234 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 234 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
235 #endif 235 #endif
236 #ifdef CONFIG_CONSOLE_SER3 236 #ifdef CONFIG_CONSOLE_SER3
237 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 237 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
238 #endif 238 #endif
239 239
240 return 0; 240 return 0;
241 } 241 }
242 242
243 #ifdef CONFIG_BOARD_POSTCLK_INIT 243 #ifdef CONFIG_BOARD_POSTCLK_INIT
244 int board_postclk_init(void) 244 int board_postclk_init(void)
245 { 245 {
246 /* TODO */ 246 /* TODO */
247 return 0; 247 return 0;
248 } 248 }
249 #endif 249 #endif
250 250
251 int dram_init(void) 251 int dram_init(void)
252 { 252 {
253 /* rom_pointer[1] contains the size of TEE occupies */ 253 /* rom_pointer[1] contains the size of TEE occupies */
254 if (rom_pointer[1]) 254 if (rom_pointer[1])
255 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; 255 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
256 else 256 else
257 gd->ram_size = PHYS_SDRAM_SIZE; 257 gd->ram_size = PHYS_SDRAM_SIZE;
258 258
259 return 0; 259 return 0;
260 } 260 }
261 261
262 #ifdef CONFIG_SYS_I2C 262 #ifdef CONFIG_SYS_I2C
263 /*I2C2, I2C_CAM0 and I2C_LCD*/ 263 /*I2C2, I2C_CAM0 and I2C_LCD*/
264 struct i2c_pads_info i2c_pad_info2 = { 264 struct i2c_pads_info i2c_pad_info2 = {
265 .scl = { 265 .scl = {
266 .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL, 266 .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL,
267 .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL, 267 .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL,
268 .gp = IMX_GPIO_NR(5, 16), 268 .gp = IMX_GPIO_NR(5, 16),
269 }, 269 },
270 .sda = { 270 .sda = {
271 .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL, 271 .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL,
272 .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL, 272 .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL,
273 .gp = IMX_GPIO_NR(5, 17), 273 .gp = IMX_GPIO_NR(5, 17),
274 }, 274 },
275 }; 275 };
276 276
277 /*I2C3, I2C_GP*/ 277 /*I2C3, I2C_GP*/
278 struct i2c_pads_info i2c_pad_info3 = { 278 struct i2c_pads_info i2c_pad_info3 = {
279 .scl = { 279 .scl = {
280 .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL, 280 .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL,
281 .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL, 281 .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL,
282 .gp = IMX_GPIO_NR(5, 18), 282 .gp = IMX_GPIO_NR(5, 18),
283 }, 283 },
284 .sda = { 284 .sda = {
285 .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL, 285 .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL,
286 .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL, 286 .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL,
287 .gp = IMX_GPIO_NR(5, 19), 287 .gp = IMX_GPIO_NR(5, 19),
288 }, 288 },
289 }; 289 };
290 290
291 /*I2C4, I2C_CAM1*/ 291 /*I2C4, I2C_CAM1*/
292 struct i2c_pads_info i2c_pad_info4 = { 292 struct i2c_pads_info i2c_pad_info4 = {
293 .scl = { 293 .scl = {
294 .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | I2C_PAD_CTRL, 294 .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | I2C_PAD_CTRL,
295 .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | I2C_PAD_CTRL, 295 .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | I2C_PAD_CTRL,
296 .gp = IMX_GPIO_NR(5, 20), 296 .gp = IMX_GPIO_NR(5, 20),
297 }, 297 },
298 .sda = { 298 .sda = {
299 .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | I2C_PAD_CTRL, 299 .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | I2C_PAD_CTRL,
300 .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | I2C_PAD_CTRL, 300 .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | I2C_PAD_CTRL,
301 .gp = IMX_GPIO_NR(5, 21), 301 .gp = IMX_GPIO_NR(5, 21),
302 }, 302 },
303 }; 303 };
304 #endif 304 #endif
305 305
306 #ifdef CONFIG_OF_BOARD_SETUP 306 #ifdef CONFIG_OF_BOARD_SETUP
307 int ft_board_setup(void *blob, bd_t *bd) 307 int ft_board_setup(void *blob, bd_t *bd)
308 { 308 {
309 return 0; 309 return 0;
310 } 310 }
311 #endif 311 #endif
312 312
313 /* Get the top of usable RAM */ 313 /* Get the top of usable RAM */
314 ulong board_get_usable_ram_top(ulong total_size) 314 ulong board_get_usable_ram_top(ulong total_size)
315 { 315 {
316 316
317 //printf("board_get_usable_ram_top total_size is 0x%lx \n", total_size); 317 //printf("board_get_usable_ram_top total_size is 0x%lx \n", total_size);
318 318
319 if(gd->ram_top > 0x100000000) 319 if(gd->ram_top > 0x100000000)
320 gd->ram_top = 0x100000000; 320 gd->ram_top = 0x100000000;
321 321
322 return gd->ram_top; 322 return gd->ram_top;
323 } 323 }
324 324
325 #ifdef CONFIG_FEC_MXC 325 #ifdef CONFIG_FEC_MXC
326 #define FEC_RST_PAD IMX_GPIO_NR(1, 11) 326 #define FEC_RST_PAD IMX_GPIO_NR(1, 11)
327 static iomux_v3_cfg_t const fec1_irq_pads[] = { 327 static iomux_v3_cfg_t const fec1_irq_pads[] = {
328 IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), 328 IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
329 }; 329 };
330 330
331 static void setup_iomux_fec(void) 331 static void setup_iomux_fec(void)
332 { 332 {
333 imx_iomux_v3_setup_multiple_pads(fec1_irq_pads, 333 imx_iomux_v3_setup_multiple_pads(fec1_irq_pads,
334 ARRAY_SIZE(fec1_irq_pads)); 334 ARRAY_SIZE(fec1_irq_pads));
335 335
336 gpio_request(IMX_GPIO_NR(1, 11), "fec1_irq"); 336 gpio_request(IMX_GPIO_NR(1, 11), "fec1_irq");
337 gpio_direction_input(IMX_GPIO_NR(1, 11)); 337 gpio_direction_input(IMX_GPIO_NR(1, 11));
338 } 338 }
339 339
340 static int setup_fec(void) 340 static int setup_fec(void)
341 { 341 {
342 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 342 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
343 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 343 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
344 344
345 setup_iomux_fec(); 345 setup_iomux_fec();
346 346
347 /* Use 125M anatop REF_CLK1 for ENET1, not from external */ 347 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
348 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 348 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
349 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); 349 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
350 return set_clk_enet(ENET_125MHZ); 350 return set_clk_enet(ENET_125MHZ);
351 } 351 }
352 352
353 353
354 int board_phy_config(struct phy_device *phydev) 354 int board_phy_config(struct phy_device *phydev)
355 { 355 {
356 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 356 /* enable rgmii rxc skew and phy mode select to RGMII copper */
357 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 357 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
358 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 358 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
359 359
360 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 360 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
361 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 361 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
362 362
363 if (phydev->drv->config) 363 if (phydev->drv->config)
364 phydev->drv->config(phydev); 364 phydev->drv->config(phydev);
365 return 0; 365 return 0;
366 } 366 }
367 #endif 367 #endif
368 368
369 static void setup_iomux_ecspi1(void) 369 static void setup_iomux_ecspi1(void)
370 { 370 {
371 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 371 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
372 ARRAY_SIZE(ecspi1_pads)); 372 ARRAY_SIZE(ecspi1_pads));
373 } 373 }
374 374
375 int board_spi_cs_gpio(unsigned bus, unsigned cs) 375 int board_spi_cs_gpio(unsigned bus, unsigned cs)
376 { 376 {
377 gpio_request(IMX_GPIO_NR(5, 9), "espi1_cs0"); 377 gpio_request(IMX_GPIO_NR(5, 9), "espi1_cs0");
378 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(5, 9)) : -1; 378 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(5, 9)) : -1;
379 gpio_request(IMX_GPIO_NR(1, 0), "espi1_cs1"); 379 gpio_request(IMX_GPIO_NR(1, 0), "espi1_cs1");
380 return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(1, 0)) : -1; 380 return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(1, 0)) : -1;
381 gpio_request(IMX_GPIO_NR(3, 15), "espi1_cs2"); 381 gpio_request(IMX_GPIO_NR(3, 15), "espi1_cs2");
382 return (bus == 0 && cs == 2) ? (IMX_GPIO_NR(3, 15)) : -1; 382 return (bus == 0 && cs == 2) ? (IMX_GPIO_NR(3, 15)) : -1;
383 gpio_request(IMX_GPIO_NR(3, 17), "espi1_cs3"); 383 gpio_request(IMX_GPIO_NR(3, 17), "espi1_cs3");
384 return (bus == 0 && cs == 3) ? (IMX_GPIO_NR(3, 17)) : -1; 384 return (bus == 0 && cs == 3) ? (IMX_GPIO_NR(3, 17)) : -1;
385 } 385 }
386 386
387 #ifdef CONFIG_USB_DWC3 387 #ifdef CONFIG_USB_DWC3
388 388
389 #define USB_PHY_CTRL0 0xF0040 389 #define USB_PHY_CTRL0 0xF0040
390 #define USB_PHY_CTRL0_REF_SSP_EN BIT(2) 390 #define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
391 391
392 #define USB_PHY_CTRL1 0xF0044 392 #define USB_PHY_CTRL1 0xF0044
393 #define USB_PHY_CTRL1_RESET BIT(0) 393 #define USB_PHY_CTRL1_RESET BIT(0)
394 #define USB_PHY_CTRL1_COMMONONN BIT(1) 394 #define USB_PHY_CTRL1_COMMONONN BIT(1)
395 #define USB_PHY_CTRL1_ATERESET BIT(3) 395 #define USB_PHY_CTRL1_ATERESET BIT(3)
396 #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) 396 #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
397 #define USB_PHY_CTRL1_VDATDETENB0 BIT(20) 397 #define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
398 398
399 #define USB_PHY_CTRL2 0xF0048 399 #define USB_PHY_CTRL2 0xF0048
400 #define USB_PHY_CTRL2_TXENABLEN0 BIT(8) 400 #define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
401 401
402 static struct dwc3_device dwc3_device_data = { 402 static struct dwc3_device dwc3_device_data = {
403 .maximum_speed = USB_SPEED_HIGH, 403 .maximum_speed = USB_SPEED_HIGH,
404 .base = USB1_BASE_ADDR, 404 .base = USB1_BASE_ADDR,
405 .dr_mode = USB_DR_MODE_PERIPHERAL, 405 .dr_mode = USB_DR_MODE_PERIPHERAL,
406 .index = 0, 406 .index = 0,
407 .power_down_scale = 2, 407 .power_down_scale = 2,
408 }; 408 };
409 409
410 int usb_gadget_handle_interrupts(void) 410 int usb_gadget_handle_interrupts(void)
411 { 411 {
412 dwc3_uboot_handle_interrupt(0); 412 dwc3_uboot_handle_interrupt(0);
413 return 0; 413 return 0;
414 } 414 }
415 415
416 static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) 416 static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
417 { 417 {
418 u32 RegData; 418 u32 RegData;
419 419
420 RegData = readl(dwc3->base + USB_PHY_CTRL1); 420 RegData = readl(dwc3->base + USB_PHY_CTRL1);
421 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | 421 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
422 USB_PHY_CTRL1_COMMONONN); 422 USB_PHY_CTRL1_COMMONONN);
423 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; 423 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
424 writel(RegData, dwc3->base + USB_PHY_CTRL1); 424 writel(RegData, dwc3->base + USB_PHY_CTRL1);
425 425
426 RegData = readl(dwc3->base + USB_PHY_CTRL0); 426 RegData = readl(dwc3->base + USB_PHY_CTRL0);
427 RegData |= USB_PHY_CTRL0_REF_SSP_EN; 427 RegData |= USB_PHY_CTRL0_REF_SSP_EN;
428 writel(RegData, dwc3->base + USB_PHY_CTRL0); 428 writel(RegData, dwc3->base + USB_PHY_CTRL0);
429 429
430 RegData = readl(dwc3->base + USB_PHY_CTRL2); 430 RegData = readl(dwc3->base + USB_PHY_CTRL2);
431 RegData |= USB_PHY_CTRL2_TXENABLEN0; 431 RegData |= USB_PHY_CTRL2_TXENABLEN0;
432 writel(RegData, dwc3->base + USB_PHY_CTRL2); 432 writel(RegData, dwc3->base + USB_PHY_CTRL2);
433 433
434 RegData = readl(dwc3->base + USB_PHY_CTRL1); 434 RegData = readl(dwc3->base + USB_PHY_CTRL1);
435 RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); 435 RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
436 writel(RegData, dwc3->base + USB_PHY_CTRL1); 436 writel(RegData, dwc3->base + USB_PHY_CTRL1);
437 } 437 }
438 #endif 438 #endif
439 439
440 /*USB Enable Over-Current Pin Setting*/ 440 /*USB Enable Over-Current Pin Setting*/
441 static iomux_v3_cfg_t const usb_en_oc_pads[] = { 441 static iomux_v3_cfg_t const usb_en_oc_pads[] = {
442 IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), 442 IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
443 IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), 443 IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
444 IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), 444 IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
445 IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), 445 IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
446 }; 446 };
447 447
448 static void setup_iomux_usb_en_oc(void) 448 static void setup_iomux_usb_en_oc(void)
449 { 449 {
450 imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads, 450 imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads,
451 ARRAY_SIZE(usb_en_oc_pads)); 451 ARRAY_SIZE(usb_en_oc_pads));
452 452
453 gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#"); 453 gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#");
454 gpio_direction_input(IMX_GPIO_NR(3, 10)); 454 gpio_direction_input(IMX_GPIO_NR(3, 10));
455 gpio_request(IMX_GPIO_NR(3, 11), "usb1_en_oc#"); 455 gpio_request(IMX_GPIO_NR(3, 11), "usb1_en_oc#");
456 gpio_direction_input(IMX_GPIO_NR(3, 11)); 456 gpio_direction_input(IMX_GPIO_NR(3, 11));
457 gpio_request(IMX_GPIO_NR(3, 12), "usb2_en_oc#"); 457 gpio_request(IMX_GPIO_NR(3, 12), "usb2_en_oc#");
458 gpio_direction_input(IMX_GPIO_NR(3, 12)); 458 gpio_direction_input(IMX_GPIO_NR(3, 12));
459 gpio_request(IMX_GPIO_NR(3, 13), "usb3_en_oc#"); 459 gpio_request(IMX_GPIO_NR(3, 13), "usb3_en_oc#");
460 gpio_direction_input(IMX_GPIO_NR(3, 13)); 460 gpio_direction_input(IMX_GPIO_NR(3, 13));
461 } 461 }
462 462
463 #ifdef CONFIG_USB_TCPC 463 #ifdef CONFIG_USB_TCPC
464 struct tcpc_port port; 464 struct tcpc_port port;
465 struct tcpc_port_config port_config = { 465 struct tcpc_port_config port_config = {
466 .i2c_bus = 0, 466 .i2c_bus = 0,
467 .addr = 0x50, 467 .addr = 0x50,
468 .port_type = TYPEC_PORT_UFP, 468 .port_type = TYPEC_PORT_UFP,
469 .max_snk_mv = 20000, 469 .max_snk_mv = 20000,
470 .max_snk_ma = 3000, 470 .max_snk_ma = 3000,
471 .max_snk_mw = 15000, 471 .max_snk_mw = 15000,
472 .op_snk_mv = 9000, 472 .op_snk_mv = 9000,
473 }; 473 };
474 474
475 #define USB_TYPEC_SEL IMX_GPIO_NR(3, 15) 475 #define USB_TYPEC_SEL IMX_GPIO_NR(3, 15)
476 476
477 static iomux_v3_cfg_t ss_mux_gpio[] = { 477 static iomux_v3_cfg_t ss_mux_gpio[] = {
478 IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 478 IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
479 }; 479 };
480 480
481 void ss_mux_select(enum typec_cc_polarity pol) 481 void ss_mux_select(enum typec_cc_polarity pol)
482 { 482 {
483 if (pol == TYPEC_POLARITY_CC1) 483 if (pol == TYPEC_POLARITY_CC1)
484 gpio_direction_output(USB_TYPEC_SEL, 1); 484 gpio_direction_output(USB_TYPEC_SEL, 1);
485 else 485 else
486 gpio_direction_output(USB_TYPEC_SEL, 0); 486 gpio_direction_output(USB_TYPEC_SEL, 0);
487 } 487 }
488 488
489 static int setup_typec(void) 489 static int setup_typec(void)
490 { 490 {
491 int ret; 491 int ret;
492 492
493 imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); 493 imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
494 gpio_request(USB_TYPEC_SEL, "typec_sel"); 494 gpio_request(USB_TYPEC_SEL, "typec_sel");
495 495
496 ret = tcpc_init(&port, port_config, &ss_mux_select); 496 ret = tcpc_init(&port, port_config, &ss_mux_select);
497 if (ret) { 497 if (ret) {
498 printf("%s: tcpc init failed, err=%d\n", 498 printf("%s: tcpc init failed, err=%d\n",
499 __func__, ret); 499 __func__, ret);
500 } 500 }
501 501
502 return ret; 502 return ret;
503 } 503 }
504 #endif 504 #endif
505 505
506 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) 506 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
507 int board_usb_init(int index, enum usb_init_type init) 507 int board_usb_init(int index, enum usb_init_type init)
508 { 508 {
509 int ret = 0; 509 int ret = 0;
510 imx8m_usb_power(index, true); 510 imx8m_usb_power(index, true);
511 511
512 if (index == 0 && init == USB_INIT_DEVICE) { 512 if (index == 0 && init == USB_INIT_DEVICE) {
513 #ifdef CONFIG_USB_TCPC 513 #ifdef CONFIG_USB_TCPC
514 ret = tcpc_setup_ufp_mode(&port); 514 ret = tcpc_setup_ufp_mode(&port);
515 #endif 515 #endif
516 dwc3_nxp_usb_phy_init(&dwc3_device_data); 516 dwc3_nxp_usb_phy_init(&dwc3_device_data);
517 return dwc3_uboot_init(&dwc3_device_data); 517 return dwc3_uboot_init(&dwc3_device_data);
518 } else if (index == 0 && init == USB_INIT_HOST) { 518 } else if (index == 0 && init == USB_INIT_HOST) {
519 #ifdef CONFIG_USB_TCPC 519 #ifdef CONFIG_USB_TCPC
520 ret = tcpc_setup_dfp_mode(&port); 520 ret = tcpc_setup_dfp_mode(&port);
521 #endif 521 #endif
522 return ret; 522 return ret;
523 } 523 }
524 524
525 return 0; 525 return 0;
526 } 526 }
527 527
528 int board_usb_cleanup(int index, enum usb_init_type init) 528 int board_usb_cleanup(int index, enum usb_init_type init)
529 { 529 {
530 int ret = 0; 530 int ret = 0;
531 if (index == 0 && init == USB_INIT_DEVICE) { 531 if (index == 0 && init == USB_INIT_DEVICE) {
532 dwc3_uboot_exit(index); 532 dwc3_uboot_exit(index);
533 } else if (index == 0 && init == USB_INIT_HOST) { 533 } else if (index == 0 && init == USB_INIT_HOST) {
534 #ifdef CONFIG_USB_TCPC 534 #ifdef CONFIG_USB_TCPC
535 ret = tcpc_disable_src_vbus(&port); 535 ret = tcpc_disable_src_vbus(&port);
536 #endif 536 #endif
537 } 537 }
538 538
539 imx8m_usb_power(index, false); 539 imx8m_usb_power(index, false);
540 540
541 return ret; 541 return ret;
542 } 542 }
543 #endif 543 #endif
544 544
545 int board_init(void) 545 int board_init(void)
546 { 546 {
547 board_qspi_init(); 547 board_qspi_init();
548 setup_iomux_usb_en_oc(); 548 setup_iomux_usb_en_oc();
549 setup_iomux_misc(); 549 setup_iomux_misc();
550 setup_iomux_gpio(); 550 setup_iomux_gpio();
551 551
552 #ifdef CONFIG_FEC_MXC 552 #ifdef CONFIG_FEC_MXC
553 setup_fec(); 553 setup_fec();
554 #endif 554 #endif
555 555
556 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) 556 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
557 init_usb_clk(); 557 init_usb_clk();
558 #endif 558 #endif
559 559
560 #ifdef CONFIG_USB_TCPC 560 #ifdef CONFIG_USB_TCPC
561 setup_typec(); 561 setup_typec();
562 #endif 562 #endif
563 return 0; 563 return 0;
564 } 564 }
565 565
566 int board_mmc_get_env_dev(int devno) 566 int board_mmc_get_env_dev(int devno)
567 { 567 {
568 return devno; 568 return devno;
569 } 569 }
570 570
571 int board_late_init(void) 571 int board_late_init(void)
572 { 572 {
573 setup_iomux_ecspi1(); 573 setup_iomux_ecspi1();
574 574
575 /* Read Module Information from on module EEPROM and pass 575 /* Read Module Information from on module EEPROM and pass
576 * mac address to kernel 576 * mac address to kernel
577 */ 577 */
578 struct udevice *dev; 578 struct udevice *dev;
579 int ret; 579 int ret;
580 u8 name[8]; 580 u8 name[8];
581 u8 serial[12]; 581 u8 serial[12];
582 u8 revision[4]; 582 u8 revision[4];
583 u8 mac[6]; 583 u8 mac[6];
584 584
585 ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev); 585 ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev);
586 if (ret) { 586 if (ret) {
587 debug("failed to get eeprom\n"); 587 debug("failed to get eeprom\n");
588 return 0; 588 return 0;
589 } 589 }
590 590
591 /* Board ID */ 591 /* Board ID */
592 ret = dm_i2c_read(dev, 0x4, name, 8); 592 ret = dm_i2c_read(dev, 0x4, name, 8);
593 if (ret) { 593 if (ret) {
594 debug("failed to read board ID from EEPROM\n"); 594 debug("failed to read board ID from EEPROM\n");
595 return 0; 595 return 0;
596 } 596 }
597 puts("---------Embedian SMARC-iMX8M------------\n"); 597 puts("---------Embedian SMARC-iMX8M------------\n");
598 printf(" Board ID: %c%c%c%c%c%c%c%c\n", 598 printf(" Board ID: %c%c%c%c%c%c%c%c\n",
599 name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); 599 name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]);
600 600
601 /* Board Hardware Revision */ 601 /* Board Hardware Revision */
602 ret = dm_i2c_read(dev, 0xc, revision, 4); 602 ret = dm_i2c_read(dev, 0xc, revision, 4);
603 if (ret) { 603 if (ret) {
604 debug("failed to read hardware revison from EEPROM\n"); 604 debug("failed to read hardware revison from EEPROM\n");
605 return 0; 605 return 0;
606 } 606 }
607 printf(" Hardware Revision: %c%c%c%c\n", 607 printf(" Hardware Revision: %c%c%c%c\n",
608 revision[0], revision[1], revision[2], revision[3]); 608 revision[0], revision[1], revision[2], revision[3]);
609 609
610 /* Serial number */ 610 /* Serial number */
611 ret = dm_i2c_read(dev, 0x10, serial, 12); 611 ret = dm_i2c_read(dev, 0x10, serial, 12);
612 if (ret) { 612 if (ret) {
613 debug("failed to read srial number from EEPROM\n"); 613 debug("failed to read srial number from EEPROM\n");
614 return 0; 614 return 0;
615 } 615 }
616 printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", 616 printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n",
617 serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); 617 serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]);
618 618
619 /*MAC address */ 619 /*MAC address */
620 ret = dm_i2c_read(dev, 0x3c, mac, 6); 620 ret = dm_i2c_read(dev, 0x3c, mac, 6);
621 if (ret) { 621 if (ret) {
622 debug("failed to read eth0 mac address from EEPROM\n"); 622 debug("failed to read eth0 mac address from EEPROM\n");
623 return 0; 623 return 0;
624 } 624 }
625 625
626 if (is_valid_ethaddr(mac)) 626 if (is_valid_ethaddr(mac))
627 printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", 627 printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
628 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 628 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
629 eth_env_set_enetaddr("ethaddr", mac); 629 eth_env_set_enetaddr("ethaddr", mac);
630 puts("-----------------------------------------\n"); 630 puts("-----------------------------------------\n");
631 631
632 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 632 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
633 env_set("board_name", "SMARC-iMX8M"); 633 env_set("board_name", "SMARC-iMX8M");
634 env_set("board_rev", "iMX8MQ"); 634 env_set("board_rev", "iMX8MQ");
635 #endif 635 #endif
636 636
637 #ifdef CONFIG_ENV_IS_IN_MMC 637 #ifdef CONFIG_ENV_IS_IN_MMC
638 board_late_mmc_env_init(); 638 board_late_mmc_env_init();
639 #endif 639 #endif
640 640
641 /* SMARC BOOT_SEL*/ 641 /* SMARC BOOT_SEL*/
642 gpio_request(IMX_GPIO_NR(1, 4), "BOOT_SEL_1"); 642 gpio_request(IMX_GPIO_NR(1, 4), "BOOT_SEL_1");
643 gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2"); 643 gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2");
644 gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3"); 644 gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3");
645 if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { 645 if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
646 puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n"); 646 puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n");
647 hang(); 647 hang();
648 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { 648 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
649 puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n"); 649 puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n");
650 puts("BOOT_SEL Detected: OFF OFF ON, Boot from USB is not supported...\n"); 650 puts("BOOT_SEL Detected: OFF OFF ON, Boot from USB is not supported...\n");
651 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { 651 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
652 puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n"); 652 puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n");
653 hang(); 653 hang();
654 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { 654 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
655 puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n"); 655 puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n");
656 env_set_ulong("mmcdev", 1); 656 env_set_ulong("mmcdev", 1);
657 if (!env_get("fastboot_dev")) 657 if (!env_get("fastboot_dev"))
658 env_set("fastboot_dev", "mmc1"); 658 env_set("fastboot_dev", "mmc1");
659 if (!env_get("bootcmd")) 659 if (!env_get("bootcmd"))
660 env_set("bootcmd", "boota mmc1"); 660 env_set("bootcmd", "boota mmc1");
661 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { 661 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
662 puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n"); 662 puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n");
663 env_set_ulong("mmcdev", 0); 663 env_set_ulong("mmcdev", 0);
664 if (!env_get("fastboot_dev")) 664 if (!env_get("fastboot_dev"))
665 env_set("fastboot_dev", "mmc0"); 665 env_set("fastboot_dev", "mmc0");
666 if (!env_get("bootcmd")) 666 if (!env_get("bootcmd"))
667 env_set("bootcmd", "boota mmc0"); 667 env_set("bootcmd", "boota mmc0");
668 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { 668 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
669 puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); 669 puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
670 env_set("bootcmd", "run netboot;"); 670 env_set("bootcmd", "run netboot;");
671 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { 671 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
672 puts("Carrier SPI Boot is not supported...\n"); 672 puts("Carrier SPI Boot is not supported...\n");
673 hang(); 673 hang();
674 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { 674 } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
675 puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n"); 675 puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n");
676 hang(); 676 hang();
677 } else { 677 } else {
678 puts("unsupported boot devices\n"); 678 puts("unsupported boot devices\n");
679 hang(); 679 hang();
680 } 680 }
681 681
682 return 0; 682 return 0;
683 } 683 }
684 684
685 #ifdef CONFIG_FSL_FASTBOOT 685 #ifdef CONFIG_FSL_FASTBOOT
686 #ifdef CONFIG_ANDROID_RECOVERY 686 #ifdef CONFIG_ANDROID_RECOVERY
687 #define LID_KEY IMX_GPIO_NR(1, 9) 687 #define LID_KEY IMX_GPIO_NR(1, 9)
688 #define LID_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 688 #define LID_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
689 689
690 static iomux_v3_cfg_t const lid_pads[] = { 690 static iomux_v3_cfg_t const lid_pads[] = {
691 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL), 691 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL),
692 }; 692 };
693 693
694 int is_recovery_key_pressing(void) 694 int is_recovery_key_pressing(void)
695 { 695 {
696 imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads)); 696 imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads));
697 gpio_request(LID_KEY, "LID"); 697 gpio_request(LID_KEY, "LID");
698 gpio_direction_input(LID_KEY); 698 gpio_direction_input(LID_KEY);
699 if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */ 699 if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */
700 printf("Recovery key pressed\n"); 700 printf("Recovery key pressed\n");
701 return 1; 701 return 1;
702 } 702 }
703 return 0; 703 return 0;
704 } 704 }
705 #endif /*CONFIG_ANDROID_RECOVERY*/ 705 #endif /*CONFIG_ANDROID_RECOVERY*/
706 #endif /*CONFIG_FSL_FASTBOOT*/ 706 #endif /*CONFIG_FSL_FASTBOOT*/
707 707
708 #if defined(CONFIG_VIDEO_IMXDCSS) 708 #if defined(CONFIG_VIDEO_IMXDCSS)
709 709
710 struct display_info_t const displays[] = {{ 710 struct display_info_t const displays[] = {{
711 .bus = 0, /* Unused */ 711 .bus = 0, /* Unused */
712 .addr = 0, /* Unused */ 712 .addr = 0, /* Unused */
713 .pixfmt = GDF_32BIT_X888RGB, 713 .pixfmt = GDF_32BIT_X888RGB,
714 .detect = NULL, 714 .detect = NULL,
715 .enable = NULL, 715 .enable = NULL,
716 #ifndef CONFIG_VIDEO_IMXDCSS_1080P 716 #ifndef CONFIG_VIDEO_IMXDCSS_1080P
717 .mode = { 717 .mode = {
718 .name = "HDMI", /* 720P60 */ 718 .name = "HDMI", /* 720P60 */
719 .refresh = 60, 719 .refresh = 60,
720 .xres = 1280, 720 .xres = 1280,
721 .yres = 720, 721 .yres = 720,
722 .pixclock = 13468, /* 74250 kHz */ 722 .pixclock = 13468, /* 74250 kHz */
723 .left_margin = 110, 723 .left_margin = 110,
724 .right_margin = 220, 724 .right_margin = 220,
725 .upper_margin = 5, 725 .upper_margin = 5,
726 .lower_margin = 20, 726 .lower_margin = 20,
727 .hsync_len = 40, 727 .hsync_len = 40,
728 .vsync_len = 5, 728 .vsync_len = 5,
729 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 729 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
730 .vmode = FB_VMODE_NONINTERLACED 730 .vmode = FB_VMODE_NONINTERLACED
731 } 731 }
732 #else 732 #else
733 .mode = { 733 .mode = {
734 .name = "HDMI", /* 1080P60 */ 734 .name = "HDMI", /* 1080P60 */
735 .refresh = 60, 735 .refresh = 60,
736 .xres = 1920, 736 .xres = 1920,
737 .yres = 1080, 737 .yres = 1080,
738 .pixclock = 6734, /* 148500 kHz */ 738 .pixclock = 6734, /* 148500 kHz */
739 .left_margin = 148, 739 .left_margin = 148,
740 .right_margin = 88, 740 .right_margin = 88,
741 .upper_margin = 36, 741 .upper_margin = 36,
742 .lower_margin = 4, 742 .lower_margin = 4,
743 .hsync_len = 44, 743 .hsync_len = 44,
744 .vsync_len = 5, 744 .vsync_len = 5,
745 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 745 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
746 .vmode = FB_VMODE_NONINTERLACED 746 .vmode = FB_VMODE_NONINTERLACED
747 } 747 }
748 #endif 748 #endif
749 } }; 749 } };
750 size_t display_count = ARRAY_SIZE(displays); 750 size_t display_count = ARRAY_SIZE(displays);
751 751
752 #endif /* CONFIG_VIDEO_IMXDCSS */ 752 #endif /* CONFIG_VIDEO_IMXDCSS */
753 753
754 /* return hard code board id for imx8m_ref */ 754 /* return hard code board id for imx8m_ref */
755 #if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) 755 #if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
756 int get_imx8m_baseboard_id(void) 756 int get_imx8m_baseboard_id(void)
757 { 757 {
758 return IMX8M_REF_3G; 758 return IMX8M_REF_3G;
759 } 759 }
760 #endif 760 #endif
761 761
board/embedian/smarcimx8mq/spl.c
Diff comments   View file @ 85f8466
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <spl.h> 8 #include <spl.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <errno.h> 10 #include <errno.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <asm/mach-imx/iomux-v3.h> 12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/arch/ddr.h> 13 #include <asm/arch/ddr.h>
14 #include <asm/arch/imx8mq_pins.h> 14 #include <asm/arch/imx8mq_pins.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <power/pmic.h> 16 #include <power/pmic.h>
17 #include <power/pfuze100_pmic.h> 17 #include <power/pfuze100_pmic.h>
18 #include "../../freescale/common/pfuze.h" 18 #include "../../freescale/common/pfuze.h"
19 #include <asm/arch/clock.h> 19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/gpio.h> 20 #include <asm/mach-imx/gpio.h>
21 #include <asm/mach-imx/mxc_i2c.h> 21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <fsl_esdhc.h> 22 #include <fsl_esdhc.h>
23 #include <mmc.h> 23 #include <mmc.h>
24 #include <asm/arch/imx8m_ddr.h> 24 #include <asm/arch/imx8m_ddr.h>
25 25
26 DECLARE_GLOBAL_DATA_PTR; 26 DECLARE_GLOBAL_DATA_PTR;
27 27
28 /*extern struct dram_timing_info dram_timing_b0;*/ 28 /*extern struct dram_timing_info dram_timing_b0;*/
29 29
30 void spl_dram_init(void) 30 void spl_dram_init(void)
31 { 31 {
32 /* ddr init */ 32 /* ddr init */
33 ddr_init(&dram_timing); 33 ddr_init(&dram_timing);
34 } 34 }
35 35
36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
37 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 37 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
38 struct i2c_pads_info i2c_pad_info1 = { 38 struct i2c_pads_info i2c_pad_info1 = {
39 .scl = { 39 .scl = {
40 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, 40 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
41 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, 41 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
42 .gp = IMX_GPIO_NR(5, 14), 42 .gp = IMX_GPIO_NR(5, 14),
43 }, 43 },
44 .sda = { 44 .sda = {
45 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, 45 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
46 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, 46 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
47 .gp = IMX_GPIO_NR(5, 15), 47 .gp = IMX_GPIO_NR(5, 15),
48 }, 48 },
49 }; 49 };
50 50
51 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) 51 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
52 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) 52 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
53 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) 53 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
54 54
55 int board_mmc_getcd(struct mmc *mmc) 55 int board_mmc_getcd(struct mmc *mmc)
56 { 56 {
57 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 57 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
58 int ret = 0; 58 int ret = 0;
59 59
60 switch (cfg->esdhc_base) { 60 switch (cfg->esdhc_base) {
61 case USDHC1_BASE_ADDR: 61 case USDHC1_BASE_ADDR:
62 ret = 1; 62 ret = 1;
63 break; 63 break;
64 case USDHC2_BASE_ADDR: 64 case USDHC2_BASE_ADDR:
65 ret = !gpio_get_value(USDHC2_CD_GPIO); 65 ret = !gpio_get_value(USDHC2_CD_GPIO);
66 return ret; 66 return ret;
67 } 67 }
68 68
69 return 1; 69 return 1;
70 } 70 }
71 71
72 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ 72 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
73 PAD_CTL_FSEL2) 73 PAD_CTL_FSEL2)
74 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) 74 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
75 75
76 static iomux_v3_cfg_t const usdhc1_pads[] = { 76 static iomux_v3_cfg_t const usdhc1_pads[] = {
77 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 87 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
88 }; 88 };
89 89
90 static iomux_v3_cfg_t const usdhc2_pads[] = { 90 static iomux_v3_cfg_t const usdhc2_pads[] = {
91 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 91 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
92 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 92 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
93 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 93 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
94 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 94 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
95 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ 95 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
96 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 96 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
97 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 97 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
98 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 98 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
99 }; 99 };
100 100
101 /* RESET_OUT */ 101 /* RESET_OUT */
102 static iomux_v3_cfg_t const reset_out_pads[] = { 102 static iomux_v3_cfg_t const reset_out_pads[] = {
103 IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), 103 IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
104 }; 104 };
105 105
106 static void setup_iomux_reset_out(void) 106 static void setup_iomux_reset_out(void)
107 { 107 {
108 imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); 108 imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
109 109
110 /* Set CPU RESET_OUT as Output */ 110 /* Set CPU RESET_OUT as Output */
111 gpio_request(IMX_GPIO_NR(1, 03), "CPU_RESET"); 111 gpio_request(IMX_GPIO_NR(1, 03), "CPU_RESET");
112 gpio_direction_output(IMX_GPIO_NR(1, 03) , 0); 112 gpio_direction_output(IMX_GPIO_NR(1, 03) , 0);
113 } 113 }
114 114
115 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 115 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
116 {USDHC1_BASE_ADDR, 0, 8}, 116 {USDHC1_BASE_ADDR, 0, 8},
117 {USDHC2_BASE_ADDR, 0, 4}, 117 {USDHC2_BASE_ADDR, 0, 4},
118 }; 118 };
119 119
120 int board_mmc_init(bd_t *bis) 120 int board_mmc_init(bd_t *bis)
121 { 121 {
122 int i, ret; 122 int i, ret;
123 /* 123 /*
124 * According to the board_mmc_init() the following map is done: 124 * According to the board_mmc_init() the following map is done:
125 * (U-Boot device node) (Physical Port) 125 * (U-Boot device node) (Physical Port)
126 * mmc0 USDHC1 126 * mmc0 USDHC1
127 * mmc1 USDHC2 127 * mmc1 USDHC2
128 */ 128 */
129 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 129 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
130 switch (i) { 130 switch (i) {
131 case 0: 131 case 0:
132 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); 132 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
133 imx_iomux_v3_setup_multiple_pads( 133 imx_iomux_v3_setup_multiple_pads(
134 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 134 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
135 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); 135 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
136 gpio_direction_output(USDHC1_PWR_GPIO, 0); 136 gpio_direction_output(USDHC1_PWR_GPIO, 0);
137 udelay(500); 137 udelay(500);
138 gpio_direction_output(USDHC1_PWR_GPIO, 1); 138 gpio_direction_output(USDHC1_PWR_GPIO, 1);
139 break; 139 break;
140 case 1: 140 case 1:
141 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); 141 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
142 imx_iomux_v3_setup_multiple_pads( 142 imx_iomux_v3_setup_multiple_pads(
143 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 143 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
144 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); 144 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
145 gpio_direction_output(USDHC2_PWR_GPIO, 0); 145 gpio_direction_output(USDHC2_PWR_GPIO, 0);
146 udelay(500); 146 udelay(500);
147 gpio_direction_output(USDHC2_PWR_GPIO, 1); 147 gpio_direction_output(USDHC2_PWR_GPIO, 1);
148 break; 148 break;
149 default: 149 default:
150 printf("Warning: you configured more USDHC controllers" 150 printf("Warning: you configured more USDHC controllers"
151 "(%d) than supported by the board\n", i + 1); 151 "(%d) than supported by the board\n", i + 1);
152 return -EINVAL; 152 return -EINVAL;
153 } 153 }
154 154
155 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 155 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
156 if (ret) 156 if (ret)
157 return ret; 157 return ret;
158 } 158 }
159 159
160 return 0; 160 return 0;
161 } 161 }
162 162
163 #ifdef CONFIG_POWER 163 #ifdef CONFIG_POWER
164 #define I2C_PMIC 0 164 #define I2C_PMIC 0
165 int power_init_board(void) 165 int power_init_board(void)
166 { 166 {
167 struct pmic *p; 167 struct pmic *p;
168 int ret; 168 int ret;
169 unsigned int reg; 169 unsigned int reg;
170 170
171 ret = power_pfuze100_init(I2C_PMIC); 171 ret = power_pfuze100_init(I2C_PMIC);
172 if (ret) 172 if (ret)
173 return -ENODEV; 173 return -ENODEV;
174 174
175 p = pmic_get("PFUZE100"); 175 p = pmic_get("PFUZE100");
176 ret = pmic_probe(p); 176 ret = pmic_probe(p);
177 if (ret) 177 if (ret)
178 return -ENODEV; 178 return -ENODEV;
179 179
180 pmic_reg_read(p, PFUZE100_DEVICEID, &reg); 180 pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
181 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 181 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
182 182
183 pmic_reg_read(p, PFUZE100_SW3AVOL, &reg); 183 pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
184 if ((reg & 0x3f) != 0x18) { 184 if ((reg & 0x3f) != 0x18) {
185 reg &= ~0x3f; 185 reg &= ~0x3f;
186 reg |= 0x18; 186 reg |= 0x18;
187 pmic_reg_write(p, PFUZE100_SW3AVOL, reg); 187 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
188 } 188 }
189 189
190 ret = pfuze_mode_init(p, APS_PFM); 190 ret = pfuze_mode_init(p, APS_PFM);
191 if (ret < 0) 191 if (ret < 0)
192 return ret; 192 return ret;
193 193
194 /* set SW3A standby mode to off */ 194 /* set SW3A standby mode to off */
195 pmic_reg_read(p, PFUZE100_SW3AMODE, &reg); 195 pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
196 reg &= ~0xf; 196 reg &= ~0xf;
197 reg |= APS_OFF; 197 reg |= APS_OFF;
198 pmic_reg_write(p, PFUZE100_SW3AMODE, reg); 198 pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
199 199
200 return 0; 200 return 0;
201 } 201 }
202 #endif 202 #endif
203 203
204 void spl_board_init(void) 204 void spl_board_init(void)
205 { 205 {
206 #ifndef CONFIG_SPL_USB_SDP_SUPPORT 206 #ifndef CONFIG_SPL_USB_SDP_SUPPORT
207 /* Serial download mode */ 207 /* Serial download mode */
208 if (is_usb_boot()) { 208 if (is_usb_boot()) {
209 puts("Back to ROM, SDP\n"); 209 puts("Back to ROM, SDP\n");
210 restore_boot_params(); 210 restore_boot_params();
211 } 211 }
212 #endif 212 #endif
213 213
214 init_usb_clk(); 214 init_usb_clk();
215 215
216 puts("Normal Boot\n"); 216 puts("Normal Boot\n");
217 setup_iomux_reset_out(); 217 setup_iomux_reset_out();
218 } 218 }
219 219
220 #ifdef CONFIG_SPL_LOAD_FIT 220 #ifdef CONFIG_SPL_LOAD_FIT
221 int board_fit_config_name_match(const char *name) 221 int board_fit_config_name_match(const char *name)
222 { 222 {
223 /* Just empty function now - can't decide what to choose */ 223 /* Just empty function now - can't decide what to choose */
224 debug("%s: %s\n", __func__, name); 224 debug("%s: %s\n", __func__, name);
225 225
226 return 0; 226 return 0;
227 } 227 }
228 #endif 228 #endif
229 229
230 void board_init_f(ulong dummy) 230 void board_init_f(ulong dummy)
231 { 231 {
232 int ret; 232 int ret;
233 233
234 /* Clear global data */ 234 /* Clear global data */
235 memset((void *)gd, 0, sizeof(gd_t)); 235 memset((void *)gd, 0, sizeof(gd_t));
236 236
237 arch_cpu_init(); 237 arch_cpu_init();
238 238
239 init_uart_clk(0); /* Init UART0 clock */ 239 #ifdef CONFIG_CONSOLE_SER3
240 init_uart_clk(0); /* Init UART0 clock */
241 #endif
242
243 #ifdef CONFIG_CONSOLE_SER2
244 init_uart_clk(1); /* Init UART1 clock */
245 #endif
246
247 #ifdef CONFIG_CONSOLE_SER1
248 init_uart_clk(2); /* Init UART2 clock */
249 #endif
250
251 #ifdef CONFIG_CONSOLE_SER0
252 init_uart_clk(3); /* Init UART3 clock */
253 #endif
240 254
241 board_early_init_f(); 255 board_early_init_f();
242 256
243 timer_init(); 257 timer_init();
244 258
245 preloader_console_init(); 259 preloader_console_init();
246 260
247 /* Clear the BSS. */ 261 /* Clear the BSS. */
248 memset(__bss_start, 0, __bss_end - __bss_start); 262 memset(__bss_start, 0, __bss_end - __bss_start);
249 263
250 ret = spl_init(); 264 ret = spl_init();
251 if (ret) { 265 if (ret) {
252 debug("spl_init() failed: %d\n", ret); 266 debug("spl_init() failed: %d\n", ret);
253 hang(); 267 hang();
254 } 268 }
255 269
256 enable_tzc380(); 270 enable_tzc380();
257 271
258 /* Adjust pmic voltage to 1.0V for 800M */ 272 /* Adjust pmic voltage to 1.0V for 800M */
259 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x08, &i2c_pad_info1); 273 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x08, &i2c_pad_info1);
260 274
261 power_init_board(); 275 power_init_board();
262 276
263 /* DDR initialization */ 277 /* DDR initialization */
264 spl_dram_init(); 278 spl_dram_init();
265 279
266 board_init_r(NULL, 0); 280 board_init_r(NULL, 0);
267 } 281 }
268 282