From a174782d0eb932e5f00036c6c8052458768cc418 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 25 Jun 2021 16:43:28 +0300 Subject: [PATCH] board: fsl: lx2160aqds: add support for SERDES #1 protocol 14 Add support for the SERDES #1 protocol 14 which enables a 100G MAC (dpmac.1). For this to work, a new DTS file which describes how the M8 mezzanine card is connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-lx2160a-qds-14-x-x.dts | 17 +++++++++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-14.dtsi | 30 ++++++++++++++++++++++++++++++ board/freescale/lx2160a/eth_lx2160aqds.c | 1 + configs/lx2160aqds_tfa_defconfig | 2 +- 5 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-14-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-14.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 58047e2..b8017fd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -465,6 +465,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-lx2160a-qds-20-x-x.dtb \ fsl-lx2160a-qds-20-11-x.dtb \ fsl-lx2160a-qds-13-x-x.dtb \ + fsl-lx2160a-qds-14-x-x.dtb \ fsl-lx2162a-qds.dtb\ fsl-lx2162a-qds-17-x.dtb\ fsl-lx2162a-qds-18-x.dtb\ diff --git a/arch/arm/dts/fsl-lx2160a-qds-14-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-14-x-x.dts new file mode 100644 index 0000000..1aebd06 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-14-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 14.x.x + * + * Copyright 2021-2022 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-14.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 14.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-14.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-14.dtsi new file mode 100644 index 0000000..ae5183e --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-14.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 14 + * + * Some assumptions are made: + * * mezzanine card M8 (100G) is connected to IO SLOT 1 - DPMAC 1 + * + * Copyright 2021-2022 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-handle = <&inphi1_phy0 &inphi1_phy1>; + phy-connection-type = "caui4"; +}; + +&emdio1_slot1 { + inphi1_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi1_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 8fb3aea..cf1f59a 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -879,6 +879,7 @@ static struct serdes_configuration { {1, 3, true}, {1, 7, true}, {1, 13, true}, + {1, 14, true}, {1, 19, true}, {1, 20, true}, diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 33957df..e7277bd 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x fsl-lx2160a-qds-13-x-x" +CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x fsl-lx2160a-qds-13-x-x fsl-lx2160a-qds-14-x-x" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -- 1.9.1