Commit a42789ade30eaf3595fafb61ade326dc24e6825a
Exists in
smarc_8mq_lf_v2020.04
and in
4 other branches
Merge remote-tracking branch 'origin/imx_v2020.04' into lf_v2020.04
* origin/imx_v2020.04: LF-3161-2 mx6ul: bee: Remove XN bit for bee enabled region LF-3161-1 arm: imx: Fix speculative instruction prefetch issue
Showing 2 changed files Side-by-side Diff
arch/arm/mach-imx/cache.c
... | ... | @@ -10,6 +10,8 @@ |
10 | 10 | #include <asm/io.h> |
11 | 11 | #include <asm/mach-imx/sys_proto.h> |
12 | 12 | |
13 | +DECLARE_GLOBAL_DATA_PTR; | |
14 | + | |
13 | 15 | static void enable_ca7_smp(void) |
14 | 16 | { |
15 | 17 | u32 val; |
16 | 18 | |
17 | 19 | |
... | ... | @@ -39,12 +41,16 @@ |
39 | 41 | } |
40 | 42 | |
41 | 43 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
44 | + | |
45 | +#define ARMV7_DOMAIN_CLIENT 1 | |
46 | +#define ARMV7_DOMAIN_MASK (0x3 << 0) | |
47 | + | |
42 | 48 | void enable_caches(void) |
43 | 49 | { |
44 | 50 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
45 | - enum dcache_option option = DCACHE_WRITETHROUGH; | |
51 | + enum dcache_option option = DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK; | |
46 | 52 | #else |
47 | - enum dcache_option option = DCACHE_WRITEBACK; | |
53 | + enum dcache_option option = DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK; | |
48 | 54 | #endif |
49 | 55 | /* Avoid random hang when download by usb */ |
50 | 56 | invalidate_dcache_all(); |
... | ... | @@ -63,6 +69,40 @@ |
63 | 69 | IRAM_SIZE, |
64 | 70 | option); |
65 | 71 | } |
72 | + | |
73 | +void dram_bank_mmu_setup(int bank) | |
74 | +{ | |
75 | + bd_t *bd = gd->bd; | |
76 | + int i; | |
77 | + | |
78 | + debug("%s: bank: %d\n", __func__, bank); | |
79 | + for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; | |
80 | + i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + | |
81 | + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); | |
82 | + i++) { | |
83 | +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) | |
84 | + set_section_dcache(i, DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK); | |
85 | +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) | |
86 | + set_section_dcache(i, DCACHE_WRITEALLOC & ~TTB_SECT_XN_MASK); | |
87 | +#else | |
88 | + set_section_dcache(i, DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK); | |
89 | +#endif | |
90 | + } | |
91 | +} | |
92 | + | |
93 | +void arm_init_domains(void) | |
94 | +{ | |
95 | + u32 reg; | |
96 | + | |
97 | + reg = get_dacr(); | |
98 | + /* | |
99 | + * Set domain to client to do access and XN check | |
100 | + */ | |
101 | + reg &= ~ARMV7_DOMAIN_MASK; | |
102 | + reg |= ARMV7_DOMAIN_CLIENT; | |
103 | + set_dacr(reg); | |
104 | +} | |
105 | + | |
66 | 106 | #else |
67 | 107 | void enable_caches(void) |
68 | 108 | { |
arch/arm/mach-imx/mx6/bee.c
... | ... | @@ -275,9 +275,9 @@ |
275 | 275 | struct bee_parameters *p = ¶ |
276 | 276 | |
277 | 277 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
278 | - enum dcache_option option = DCACHE_WRITETHROUGH; | |
278 | + enum dcache_option option = DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK; | |
279 | 279 | #else |
280 | - enum dcache_option option = DCACHE_WRITEBACK; | |
280 | + enum dcache_option option = DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK; | |
281 | 281 | #endif |
282 | 282 | |
283 | 283 | if (argc > 5) |