Commit aae7422b45012da8f9594c72ab914b87d3a3708a

Authored by Vipul Kumar
Committed by Michal Simek
1 parent bd5a8e5850

arm64: zynqmp: Moved ethernet PHY configs of ZynqMP boards to defconfig

This patch moved ethernet PHY configs of ZynqMP boards
to respective defconfig.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 9 changed files with 40 additions and 5 deletions Side-by-side Diff

configs/xilinx_zynqmp_ep_defconfig
... ... @@ -69,6 +69,11 @@
69 69 CONFIG_SPI_FLASH_STMICRO=y
70 70 CONFIG_SPI_FLASH_WINBOND=y
71 71 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  72 +CONFIG_PHY_MARVELL=y
  73 +CONFIG_PHY_NATSEMI=y
  74 +CONFIG_PHY_REALTEK=y
  75 +CONFIG_PHY_TI=y
  76 +CONFIG_PHY_VITESSE=y
72 77 CONFIG_DM_ETH=y
73 78 CONFIG_PHY_GIGE=y
74 79 CONFIG_ZYNQ_GEM=y
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
... ... @@ -62,6 +62,11 @@
62 62 CONFIG_SPI_FLASH_STMICRO=y
63 63 CONFIG_SPI_FLASH_WINBOND=y
64 64 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  65 +CONFIG_PHY_MARVELL=y
  66 +CONFIG_PHY_NATSEMI=y
  67 +CONFIG_PHY_REALTEK=y
  68 +CONFIG_PHY_TI=y
  69 +CONFIG_PHY_VITESSE=y
65 70 CONFIG_DM_ETH=y
66 71 CONFIG_PHY_GIGE=y
67 72 CONFIG_ZYNQ_GEM=y
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
... ... @@ -58,6 +58,11 @@
58 58 CONFIG_SPI_FLASH=y
59 59 CONFIG_SPI_FLASH_BAR=y
60 60 CONFIG_SPI_FLASH_SST=y
  61 +CONFIG_PHY_MARVELL=y
  62 +CONFIG_PHY_NATSEMI=y
  63 +CONFIG_PHY_REALTEK=y
  64 +CONFIG_PHY_TI=y
  65 +CONFIG_PHY_VITESSE=y
61 66 CONFIG_DM_ETH=y
62 67 CONFIG_PHY_GIGE=y
63 68 CONFIG_ZYNQ_GEM=y
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
... ... @@ -50,6 +50,11 @@
50 50 CONFIG_SPI_FLASH_STMICRO=y
51 51 CONFIG_SPI_FLASH_WINBOND=y
52 52 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  53 +CONFIG_PHY_MARVELL=y
  54 +CONFIG_PHY_NATSEMI=y
  55 +CONFIG_PHY_REALTEK=y
  56 +CONFIG_PHY_TI=y
  57 +CONFIG_PHY_VITESSE=y
53 58 CONFIG_DM_ETH=y
54 59 CONFIG_PHY_GIGE=y
55 60 CONFIG_ZYNQ_GEM=y
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
... ... @@ -43,6 +43,11 @@
43 43 CONFIG_DM_MMC=y
44 44 CONFIG_MMC_SDHCI=y
45 45 CONFIG_MMC_SDHCI_ZYNQ=y
  46 +CONFIG_PHY_MARVELL=y
  47 +CONFIG_PHY_NATSEMI=y
  48 +CONFIG_PHY_REALTEK=y
  49 +CONFIG_PHY_TI=y
  50 +CONFIG_PHY_VITESSE=y
46 51 CONFIG_DM_ETH=y
47 52 CONFIG_DEBUG_UART_ZYNQ=y
48 53 CONFIG_DEBUG_UART_BASE=0xff000000
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
... ... @@ -64,6 +64,11 @@
64 64 CONFIG_SPI_FLASH_STMICRO=y
65 65 CONFIG_SPI_FLASH_WINBOND=y
66 66 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  67 +CONFIG_PHY_MARVELL=y
  68 +CONFIG_PHY_NATSEMI=y
  69 +CONFIG_PHY_REALTEK=y
  70 +CONFIG_PHY_TI=y
  71 +CONFIG_PHY_VITESSE=y
67 72 CONFIG_DM_ETH=y
68 73 CONFIG_PHY_GIGE=y
69 74 CONFIG_ZYNQ_GEM=y
configs/xilinx_zynqmp_zcu102_revA_defconfig
... ... @@ -64,6 +64,11 @@
64 64 CONFIG_SPI_FLASH_STMICRO=y
65 65 CONFIG_SPI_FLASH_WINBOND=y
66 66 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  67 +CONFIG_PHY_MARVELL=y
  68 +CONFIG_PHY_NATSEMI=y
  69 +CONFIG_PHY_REALTEK=y
  70 +CONFIG_PHY_TI=y
  71 +CONFIG_PHY_VITESSE=y
67 72 CONFIG_DM_ETH=y
68 73 CONFIG_PHY_GIGE=y
69 74 CONFIG_ZYNQ_GEM=y
configs/xilinx_zynqmp_zcu102_revB_defconfig
... ... @@ -64,6 +64,11 @@
64 64 CONFIG_SPI_FLASH_STMICRO=y
65 65 CONFIG_SPI_FLASH_WINBOND=y
66 66 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  67 +CONFIG_PHY_MARVELL=y
  68 +CONFIG_PHY_NATSEMI=y
  69 +CONFIG_PHY_REALTEK=y
  70 +CONFIG_PHY_TI=y
  71 +CONFIG_PHY_VITESSE=y
67 72 CONFIG_DM_ETH=y
68 73 CONFIG_PHY_GIGE=y
69 74 CONFIG_ZYNQ_GEM=y
include/configs/xilinx_zynqmp.h
... ... @@ -136,11 +136,6 @@
136 136 #if defined(CONFIG_ZYNQ_GEM)
137 137 # define CONFIG_MII
138 138 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
139   -# define CONFIG_PHY_MARVELL
140   -# define CONFIG_PHY_NATSEMI
141   -# define CONFIG_PHY_TI
142   -# define CONFIG_PHY_VITESSE
143   -# define CONFIG_PHY_REALTEK
144 139 # define PHY_ANEG_TIMEOUT 20000
145 140 #endif
146 141