From ab6b18bcf3cade15586839274bfde2030726ad37 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 20 Dec 2018 23:11:51 -0800 Subject: [PATCH] MLK-20635 imx8: clock: Fix GPR settings for FEC FEC has some clock settings inside DSC GPR. Kernel configures them, but u-boot not. So when doing partition reset, the GPR keeps the value from kernel, and cause clock issue to u-boot FEC: kernel enables the divclk in GPR and set the clock slice to 250Mhz, u-boot configures the clock slice to 125Mhz, the divclk causes the RGMII TX CLK to 62.5Mhz. Fix the issue by aligning the GPR and clock slice settings with kernel Signed-off-by: Ye Li Reviewed-by: Fugang Duan --- arch/arm/mach-imx/imx8/clock.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 78b53f2..98e0651 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -403,8 +403,10 @@ void init_clk_fec(int index) return; } - /* Set SC_R_ENET_0 clock root to 125 MHz */ - rate = 125000000; + /* Set SC_R_ENET_0 clock root to 250 MHz, the clkdiv is set to div 2 + * so finally RGMII TX clk is 125Mhz + */ + rate = 250000000; /* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */ err = sc_pm_set_clock_rate(ipc, enet[index], 2, &rate); @@ -422,6 +424,14 @@ void init_clk_fec(int index) return; } + /* Configure GPR regisers */ + sc_misc_set_control(ipc, enet[index], SC_C_TXCLK, 0); + sc_misc_set_control(ipc, enet[index], SC_C_CLKDIV, 1); /* Enable divclk */ + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 1); + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_125, 1); + sc_misc_set_control(ipc, enet[index], SC_C_SEL_125, 0); + sc_misc_set_control(ipc, enet[index], SC_C_IPG_STOP, 0); + LPCG_AllClockOn(ENET_0_LPCG + index * 0x10000); } -- 1.9.1