Commit afba354e268d048f9ccea126db89da5af75b45f6

Authored by Eric Lee
1 parent 0f27307122

remove qspi_header

Showing 1 changed file with 0 additions and 128 deletions Side-by-side Diff

1   -0 /*dqs_loopback=0 or 1*/
2   -0 /*hold_delay=0 to 3*/
3   -0 /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
4   -0 /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/
5   -0 /*device_quad_mode_en=1 to enable sending command to SPI device*/
6   -0 /*device_cmd=command to device for enableing Quad I/O mode*/
7   -0 /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
8   -2000000 /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
9   -3 /*cs_hold_time=0 to 0xF*/
10   -3 /*cs_setup_time=0 to 0xF*/
11   -8000000 /*sflash_A1_size=size in byte(hex)*/
12   -0 /*sflash_A2_size=size in byte(hex)*/
13   -8000000 /*sflash_B1_size=size in byte(hex)*/
14   -0 /*sflash_B2_size=size in byte(hex)*/
15   -0 /*sclk_freq=0 to 6*/
16   -0 /*busy_bit_offset=bit position of device BUSY in device status register*/
17   -1 /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
18   -0 /*sflash_port=0 or 1 (Port B used)*/
19   -0 /*ddr_mode_enable=0 or 1*/
20   -0 /*dqs_enable=0 or 1*/
21   -0 /*parallel_mode_enable=0 or 1*/
22   -0 /*portA_cs1=0 or 1*/
23   -0 /*portB_cs1=0 or 1*/
24   -0 /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
25   -0 /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
26   -0 /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
27   -08180403 /*lut[0] command sequence*/
28   -24001c00 /*lut[1] command sequence*/
29   -0 /*lut[2] command sequence*/
30   -0 /*lut[3] command sequence*/
31   -0 /*lut[4] command sequence*/
32   -0 /*lut[5] command sequence*/
33   -0 /*lut[6] command sequence*/
34   -0 /*lut[7] command sequence*/
35   -0 /*lut[8] command sequence*/
36   -0 /*lut[9] command sequence*/
37   -0 /*lut[10] command sequence*/
38   -0 /*lut[11] command sequence*/
39   -0 /*lut[12] command sequence*/
40   -0 /*lut[13] command sequence*/
41   -0 /*lut[14] command sequence*/
42   -0 /*lut[15] command sequence*/
43   -0 /*lut[16] command sequence*/
44   -0 /*lut[17] command sequence*/
45   -0 /*lut[18] command sequence*/
46   -0 /*lut[19] command sequence*/
47   -0 /*lut[20] command sequence*/
48   -0 /*lut[21] command sequence*/
49   -0 /*lut[22] command sequence*/
50   -0 /*lut[23] command sequence*/
51   -0 /*lut[24] command sequence*/
52   -0 /*lut[25] command sequence*/
53   -0 /*lut[26] command sequence*/
54   -0 /*lut[27] command sequence*/
55   -0 /*lut[28] command sequence*/
56   -0 /*lut[29] command sequence*/
57   -0 /*lut[30] command sequence*/
58   -0 /*lut[31] command sequence*/
59   -0 /*lut[32] command sequence*/
60   -0 /*lut[33] command sequence*/
61   -0 /*lut[34] command sequence*/
62   -0 /*lut[35] command sequence*/
63   -0 /*lut[36] command sequence*/
64   -0 /*lut[37] command sequence*/
65   -0 /*lut[38] command sequence*/
66   -0 /*lut[39] command sequence*/
67   -0 /*lut[40] command sequence*/
68   -0 /*lut[41] command sequence*/
69   -0 /*lut[42] command sequence*/
70   -0 /*lut[43] command sequence*/
71   -0 /*lut[44] command sequence*/
72   -0 /*lut[45] command sequence*/
73   -0 /*lut[46] command sequence*/
74   -0 /*lut[47] command sequence*/
75   -0 /*lut[48] command sequence*/
76   -0 /*lut[49] command sequence*/
77   -0 /*lut[50] command sequence*/
78   -0 /*lut[51] command sequence*/
79   -0 /*lut[52] command sequence*/
80   -0 /*lut[53] command sequence*/
81   -0 /*lut[54] command sequence*/
82   -0 /*lut[55] command sequence*/
83   -0 /*lut[56] command sequence*/
84   -0 /*lut[57] command sequence*/
85   -0 /*lut[58] command sequence*/
86   -0 /*lut[59] command sequence*/
87   -0 /*lut[60] command sequence*/
88   -0 /*lut[61] command sequence*/
89   -0 /*lut[62] command sequence*/
90   -0 /*lut[63] command sequence*/
91   -1000001 /*read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/
92   -0 /*enable_dqs_phase=0 or 1*/
93   -0 /*config_cmds_en, enable config command*/
94   -0 /*config_cmds[0]*/
95   -0 /*config_cmds[1]*/
96   -0 /*config_cmds[2]*/
97   -0 /*config_cmds[3]*/
98   -0 /*config_cmds_args[0]*/
99   -0 /*config_cmds_args[1]*/
100   -0 /*config_cmds_args[2]*/
101   -0 /*config_cmds_args[3]*/
102   -0 /*io_pad_override_setting QSPI pins override setting*/
103   -0 /*reserve[0], 25 byte reserved area*/
104   -0 /*reserve[1], 25 byte reserved area*/
105   -0 /*reserve[2], 25 byte reserved area*/
106   -0 /*reserve[3], 25 byte reserved area*/
107   -0 /*reserve[4], 25 byte reserved area*/
108   -0 /*reserve[5], 25 byte reserved area*/
109   -0 /*reserve[6], 25 byte reserved area*/
110   -0 /*reserve[7], 25 byte reserved area*/
111   -0 /*reserve[8], 25 byte reserved area*/
112   -0 /*reserve[9], 25 byte reserved area*/
113   -0 /*reserve[10], 25 byte reserved area*/
114   -0 /*reserve[11], 25 byte reserved area*/
115   -0 /*reserve[12], 25 byte reserved area*/
116   -0 /*reserve[13], 25 byte reserved area*/
117   -0 /*reserve[14], 25 byte reserved area*/
118   -0 /*reserve[15], 25 byte reserved area*/
119   -0 /*reserve[16], 25 byte reserved area*/
120   -0 /*reserve[17], 25 byte reserved area*/
121   -0 /*reserve[18], 25 byte reserved area*/
122   -0 /*reserve[19], 25 byte reserved area*/
123   -0 /*reserve[20], 25 byte reserved area*/
124   -0 /*reserve[21], 25 byte reserved area*/
125   -0 /*reserve[22], 25 byte reserved area*/
126   -0 /*reserve[23], 25 byte reserved area*/
127   -0 /*reserve[24], 25 byte reserved area*/
128   -c0ffee01 /*tag, QSPI configuration tag, should be 0xc0ffee01*/