From b02221d7cbfe2911ab347813be5155921f08f7f0 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 22 May 2018 01:48:19 -0700 Subject: [PATCH] MLK-18243-18: arm: imx: add i.MX8MM EVK board support Add i.MX8MM EVK board support LPDDR4 code is still keep in old coding style to ease updating if there is no code released. dts is synced from kernel with sd2 regulator start up delay and off on delay added. Signed-off-by: Peng Fan (cherry picked from commit 01b3f229b188e28b0887c0b32f66e939a50d3a69) Signed-off-by: Ye Li --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-imx8mm-evk.dts | 451 ++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 6 + board/freescale/imx8mm_evk/Kconfig | 14 + board/freescale/imx8mm_evk/Makefile | 12 + board/freescale/imx8mm_evk/ddr/Makefile | 13 + board/freescale/imx8mm_evk/ddr/ddr.h | 60 ++ board/freescale/imx8mm_evk/ddr/helper.c | 104 +++ .../imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c | 279 ++++++ board/freescale/imx8mm_evk/ddr/lpddr4_define.h | 161 ++++ .../freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c | 154 ++++ .../ddr/lpddr4_phyinit_train_3000mts_fw09.c | 943 +++++++++++++++++++++ .../ddr/lpddr4_pmu_training_3000mts_fw09.c | 184 ++++ board/freescale/imx8mm_evk/imx8mm_evk.c | 263 ++++++ board/freescale/imx8mm_evk/spl.c | 163 ++++ configs/imx8mm_evk_defconfig | 47 + include/configs/imx8mm_evk.h | 281 ++++++ 17 files changed, 3137 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-imx8mm-evk.dts create mode 100644 board/freescale/imx8mm_evk/Kconfig create mode 100644 board/freescale/imx8mm_evk/Makefile create mode 100755 board/freescale/imx8mm_evk/ddr/Makefile create mode 100644 board/freescale/imx8mm_evk/ddr/ddr.h create mode 100644 board/freescale/imx8mm_evk/ddr/helper.c create mode 100644 board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c create mode 100644 board/freescale/imx8mm_evk/ddr/lpddr4_define.h create mode 100644 board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c create mode 100644 board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c create mode 100644 board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644 board/freescale/imx8mm_evk/spl.c create mode 100644 configs/imx8mm_evk_defconfig create mode 100644 include/configs/imx8mm_evk.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd0b364..cb39392a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -430,7 +430,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \ fsl-imx8mq-ddr3l-arm2.dtb \ - fsl-imx8mq-ddr4-arm2.dtb + fsl-imx8mq-ddr4-arm2.dtb \ + fsl-imx8mm-evk.dtb dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-ddr4-arm2.dtb \ fsl-imx8qm-lpddr4-arm2.dtb \ diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts b/arch/arm/dts/fsl-imx8mm-evk.dts new file mode 100644 index 0000000..d5f597b --- /dev/null +++ b/arch/arm/dts/fsl-imx8mm-evk.dts @@ -0,0 +1,451 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM EVK board"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-patch = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-evk { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8168b5f..a3256e7 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -32,6 +32,11 @@ config TARGET_IMX8MQ_DDR4_ARM2 select IMX8MQ select SUPPORT_SPL +config TARGET_IMX8MM_EVK + bool "imx8mm evk" + select IMX8MM + select SUPPORT_SPL + endchoice config SYS_SOC @@ -39,5 +44,6 @@ config SYS_SOC source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mq_arm2/Kconfig" +source "board/freescale/imx8mm_evk/Kconfig" endif diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig new file mode 100644 index 0000000..ec3c81e --- /dev/null +++ b/board/freescale/imx8mm_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8MM_EVK + +config SYS_BOARD + default "imx8mm_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mm_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile new file mode 100644 index 0000000..db8ccaa --- /dev/null +++ b/board/freescale/imx8mm_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/ +endif diff --git a/board/freescale/imx8mm_evk/ddr/Makefile b/board/freescale/imx8mm_evk/ddr/Makefile new file mode 100755 index 0000000..2b9ee4e --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += helper.o +obj-y += lpddr4_cfg_umctl2_m845.o +obj-y += lpddr4_phyinit_train_3000mts_fw09.o +obj-y += lpddr4_pmu_training_3000mts_fw09.o +obj-y += lpddr4_phyinit_task.o +endif diff --git a/board/freescale/imx8mm_evk/ddr/ddr.h b/board/freescale/imx8mm_evk/ddr/ddr.h new file mode 100644 index 0000000..2de9fad --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/ddr.h @@ -0,0 +1,60 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * Common file for ddr code + */ + +#ifndef __M845S_DDR_H_ +#define __M845S_DDR_H_ + +#ifdef DDR_DEBUG +#define ddr_dbg(fmt, ...) printf("DDR: debug:" fmt "\n", ##__VA_ARGS__) +#else +#define ddr_dbg(fmt, ...) +#endif + +/******************************************************************* + Desc: user data type + + *******************************************************************/ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; +/******************************************************************* + Desc: prototype + + *******************************************************************/ +void ddr_init(void); +void lpddr4_3000mts_cfg_umctl2(void); +void ddr_load_train_code(enum fw_type type); +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate); +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void); +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void); +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void); +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void); +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void); +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned long run_2D); +int dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void); +void lpddr4_750M_cfg_phy(void); + +/******************************************************************* + Desc: definition + + *******************************************************************/ +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline uint32_t reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} +#endif diff --git a/board/freescale/imx8mm_evk/ddr/helper.c b/board/freescale/imx8mm_evk/ddr/helper.c new file mode 100644 index 0000000..2b22493 --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/helper.c @@ -0,0 +1,104 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768//23400 //byte +#define DMEM_LEN 16384//1720 //byte +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_code(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN; ){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + printf("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if(error){ + printf("check ddr4_pmu_train_imem code fail=%d\n",error); + }else{ + printf("check ddr4_pmu_train_imem code pass\n"); + } + + printf("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if(error){ + printf("check ddr4_pmu_train_dmem code fail=%d",error); + }else{ + printf("check ddr4_pmu_train_dmem code pass\n"); + } +} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c b/board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c new file mode 100644 index 0000000..eabe213 --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c @@ -0,0 +1,279 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "lpddr4_define.h" + +struct ddr_ctl_param +{ + u32 reg; /*reg address */ + u32 val; /*config param */ +}; + +static struct ddr_ctl_param ctl_init_cfg[] = +{ + { .reg =DDRC_DBG1(0), .val = 0x00000001}, + { .reg =DDRC_PWRCTL(0), .val = 0x00000001}, +#ifdef DDR_ONE_RANK + { .reg =DDRC_MSTR(0), .val = 0xa1080020}, +#else + { .reg =DDRC_MSTR(0), .val = 0xa3080020}, +#endif +#ifdef DDR_800M_CFG + { .reg =DDRC_RFSHTMG(0), .val = 0x006100E0}, +#else + { .reg =DDRC_RFSHTMG(0), .val = 0x005b00d2}, +#endif +#ifdef PHY_TRAIN + { .reg =DDRC_INIT0(0), .val = 0xC003061B}, +#else +#ifdef DDR_FAST_SIM + { .reg =DDRC_INIT0(0), .val = 0x00030003}, +#else + { .reg =DDRC_INIT0(0), .val = 0x0003061B}, +#endif +#endif +#ifdef DDR_FAST_SIM + { .reg =DDRC_INIT1(0), .val = 0x00060000}, +#else + { .reg =DDRC_INIT1(0), .val = 0x009D0000}, +#endif + { .reg =DDRC_INIT3(0), .val = 0x00D4002D}, +#ifdef WR_POST_EXT_3200 + { .reg =DDRC_INIT4(0), .val = 0x00330008}, +#else + + { .reg =DDRC_INIT4(0), .val = 0x00310000}, +#endif + { .reg =DDRC_INIT6(0), .val = 0x0066004a}, + { .reg =DDRC_INIT7(0), .val = 0x0006004a}, + + { .reg =DDRC_DRAMTMG0(0), .val = 0x1A201B22}, + { .reg =DDRC_DRAMTMG1(0), .val = 0x00060633}, + { .reg =DDRC_DRAMTMG3(0), .val = 0x00C0C000}, + { .reg =DDRC_DRAMTMG4(0), .val = 0x0F04080F}, + { .reg =DDRC_DRAMTMG5(0), .val = 0x02040C0C}, + { .reg =DDRC_DRAMTMG6(0), .val = 0x01010007}, + { .reg =DDRC_DRAMTMG7(0), .val = 0x00000401}, + { .reg =DDRC_DRAMTMG12(0), .val = 0x00020600}, + { .reg =DDRC_DRAMTMG13(0), .val = 0x0C100002}, + { .reg =DDRC_DRAMTMG14(0), .val = 0x000000E6}, + { .reg =DDRC_DRAMTMG17(0), .val = 0x00A00050}, + + { .reg =DDRC_ZQCTL0(0), .val = 0x03200018}, + { .reg =DDRC_ZQCTL1(0), .val = 0x028061A8}, + { .reg =DDRC_ZQCTL2(0), .val = 0x00000000}, + + { .reg =DDRC_DFITMG0(0), .val = 0x0497820A}, + { .reg =DDRC_DFITMG1(0), .val = 0x00080303}, + { .reg =DDRC_DFIUPD0(0), .val = 0xE0400018}, + + { .reg =DDRC_DFIUPD1(0), .val = 0x00DF00E4}, + { .reg =DDRC_DFIUPD2(0), .val = 0x80000000}, + { .reg =DDRC_DFIMISC(0), .val = 0x00000011}, + { .reg =DDRC_DFITMG2(0), .val = 0x0000170A}, + + { .reg =DDRC_DBICTL(0), .val = 0x00000001}, +#ifdef BUG_WR_DFI + { .reg =DDRC_DFIPHYMSTR(0), .val = 0x00000000}, +#else + { .reg =DDRC_DFIPHYMSTR(0), .val = 0x00000001}, +#endif + { .reg =DDRC_RANKCTL(0), .val = 0x00000c99}, + { .reg =DDRC_DRAMTMG2(0), .val = 0x070E171a}, +#ifdef M845S_4GBx2 +#ifdef DDR_ONE_RANK + { .reg =DDRC_ADDRMAP0(0), .val = 0x0000001f}, +#else + { .reg =DDRC_ADDRMAP0(0), .val = 0x00000017}, +#endif + { .reg =DDRC_ADDRMAP1(0), .val = 0x00080808}, + { .reg =DDRC_ADDRMAP2(0), .val = 0x00000000}, + { .reg =DDRC_ADDRMAP3(0), .val = 0x00000000}, + { .reg =DDRC_ADDRMAP4(0), .val = 0x00001f1f}, + { .reg =DDRC_ADDRMAP5(0), .val = 0x07070707}, + { .reg =DDRC_ADDRMAP6(0), .val = 0x07070707}, + { .reg =DDRC_ADDRMAP7(0), .val = 0x00000f0f}, +#else +#ifdef DDR_ONE_RANK + { .reg =DDRC_ADDRMAP0(0), .val = 0x0000001f}, +#else + { .reg =DDRC_ADDRMAP0(0), .val = 0x00000016}, +#endif + { .reg =DDRC_ADDRMAP1(0), .val = 0x00080808}, + { .reg =DDRC_ADDRMAP2(0), .val = 0x00000000}, + { .reg =DDRC_ADDRMAP3(0), .val = 0x00000000}, + { .reg =DDRC_ADDRMAP4(0), .val = 0x00001f1f}, + { .reg =DDRC_ADDRMAP5(0), .val = 0x07070707}, + { .reg =DDRC_ADDRMAP6(0), .val = 0x0f070707}, + { .reg =DDRC_ADDRMAP7(0), .val = 0x00000f0f}, + { .reg =DDRC_ADDRMAP8(0), .val = 0x00000000}, + { .reg =DDRC_ADDRMAP9(0), .val = 0x0a020b06}, + { .reg =DDRC_ADDRMAP10(0), .val = 0x0a0a0a0a}, + { .reg =DDRC_ADDRMAP11(0), .val = 0x00000000}, +#endif + +#ifdef PERF_TEST_2 + { .reg =DDRC_SCHED(0), .val = 0x29001701}, + { .reg =DDRC_SCHED1(0), .val = 0x0000002c}, + { .reg =DDRC_PERFLPR1(0), .val = 0x900093e7}, + { .reg =DDRC_PCCFG(0), .val = 0x00000111}, + { .reg =DDRC_PCFGW_0(0), .val = 0x000072ff}, + { .reg =DDRC_PCFGQOS0_0(0), .val = 0x02100e07}, + { .reg =DDRC_PCFGQOS1_0(0), .val = 0x00620096}, + { .reg =DDRC_PCFGWQOS0_0(0), .val = 0x01100e07}, + { .reg =DDRC_PCFGWQOS1_0(0), .val = 0x0000012c}, +#else + { .reg =DDRC_SCHED(0), .val = 0x29001701}, + { .reg =DDRC_SCHED1(0), .val = 0x0000002c}, + { .reg =DDRC_PERFHPR1(0), .val = 0x04000030}, + { .reg =DDRC_PERFLPR1(0), .val = 0x900093e7}, + { .reg =DDRC_PCCFG(0), .val = 0x00000111}, + { .reg =DDRC_PCFGW_0(0), .val = 0x000072ff}, + { .reg =DDRC_PCFGQOS0_0(0), .val = 0x02100e07}, + { .reg =DDRC_PCFGQOS1_0(0), .val = 0x00620096}, + { .reg =DDRC_PCFGWQOS0_0(0), .val = 0x01100e07}, + { .reg =DDRC_PCFGWQOS1_0(0), .val = 0x0000012c}, +#endif + +#ifdef P1_400 + { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0x0d0b010c}, + { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x00030410}, + { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x0305090c}, + { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x00505006}, + { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x05040305}, + { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x0d0e0504}, + { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x0a060004}, + { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x0000090e}, + { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x00000032}, + { .reg =DDRC_FREQ1_DRAMTMG15(0), .val = 0x00000000}, + { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0036001b}, + { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x7e9fbeb1}, + { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x03818200}, + { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x00000000}, + { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x000C001c}, + { .reg =DDRC_FREQ1_INIT3(0), .val = 0x00840000}, + { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000}, + { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004a}, + { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004a}, +#else +#ifdef WEI_667 + { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0x0d0b0107}, + { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x00030410}, + { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x0305080c}, + { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x00505006}, + { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x05040305}, + { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x0f0b0504}, + { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x0e0c000c}, + { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x00000607}, + { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x00000066}, + { .reg =DDRC_FREQ1_DRAMTMG15(0), .val = 0x80000000}, + { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0036001b}, + { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x03858202}, + { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x00000502}, + { .reg =DDRC_FREQ1_DERATEEN(0), .val = 0x00000001}, + { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x2545eb1c}, + { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x0014002f}, + { .reg =DDRC_FREQ1_INIT3(0), .val = 0x00140009}, + { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000}, + { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004d}, + { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004d}, +#else + { .reg =DDRC_FREQ1_DERATEEN(0), .val = 0x0000000}, + { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x0800000}, + { .reg =DDRC_FREQ1_RFSHCTL0(0), .val = 0x0210000}, + { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x014001E}, + { .reg =DDRC_FREQ1_INIT3(0), .val = 0x0140009}, + { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000}, + { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004a}, + { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004a}, + { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0xB070A07}, + { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x003040A}, + { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x305080C}, + { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x0505000}, + { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x3040203}, + { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x2030303}, + { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x2020004}, + { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x0000302}, + { .reg =DDRC_FREQ1_DRAMTMG12(0), .val = 0x0020310}, + { .reg =DDRC_FREQ1_DRAMTMG13(0), .val = 0xA100002}, + { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x0000020}, + { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0220011}, + { .reg =DDRC_FREQ1_ZQCTL0(0), .val = 0x0A70005}, + { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x3858202}, + { .reg =DDRC_FREQ1_DFITMG1(0), .val = 0x0000404}, + { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x0000502}, +#endif +#endif + { .reg =DDRC_FREQ2_DRAMTMG0(0), .val = 0x0d0b010c}, + { .reg =DDRC_FREQ2_DRAMTMG1(0), .val = 0x00030410}, + { .reg =DDRC_FREQ2_DRAMTMG2(0), .val = 0x0305090c}, + { .reg =DDRC_FREQ2_DRAMTMG3(0), .val = 0x00505006}, + { .reg =DDRC_FREQ2_DRAMTMG4(0), .val = 0x05040305}, + { .reg =DDRC_FREQ2_DRAMTMG5(0), .val = 0x0d0e0504}, + { .reg =DDRC_FREQ2_DRAMTMG6(0), .val = 0x0a060004}, + { .reg =DDRC_FREQ2_DRAMTMG7(0), .val = 0x0000090e}, + { .reg =DDRC_FREQ2_DRAMTMG14(0), .val = 0x00000032}, + { .reg =DDRC_FREQ2_DRAMTMG17(0), .val = 0x0036001b}, + { .reg =DDRC_FREQ2_DERATEINT(0), .val = 0x7e9fbeb1}, + { .reg =DDRC_FREQ2_DFITMG0(0), .val = 0x03818200}, + { .reg =DDRC_FREQ2_DFITMG2(0), .val = 0x00000000}, + { .reg =DDRC_FREQ2_RFSHTMG(0), .val = 0x00030007}, + { .reg =DDRC_FREQ2_INIT3(0), .val = 0x00840000}, + { .reg =DDRC_FREQ2_INIT4(0), .val = 0x00310000}, + { .reg =DDRC_FREQ2_INIT6(0), .val = 0x0066004a}, + { .reg =DDRC_FREQ2_INIT7(0), .val = 0x0006004a}, +#ifdef DDR_BOOT_P2 + { .reg =DDRC_MSTR2(0), .val = 0x2}, +#else +#ifdef DDR_BOOT_P1 + { .reg =DDRC_MSTR2(0), .val = 0x1}, +#else + { .reg =DDRC_MSTR2(0), .val = 0x0}, +#endif +#endif + { .reg = DDRC_ODTCFG(0), 0x0b060908}, + { .reg = DDRC_ODTMAP(0), 0x00000000}, + { .reg = DDRC_SCHED(0), 0x29511505}, + { .reg = DDRC_SCHED1(0), 0x0000002c}, + { .reg = DDRC_PERFHPR1(0), 0x5900575b}, + { .reg = DDRC_PERFLPR1(0), 0x00000009}, + { .reg = DDRC_PERFWR1(0), 0x02005574}, + { .reg = DDRC_DBG0(0), 0x00000016}, + { .reg = DDRC_DBG1(0), 0x00000000}, + { .reg = DDRC_DBGCMD(0), 0x00000000}, + { .reg = DDRC_SWCTL(0), 0x00000001}, + { .reg = DDRC_POISONCFG(0), 0x00000011}, + { .reg = DDRC_PCCFG(0), 0x00000111}, + { .reg = DDRC_PCFGR_0(0), 0x000010f3}, + { .reg = DDRC_PCFGW_0(0), 0x000072ff}, + { .reg = DDRC_PCTRL_0(0), 0x00000001}, + { .reg = DDRC_PCFGQOS0_0(0), 0x01110d00}, + { .reg = DDRC_PCFGQOS1_0(0), 0x00620790}, + { .reg = DDRC_PCFGWQOS0_0(0), 0x00100001}, + { .reg = DDRC_PCFGWQOS1_0(0), 0x0000041f}, + { .reg = DDRC_FREQ1_DERATEEN(0), 0x00000202}, + { .reg = DDRC_FREQ1_DERATEINT(0), 0xec78f4b5}, + { .reg = DDRC_FREQ1_RFSHCTL0(0), 0x00618040}, + { .reg = DDRC_FREQ1_RFSHTMG(0), 0x00610090}, +}; + +void lpddr4_3000mts_cfg_umctl2(void) +{ + u32 index, reg, val, num; + + num = sizeof(ctl_init_cfg)/sizeof(struct ddr_ctl_param); + + for (index = 0; index < num; index++) { + val = ctl_init_cfg[index].val; + reg = ctl_init_cfg[index].reg; + writel(val, (void __iomem *)(u64)reg); + } +} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_define.h b/board/freescale/imx8mm_evk/ddr/lpddr4_define.h new file mode 100644 index 0000000..712edf6 --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/lpddr4_define.h @@ -0,0 +1,161 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef LPDDR4_DEFINE_H +#define LPDDR4_DEFINE_H + +#include "ddr.h" + +#define RUN_ON_SILICON +#define DFI_BUG_WR +#define DEVINIT_PHY + +#define DDR_ONE_RANK +#define BUG_WR_DFI +#define M845S_4GBx2 + +#ifdef LPDDR4_667MTS +#define P0_667 +#endif +#ifdef LPDDR4_1600MTS +#define P0_1600 +#endif +#ifdef LPDDR4_DVFS +#define DVFS_TEST +#define PHY_TRAIN +#define DDR_BOOT_P1 +#endif +#ifdef LPDDR4_RETENTION +#define NORMAL_RET_EN +#endif + +#ifdef P0_667 +#define P0_DRATE 667 +#else +#ifdef P0_1600 +#define P0_DRATE 1600 +#else +#define P0_DRATE 3000 +#endif +#endif + +#define P1_DRATE 667 +#define P2_DRATE 100 + +#ifdef RUN_ON_SILICON +#define PHY_TRAIN +#define ADD_P0_2D_BF_P1 +#ifdef HWFFC +#define ADD_TRAIN_1D_P2 +#endif +#else +#define DDR_FAST_SIM +#endif + +#ifdef PHY_TRAIN +#define ADD_TRAIN_1D_P0 +#ifdef DVFS_TEST +#define ADD_TRAIN_1D_P1 +#endif +#endif + +/* define BOOT FREQ, not modify */ +#ifdef DDR_BOOT_P1 +#define BOOT_FREQ P1_DRATE +#else +#ifdef DDR_BOOT_P2 +#define BOOT_FREQ P2_DRATE +#else +#define BOOT_FREQ P0_DRATE +#endif +#endif + +/* #define P1_FREQ 167 */ +#ifdef PHY_TRAIN +#define CLOCK_SWITCH_PLL P0_DRATE +#else +#define CLOCK_SWITCH_PLL BOOT_FREQ +#endif + +#define DDR_CSD2_BASE_ADDR 0x80000000 +#define GPC_PU_PWRHSK 0x303A01FC + +//---------------------------------------------------------------- +// PHY training feature +//---------------------------------------------------------------- +#define LPDDR4_HDT_CTL_2D 0xC8 //stage completion +#define LPDDR4_HDT_CTL_3200_1D 0xC8 //stage completion +#define LPDDR4_HDT_CTL_400_1D 0xC8 //stage completion +#define LPDDR4_HDT_CTL_100_1D 0xC8 //stage completion + +#define LPDDR4_HDT_CTL_2D 0xC8 //stage completion +#define LPDDR4_HDT_CTL_3200_1D 0xC8 //stage completion +#define LPDDR4_HDT_CTL_400_1D 0xC8 //stage completion +#define LPDDR4_HDT_CTL_100_1D 0xC8 //stage completion + +#ifdef RUN_ON_SILICON +// 400/100 training seq +#define LPDDR4_TRAIN_SEQ_P2 0x121f +#define LPDDR4_TRAIN_SEQ_P1 0x121f +#define LPDDR4_TRAIN_SEQ_P0 0x121f +#else +#define LPDDR4_TRAIN_SEQ_P2 0x7 +#define LPDDR4_TRAIN_SEQ_P1 0x7 +#define LPDDR4_TRAIN_SEQ_P0 0x7 +#endif + +//2D share & weight +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +/* MRS parameter */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */ +#define LPDDR4_PHY_RTT 30 /* //30//40//28 */ +/* #define LPDDR4_PHY_VREF_VALUE 27//17//17//20//16///17,//for M845S */ +#define LPDDR4_PHY_VREF_VALUE 17 /*//17//20//16///17,//for M850D*/ + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 +#define LPDDR4_RTT_CA LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 +#define LPDDR4_VREF_VALUE_CA ((1 << 6)|0xd) +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6)|0xd) +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6)|0xd) +#define LPDDR4_MR22_RANK0 ((0 << 5)|(0 << 4)|(0 << 3)|(LPDDR4_RTT40)) +#define LPDDR4_MR22_RANK1 ((1 << 5)|(0 << 4)|(1 << 3)|(LPDDR4_RTT40)) +#define LPDDR4_MR3_PU_CAL 1 + +#endif diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c b/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c new file mode 100644 index 0000000..90daf0f --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c @@ -0,0 +1,154 @@ +/* + * Copyright 2018 NXP + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "lpddr4_define.h" + +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate) +{ + if(pstate==2) + dram_pll_init(DRAM_PLL_OUT_100M); + else if(pstate==1) + dram_pll_init(DRAM_PLL_OUT_667M); + else + dram_pll_init(DRAM_PLL_OUT_750M); +} + +int dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void) +{ + volatile unsigned int tmp, tmp_t; + volatile unsigned int train_ok; + volatile unsigned int train_fail; + volatile unsigned int stream_msg; + int ret = 0; + + train_ok = 0; + train_fail = 0; + stream_msg = 0; + while (train_ok == 0 && train_fail == 0) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + tmp_t = tmp & 0x01; + while (tmp_t){ + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + tmp_t = tmp & 0x01; + } +#ifdef PRINT_PMU + printf("get the training message\n"); +#endif + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); +#ifdef PRINT_PMU + printf("PMU major stream =0x%x\n",tmp); +#endif + if (tmp==0x08) { + stream_msg = 1; + +#ifdef DDR_PRINT_ALL_MESSAGE + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + }while((tmp_t & 0x1) == 0x0); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + }while((tmp_t & 0x1) == 0x1); + + /* read_mbox_mssg */ + stream_nb_args = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +4 * 0xd0032); + + /* read_mbox_msb */ + stream_index = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); + stream_index = (stream_index << 16) | stream_nb_args; +#ifdef PRINT_PMU + printf("PMU stream_index=0x%x nb_args=%d\n",stream_index, stream_nb_args); +#endif + + stream_arg_pos = 0; + while (stream_nb_args > 0) { + /* Need to complete previous handshake first... */ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); + /* poll_mbox_from_uc(1); */ + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + } while((tmp_t & 0x1) == 0x0); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); + + /* Read the next argument... */ + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + }while((tmp_t & 0x1) == 0x1); + + /* read_mbox_mssg */ + message = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); + /* read_mbox_msb */ + stream_arg_val = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); + stream_arg_val = (stream_arg_val << 16) | message; +#ifdef PRINT_PMU + printf("PMU stream_arg[%d]=0x%x\n",stream_arg_pos, stream_arg_val); +#endif + stream_nb_args--; + stream_arg_pos++; + } +#endif + } else if(tmp==0x07) { + train_ok = 1; + ret = 0; + } else if(tmp==0xff) { + train_fail = 1; + printf("%c[31;40m",0x1b); + printf("------- training vt_fail\n"); + printf("%c[0m",0x1b); + + ret = -1; + } else { + train_ok = 0; + train_fail = 0; + stream_msg = 0; + } + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0); + + if (stream_msg == 1) { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); + } + + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + tmp_t = tmp & 0x01; + while(tmp_t==0){ + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + tmp_t = tmp & 0x01; + } + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1); + } + + return ret; +} + +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned long run_2D) +{ +} + +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void) +{ +} +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void) +{ +} +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void) +{ +} +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) +{ +} +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) +{ +} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c b/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c new file mode 100644 index 0000000..4a216ad --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c @@ -0,0 +1,943 @@ +/* + * Copyright 2018 NXP + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "lpddr4_define.h" + +struct ddr_phy_param { + u32 reg; /* reg address */ + u32 val; /* config param */ +}; + + +#define DDR_PHY_FLAG_ADDR 0x00187F00 + +static struct ddr_phy_param phy_init_cfg[] = +{ + { .reg = 0x3c000000+4*0x1005f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x1015f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x1105f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x1115f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x1205f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x1215f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x1305f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x1315f, .val = 0x15f}, + { .reg = 0x3c000000+4*0x55, .val = 0x16f}, + { .reg = 0x3c000000+4*0x1055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x2055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x3055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x4055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x5055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x6055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x7055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x8055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x9055, .val = 0x16f}, + { .reg = 0x3c000000+4*0x200c5, .val = 0x19}, + { .reg = 0x3c000000+4*0x2002e, .val = 0x2}, + { .reg = 0x3c000000+4*0x90204, .val = 0x0}, + { .reg = 0x3c000000+4*0x20024, .val = 0xab}, + { .reg = 0x3c000000+4*0x2003a, .val = 0x0}, + { .reg = 0x3c000000+4*0x20056, .val = 0x3}, + { .reg = 0x3c000000+4*0x1004d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x1014d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x1104d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x1114d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x1204d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x1214d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x1304d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x1314d, .val = 0xe00}, + { .reg = 0x3c000000+4*0x10049, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x10149, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x11049, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x11149, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x12049, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x12149, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x13049, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x13149, .val = 0xfbe}, + { .reg = 0x3c000000+4*0x43, .val = 0x63}, + { .reg = 0x3c000000+4*0x1043, .val = 0x63}, + { .reg = 0x3c000000+4*0x2043, .val = 0x63}, + { .reg = 0x3c000000+4*0x3043, .val = 0x63}, + { .reg = 0x3c000000+4*0x4043, .val = 0x63}, + { .reg = 0x3c000000+4*0x5043, .val = 0x63}, + { .reg = 0x3c000000+4*0x6043, .val = 0x63}, + { .reg = 0x3c000000+4*0x7043, .val = 0x63}, + { .reg = 0x3c000000+4*0x8043, .val = 0x63}, + { .reg = 0x3c000000+4*0x9043, .val = 0x63}, + { .reg = 0x3c000000+4*0x20018, .val = 0x3}, + { .reg = 0x3c000000+4*0x20075, .val = 0x4}, + { .reg = 0x3c000000+4*0x20050, .val = 0x0}, + { .reg = 0x3c000000+4*0x20008, .val = 0x2ee}, + { .reg = 0x3c000000+4*0x20088, .val = 0x9}, + { .reg = 0x3c000000+4*0x200b2, .val = 0x1d4}, + { .reg = 0x3c000000+4*0x10043, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x10143, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x11043, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x11143, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x12043, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x12143, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x13043, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x13143, .val = 0x5a1}, + { .reg = 0x3c000000+4*0x200fa, .val = 0x1}, + { .reg = 0x3c000000+4*0x20019, .val = 0x1}, + { .reg = 0x3c000000+4*0x200f0, .val = 0x600}, + { .reg = 0x3c000000+4*0x200f1, .val = 0x0}, + { .reg = 0x3c000000+4*0x200f2, .val = 0x4444}, + { .reg = 0x3c000000+4*0x200f3, .val = 0x8888}, + { .reg = 0x3c000000+4*0x200f4, .val = 0x5655}, + { .reg = 0x3c000000+4*0x200f5, .val = 0x0}, + { .reg = 0x3c000000+4*0x200f6, .val = 0x0}, + { .reg = 0x3c000000+4*0x200f7, .val = 0xf000}, + { .reg = 0x3c000000+4*0x20025, .val = 0x0}, + { .reg = 0x3c000000+4*0x2002d, .val = 0x0}, + { .reg = 0x3c000000+4*0x200c7, .val = 0x21}, + { .reg = 0x3c000000+4*0x200ca, .val = 0x24}, + { .reg = 0x3c000000+4*0x20060, .val = 0x2}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x00}, + + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x01}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, +#ifdef RUN_ON_SILICON + { .reg = 0x3c000000+4*0x54000, .val = 0x0}, +#else + { .reg = 0x3c000000+4*0x54000, .val = 0x600}, +#endif + { .reg = 0x3c000000+4*0x54001, .val = 0x0}, + { .reg = 0x3c000000+4*0x54002, .val = 0x0}, + { .reg = 0x3c000000+4*0x54003, .val = 0xbb8}, + { .reg = 0x3c000000+4*0x54004, .val = 0x2}, + { .reg = 0x3c000000+4*0x54005, .val = ((LPDDR4_PHY_RON<<8)|LPDDR4_PHY_RTT)}, + { .reg = 0x3c000000+4*0x54006, .val = LPDDR4_PHY_VREF_VALUE}, + { .reg = 0x3c000000+4*0x54007, .val = 0x0}, +#ifdef RUN_ON_SILICON + { .reg = 0x3c000000+4*0x54008, .val = 0x131f}, +#else + { .reg = 0x3c000000+4*0x54008, .val = 0x7}, +#endif + { .reg = 0x3c000000+4*0x54009, .val = 0xc8}, + { .reg = 0x3c000000+4*0x5400a, .val = 0x0}, + { .reg = 0x3c000000+4*0x5400b, .val = 0x2}, + { .reg = 0x3c000000+4*0x5400c, .val = 0x0}, + { .reg = 0x3c000000+4*0x5400d, .val = 0x100}, + { .reg = 0x3c000000+4*0x5400e, .val = 0x0}, + { .reg = 0x3c000000+4*0x5400f, .val = 0x0}, + { .reg = 0x3c000000+4*0x54010, .val = 0x0}, + { .reg = 0x3c000000+4*0x54011, .val = 0x0}, +#ifdef DDR_ONE_RANK + { .reg = 0x3c000000+4*0x54012, .val = 0x110}, +#else + { .reg = 0x3c000000+4*0x54012, .val = 0x310}, +#endif + { .reg = 0x3c000000+4*0x54013, .val = 0x0}, + { .reg = 0x3c000000+4*0x54014, .val = 0x0}, + { .reg = 0x3c000000+4*0x54015, .val = 0x0}, + { .reg = 0x3c000000+4*0x54016, .val = 0x0}, + { .reg = 0x3c000000+4*0x54017, .val = 0x0}, + { .reg = 0x3c000000+4*0x54018, .val = 0x0}, + + { .reg = 0x3c000000+4*0x54019, .val = 0x2dd4}, + { .reg = 0x3c000000+4*0x5401a, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, + { .reg = 0x3c000000+4*0x5401b, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)/*0x4d66*/}, + { .reg = 0x3c000000+4*0x5401c, .val = ((LPDDR4_VREF_VALUE_DQ_RANK0<<8)|0x08)/*0x4d08*/}, + { .reg = 0x3c000000+4*0x5401d, .val = 0x0}, + { .reg = 0x3c000000+4*0x5401e, .val = LPDDR4_MR22_RANK0/*0x16*/}, + { .reg = 0x3c000000+4*0x5401f, .val = 0x2dd4}, + { .reg = 0x3c000000+4*0x54020, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, + { .reg = 0x3c000000+4*0x54021, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)/*0x4d66*/}, + { .reg = 0x3c000000+4*0x54022, .val = ((LPDDR4_VREF_VALUE_DQ_RANK1<<8)|0x08)/*0x4d08*/}, + { .reg = 0x3c000000+4*0x54023, .val = 0x0}, + { .reg = 0x3c000000+4*0x54024, .val = LPDDR4_MR22_RANK1/*0x16*/}, + + { .reg = 0x3c000000+4*0x54025, .val = 0x0}, + { .reg = 0x3c000000+4*0x54026, .val = 0x0}, + { .reg = 0x3c000000+4*0x54027, .val = 0x0}, + { .reg = 0x3c000000+4*0x54028, .val = 0x0}, + { .reg = 0x3c000000+4*0x54029, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402a, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402b, .val = 0x1000}, +#ifdef DDR_ONE_RANK + { .reg = 0x3c000000+4*0x5402c, .val = 0x1}, +#else + { .reg = 0x3c000000+4*0x5402c, .val = 0x3}, +#endif + { .reg = 0x3c000000+4*0x5402d, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402e, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402f, .val = 0x0}, + { .reg = 0x3c000000+4*0x54030, .val = 0x0}, + { .reg = 0x3c000000+4*0x54031, .val = 0x0}, + + { .reg = 0x3c000000+4*0x54032, .val = 0xd400}, + { .reg = 0x3c000000+4*0x54033, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, + { .reg = 0x3c000000+4*0x54034, .val = (((LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, + { .reg = 0x3c000000+4*0x54035, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, + { .reg = 0x3c000000+4*0x54036, .val = LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/}, + { .reg = 0x3c000000+4*0x54037, .val = (LPDDR4_MR22_RANK0<<8)/*0x1600*/}, + { .reg = 0x3c000000+4*0x54038, .val = 0xd400}, + { .reg = 0x3c000000+4*0x54039, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, + { .reg = 0x3c000000+4*0x5403a, .val = (((LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, + { .reg = 0x3c000000+4*0x5403b, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, + { .reg = 0x3c000000+4*0x5403c, .val = LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/}, + { .reg = 0x3c000000+4*0x5403d, .val = (LPDDR4_MR22_RANK1<<8)/*0x1600*/}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0099, .val = 0x9}, + { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0099, .val = 0x0}, + + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x02}, + + { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, + + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x03}, + + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x04}, + + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + + + + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, + + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x05}, + + + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, +#ifdef RUN_ON_SILICON + { .reg = 0x3c000000+4*0x54000, .val = 0x0}, +#else + { .reg = 0x3c000000+4*0x54000, .val = 0x600}, +#endif + { .reg = 0x3c000000+4*0x54001, .val = 0x0}, + { .reg = 0x3c000000+4*0x54002, .val = 0x0}, + { .reg = 0x3c000000+4*0x54003, .val = 0xbb8}, + { .reg = 0x3c000000+4*0x54004, .val = 0x2}, + + { .reg = 0x3c000000+4*0x54005, .val = ((LPDDR4_PHY_RON<<8)|LPDDR4_PHY_RTT)}, + { .reg = 0x3c000000+4*0x54006, .val = LPDDR4_PHY_VREF_VALUE}, + + { .reg = 0x3c000000+4*0x54007, .val = 0x0}, +#ifdef RUN_ON_SILICON + { .reg = 0x3c000000+4*0x54008, .val = 0x61}, +#else + { .reg = 0x3c000000+4*0x54008, .val = 0x1}, +#endif + { .reg = 0x3c000000+4*0x54009, .val = 0xc8}, + { .reg = 0x3c000000+4*0x5400a, .val = 0x0}, + { .reg = 0x3c000000+4*0x5400b, .val = 0x2}, + { .reg = 0x3c000000+4*0x5400c, .val = 0x0}, + { .reg = 0x3c000000+4*0x5400d, .val = 0x100}, + { .reg = 0x3c000000+4*0x5400e, .val = 0x0}, + { .reg = 0x3c000000+4*0x5400f, .val = 0x100}, + + { .reg = 0x3c000000+4*0x54010, .val = LPDDR4_2D_WEIGHT}, + + { .reg = 0x3c000000+4*0x54011, .val = 0x0}, +#ifdef DDR_ONE_RANK + { .reg = 0x3c000000+4*0x54012, .val = 0x110}, +#else + { .reg = 0x3c000000+4*0x54012, .val = 0x310}, +#endif + { .reg = 0x3c000000+4*0x54013, .val = 0x0}, + { .reg = 0x3c000000+4*0x54014, .val = 0x0}, + { .reg = 0x3c000000+4*0x54015, .val = 0x0}, + { .reg = 0x3c000000+4*0x54016, .val = 0x0}, + { .reg = 0x3c000000+4*0x54017, .val = 0x0}, + { .reg = 0x3c000000+4*0x54018, .val = 0x0}, + + { .reg = 0x3c000000+4*0x54019, .val = 0x2dd4}, + { .reg = 0x3c000000+4*0x5401a, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, + { .reg = 0x3c000000+4*0x5401b, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)/*0x4d46*/}, + { .reg = 0x3c000000+4*0x5401c, .val = ((LPDDR4_VREF_VALUE_DQ_RANK0<<8)|0x08)/*0x4d08*/}, + { .reg = 0x3c000000+4*0x5401d, .val = 0x0}, + { .reg = 0x3c000000+4*0x5401e, .val = LPDDR4_MR22_RANK0/*0x16*/}, + { .reg = 0x3c000000+4*0x5401f, .val = 0x2dd4}, + { .reg = 0x3c000000+4*0x54020, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, + { .reg = 0x3c000000+4*0x54021, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)/*0x4d46*/}, + { .reg = 0x3c000000+4*0x54022, .val = ((LPDDR4_VREF_VALUE_DQ_RANK1<<8)|0x08)/*0x4d08*/}, + { .reg = 0x3c000000+4*0x54023, .val = 0x0}, + { .reg = 0x3c000000+4*0x54024, .val = LPDDR4_MR22_RANK1/*0x16*/}, + + { .reg = 0x3c000000+4*0x54025, .val = 0x0}, + { .reg = 0x3c000000+4*0x54026, .val = 0x0}, + { .reg = 0x3c000000+4*0x54027, .val = 0x0}, + { .reg = 0x3c000000+4*0x54028, .val = 0x0}, + { .reg = 0x3c000000+4*0x54029, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402a, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402b, .val = 0x1000}, +#ifdef DDR_ONE_RANK + { .reg = 0x3c000000+4*0x5402c, .val = 0x1}, +#else + { .reg = 0x3c000000+4*0x5402c, .val = 0x3}, +#endif + { .reg = 0x3c000000+4*0x5402d, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402e, .val = 0x0}, + { .reg = 0x3c000000+4*0x5402f, .val = 0x0}, + { .reg = 0x3c000000+4*0x54030, .val = 0x0}, + { .reg = 0x3c000000+4*0x54031, .val = 0x0}, + + { .reg = 0x3c000000+4*0x54032, .val = 0xd400}, + { .reg = 0x3c000000+4*0x54033, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, + { .reg = 0x3c000000+4*0x54034, .val = (((LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, + { .reg = 0x3c000000+4*0x54035, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, + { .reg = 0x3c000000+4*0x54036, .val = LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/}, + { .reg = 0x3c000000+4*0x54037, .val = (LPDDR4_MR22_RANK0<<8)/*0x1600*/}, + { .reg = 0x3c000000+4*0x54038, .val = 0xd400}, + { .reg = 0x3c000000+4*0x54039, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, + { .reg = 0x3c000000+4*0x5403a, .val = (((LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, + { .reg = 0x3c000000+4*0x5403b, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, + { .reg = 0x3c000000+4*0x5403c, .val = LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/}, + { .reg = 0x3c000000+4*0x5403d, .val = (LPDDR4_MR22_RANK1<<8)/*0x1600*/}, + + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0099, .val = 0x9}, + { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0099, .val = 0x0}, + + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x06}, + + { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, + + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x07}, + + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + + { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, + + { .reg = 0x3c000000+4*0x90000, .val = 0x10}, + { .reg = 0x3c000000+4*0x90001, .val = 0x400}, + { .reg = 0x3c000000+4*0x90002, .val = 0x10e}, + { .reg = 0x3c000000+4*0x90003, .val = 0x0}, + { .reg = 0x3c000000+4*0x90004, .val = 0x0}, + { .reg = 0x3c000000+4*0x90005, .val = 0x8}, + { .reg = 0x3c000000+4*0x90029, .val = 0xb}, + { .reg = 0x3c000000+4*0x9002a, .val = 0x480}, + { .reg = 0x3c000000+4*0x9002b, .val = 0x109}, + { .reg = 0x3c000000+4*0x9002c, .val = 0x8}, + { .reg = 0x3c000000+4*0x9002d, .val = 0x448}, + { .reg = 0x3c000000+4*0x9002e, .val = 0x139}, + { .reg = 0x3c000000+4*0x9002f, .val = 0x8}, + { .reg = 0x3c000000+4*0x90030, .val = 0x478}, + { .reg = 0x3c000000+4*0x90031, .val = 0x109}, + { .reg = 0x3c000000+4*0x90032, .val = 0x0}, + { .reg = 0x3c000000+4*0x90033, .val = 0xe8}, + { .reg = 0x3c000000+4*0x90034, .val = 0x109}, + { .reg = 0x3c000000+4*0x90035, .val = 0x2}, + { .reg = 0x3c000000+4*0x90036, .val = 0x10}, + { .reg = 0x3c000000+4*0x90037, .val = 0x139}, + { .reg = 0x3c000000+4*0x90038, .val = 0xf}, + { .reg = 0x3c000000+4*0x90039, .val = 0x7c0}, + { .reg = 0x3c000000+4*0x9003a, .val = 0x139}, + { .reg = 0x3c000000+4*0x9003b, .val = 0x44}, + { .reg = 0x3c000000+4*0x9003c, .val = 0x630}, + { .reg = 0x3c000000+4*0x9003d, .val = 0x159}, + { .reg = 0x3c000000+4*0x9003e, .val = 0x14f}, + { .reg = 0x3c000000+4*0x9003f, .val = 0x630}, + { .reg = 0x3c000000+4*0x90040, .val = 0x159}, + { .reg = 0x3c000000+4*0x90041, .val = 0x47}, + { .reg = 0x3c000000+4*0x90042, .val = 0x630}, + { .reg = 0x3c000000+4*0x90043, .val = 0x149}, + { .reg = 0x3c000000+4*0x90044, .val = 0x4f}, + { .reg = 0x3c000000+4*0x90045, .val = 0x630}, + { .reg = 0x3c000000+4*0x90046, .val = 0x179}, + { .reg = 0x3c000000+4*0x90047, .val = 0x8}, + { .reg = 0x3c000000+4*0x90048, .val = 0xe0}, + { .reg = 0x3c000000+4*0x90049, .val = 0x109}, + { .reg = 0x3c000000+4*0x9004a, .val = 0x0}, + { .reg = 0x3c000000+4*0x9004b, .val = 0x7c8}, + { .reg = 0x3c000000+4*0x9004c, .val = 0x109}, + { .reg = 0x3c000000+4*0x9004d, .val = 0x0}, + { .reg = 0x3c000000+4*0x9004e, .val = 0x1}, + { .reg = 0x3c000000+4*0x9004f, .val = 0x8}, + { .reg = 0x3c000000+4*0x90050, .val = 0x0}, + { .reg = 0x3c000000+4*0x90051, .val = 0x45a}, + { .reg = 0x3c000000+4*0x90052, .val = 0x9}, + { .reg = 0x3c000000+4*0x90053, .val = 0x0}, + { .reg = 0x3c000000+4*0x90054, .val = 0x448}, + { .reg = 0x3c000000+4*0x90055, .val = 0x109}, + { .reg = 0x3c000000+4*0x90056, .val = 0x40}, + { .reg = 0x3c000000+4*0x90057, .val = 0x630}, + { .reg = 0x3c000000+4*0x90058, .val = 0x179}, + { .reg = 0x3c000000+4*0x90059, .val = 0x1}, + { .reg = 0x3c000000+4*0x9005a, .val = 0x618}, + { .reg = 0x3c000000+4*0x9005b, .val = 0x109}, + { .reg = 0x3c000000+4*0x9005c, .val = 0x40c0}, + { .reg = 0x3c000000+4*0x9005d, .val = 0x630}, + { .reg = 0x3c000000+4*0x9005e, .val = 0x149}, + { .reg = 0x3c000000+4*0x9005f, .val = 0x8}, + { .reg = 0x3c000000+4*0x90060, .val = 0x4}, + { .reg = 0x3c000000+4*0x90061, .val = 0x48}, + { .reg = 0x3c000000+4*0x90062, .val = 0x4040}, + { .reg = 0x3c000000+4*0x90063, .val = 0x630}, + { .reg = 0x3c000000+4*0x90064, .val = 0x149}, + { .reg = 0x3c000000+4*0x90065, .val = 0x0}, + { .reg = 0x3c000000+4*0x90066, .val = 0x4}, + { .reg = 0x3c000000+4*0x90067, .val = 0x48}, + { .reg = 0x3c000000+4*0x90068, .val = 0x40}, + { .reg = 0x3c000000+4*0x90069, .val = 0x630}, + { .reg = 0x3c000000+4*0x9006a, .val = 0x149}, + { .reg = 0x3c000000+4*0x9006b, .val = 0x10}, + { .reg = 0x3c000000+4*0x9006c, .val = 0x4}, + { .reg = 0x3c000000+4*0x9006d, .val = 0x18}, + { .reg = 0x3c000000+4*0x9006e, .val = 0x0}, + { .reg = 0x3c000000+4*0x9006f, .val = 0x4}, + { .reg = 0x3c000000+4*0x90070, .val = 0x78}, + { .reg = 0x3c000000+4*0x90071, .val = 0x549}, + { .reg = 0x3c000000+4*0x90072, .val = 0x630}, + { .reg = 0x3c000000+4*0x90073, .val = 0x159}, + { .reg = 0x3c000000+4*0x90074, .val = 0xd49}, + { .reg = 0x3c000000+4*0x90075, .val = 0x630}, + { .reg = 0x3c000000+4*0x90076, .val = 0x159}, + { .reg = 0x3c000000+4*0x90077, .val = 0x94a}, + { .reg = 0x3c000000+4*0x90078, .val = 0x630}, + { .reg = 0x3c000000+4*0x90079, .val = 0x159}, + { .reg = 0x3c000000+4*0x9007a, .val = 0x441}, + { .reg = 0x3c000000+4*0x9007b, .val = 0x630}, + { .reg = 0x3c000000+4*0x9007c, .val = 0x149}, + { .reg = 0x3c000000+4*0x9007d, .val = 0x42}, + { .reg = 0x3c000000+4*0x9007e, .val = 0x630}, + { .reg = 0x3c000000+4*0x9007f, .val = 0x149}, + { .reg = 0x3c000000+4*0x90080, .val = 0x1}, + { .reg = 0x3c000000+4*0x90081, .val = 0x630}, + { .reg = 0x3c000000+4*0x90082, .val = 0x149}, + { .reg = 0x3c000000+4*0x90083, .val = 0x0}, + { .reg = 0x3c000000+4*0x90084, .val = 0xe0}, + { .reg = 0x3c000000+4*0x90085, .val = 0x109}, + { .reg = 0x3c000000+4*0x90086, .val = 0xa}, + { .reg = 0x3c000000+4*0x90087, .val = 0x10}, + { .reg = 0x3c000000+4*0x90088, .val = 0x109}, + { .reg = 0x3c000000+4*0x90089, .val = 0x9}, + { .reg = 0x3c000000+4*0x9008a, .val = 0x3c0}, + { .reg = 0x3c000000+4*0x9008b, .val = 0x149}, + { .reg = 0x3c000000+4*0x9008c, .val = 0x9}, + { .reg = 0x3c000000+4*0x9008d, .val = 0x3c0}, + { .reg = 0x3c000000+4*0x9008e, .val = 0x159}, + { .reg = 0x3c000000+4*0x9008f, .val = 0x18}, + { .reg = 0x3c000000+4*0x90090, .val = 0x10}, + { .reg = 0x3c000000+4*0x90091, .val = 0x109}, + { .reg = 0x3c000000+4*0x90092, .val = 0x0}, + { .reg = 0x3c000000+4*0x90093, .val = 0x3c0}, + { .reg = 0x3c000000+4*0x90094, .val = 0x109}, + { .reg = 0x3c000000+4*0x90095, .val = 0x18}, + { .reg = 0x3c000000+4*0x90096, .val = 0x4}, + { .reg = 0x3c000000+4*0x90097, .val = 0x48}, + { .reg = 0x3c000000+4*0x90098, .val = 0x18}, + { .reg = 0x3c000000+4*0x90099, .val = 0x4}, + { .reg = 0x3c000000+4*0x9009a, .val = 0x58}, + { .reg = 0x3c000000+4*0x9009b, .val = 0xa}, + { .reg = 0x3c000000+4*0x9009c, .val = 0x10}, + { .reg = 0x3c000000+4*0x9009d, .val = 0x109}, + { .reg = 0x3c000000+4*0x9009e, .val = 0x2}, + { .reg = 0x3c000000+4*0x9009f, .val = 0x10}, + { .reg = 0x3c000000+4*0x900a0, .val = 0x109}, + { .reg = 0x3c000000+4*0x900a1, .val = 0x5}, + { .reg = 0x3c000000+4*0x900a2, .val = 0x7c0}, + { .reg = 0x3c000000+4*0x900a3, .val = 0x109}, + { .reg = 0x3c000000+4*0x900a4, .val = 0x10}, + { .reg = 0x3c000000+4*0x900a5, .val = 0x10}, + { .reg = 0x3c000000+4*0x900a6, .val = 0x109}, + { .reg = 0x3c000000+4*0x40000, .val = 0x811}, + { .reg = 0x3c000000+4*0x40020, .val = 0x880}, + { .reg = 0x3c000000+4*0x40040, .val = 0x0}, + { .reg = 0x3c000000+4*0x40060, .val = 0x0}, + { .reg = 0x3c000000+4*0x40001, .val = 0x4008}, + { .reg = 0x3c000000+4*0x40021, .val = 0x83}, + { .reg = 0x3c000000+4*0x40041, .val = 0x4f}, + { .reg = 0x3c000000+4*0x40061, .val = 0x0}, + { .reg = 0x3c000000+4*0x40002, .val = 0x4040}, + { .reg = 0x3c000000+4*0x40022, .val = 0x83}, + { .reg = 0x3c000000+4*0x40042, .val = 0x51}, + { .reg = 0x3c000000+4*0x40062, .val = 0x0}, + { .reg = 0x3c000000+4*0x40003, .val = 0x811}, + { .reg = 0x3c000000+4*0x40023, .val = 0x880}, + { .reg = 0x3c000000+4*0x40043, .val = 0x0}, + { .reg = 0x3c000000+4*0x40063, .val = 0x0}, + { .reg = 0x3c000000+4*0x40004, .val = 0x720}, + { .reg = 0x3c000000+4*0x40024, .val = 0xf}, + { .reg = 0x3c000000+4*0x40044, .val = 0x1740}, + { .reg = 0x3c000000+4*0x40064, .val = 0x0}, + { .reg = 0x3c000000+4*0x40005, .val = 0x16}, + { .reg = 0x3c000000+4*0x40025, .val = 0x83}, + { .reg = 0x3c000000+4*0x40045, .val = 0x4b}, + { .reg = 0x3c000000+4*0x40065, .val = 0x0}, + { .reg = 0x3c000000+4*0x40006, .val = 0x716}, + { .reg = 0x3c000000+4*0x40026, .val = 0xf}, + { .reg = 0x3c000000+4*0x40046, .val = 0x2001}, + { .reg = 0x3c000000+4*0x40066, .val = 0x0}, + { .reg = 0x3c000000+4*0x40007, .val = 0x716}, + { .reg = 0x3c000000+4*0x40027, .val = 0xf}, + { .reg = 0x3c000000+4*0x40047, .val = 0x2800}, + { .reg = 0x3c000000+4*0x40067, .val = 0x0}, + { .reg = 0x3c000000+4*0x40008, .val = 0x716}, + { .reg = 0x3c000000+4*0x40028, .val = 0xf}, + { .reg = 0x3c000000+4*0x40048, .val = 0xf00}, + { .reg = 0x3c000000+4*0x40068, .val = 0x0}, + { .reg = 0x3c000000+4*0x40009, .val = 0x720}, + { .reg = 0x3c000000+4*0x40029, .val = 0xf}, + { .reg = 0x3c000000+4*0x40049, .val = 0x1400}, + { .reg = 0x3c000000+4*0x40069, .val = 0x0}, + { .reg = 0x3c000000+4*0x4000a, .val = 0xe08}, + { .reg = 0x3c000000+4*0x4002a, .val = 0xc15}, + { .reg = 0x3c000000+4*0x4004a, .val = 0x0}, + { .reg = 0x3c000000+4*0x4006a, .val = 0x0}, + { .reg = 0x3c000000+4*0x4000b, .val = 0x623}, + { .reg = 0x3c000000+4*0x4002b, .val = 0x15}, + { .reg = 0x3c000000+4*0x4004b, .val = 0x0}, + { .reg = 0x3c000000+4*0x4006b, .val = 0x0}, + { .reg = 0x3c000000+4*0x4000c, .val = 0x4028}, + { .reg = 0x3c000000+4*0x4002c, .val = 0x80}, + { .reg = 0x3c000000+4*0x4004c, .val = 0x0}, + { .reg = 0x3c000000+4*0x4006c, .val = 0x0}, + { .reg = 0x3c000000+4*0x4000d, .val = 0xe08}, + { .reg = 0x3c000000+4*0x4002d, .val = 0xc1a}, + { .reg = 0x3c000000+4*0x4004d, .val = 0x0}, + { .reg = 0x3c000000+4*0x4006d, .val = 0x0}, + { .reg = 0x3c000000+4*0x4000e, .val = 0x623}, + { .reg = 0x3c000000+4*0x4002e, .val = 0x1a}, + { .reg = 0x3c000000+4*0x4004e, .val = 0x0}, + { .reg = 0x3c000000+4*0x4006e, .val = 0x0}, + { .reg = 0x3c000000+4*0x4000f, .val = 0x4040}, + { .reg = 0x3c000000+4*0x4002f, .val = 0x80}, + { .reg = 0x3c000000+4*0x4004f, .val = 0x0}, + { .reg = 0x3c000000+4*0x4006f, .val = 0x0}, + { .reg = 0x3c000000+4*0x40010, .val = 0x2604}, + { .reg = 0x3c000000+4*0x40030, .val = 0x15}, + { .reg = 0x3c000000+4*0x40050, .val = 0x0}, + { .reg = 0x3c000000+4*0x40070, .val = 0x0}, + { .reg = 0x3c000000+4*0x40011, .val = 0x708}, + { .reg = 0x3c000000+4*0x40031, .val = 0x5}, + { .reg = 0x3c000000+4*0x40051, .val = 0x0}, + { .reg = 0x3c000000+4*0x40071, .val = 0x2002}, + { .reg = 0x3c000000+4*0x40012, .val = 0x8}, + { .reg = 0x3c000000+4*0x40032, .val = 0x80}, + { .reg = 0x3c000000+4*0x40052, .val = 0x0}, + { .reg = 0x3c000000+4*0x40072, .val = 0x0}, + { .reg = 0x3c000000+4*0x40013, .val = 0x2604}, + { .reg = 0x3c000000+4*0x40033, .val = 0x1a}, + { .reg = 0x3c000000+4*0x40053, .val = 0x0}, + { .reg = 0x3c000000+4*0x40073, .val = 0x0}, + { .reg = 0x3c000000+4*0x40014, .val = 0x708}, + { .reg = 0x3c000000+4*0x40034, .val = 0xa}, + { .reg = 0x3c000000+4*0x40054, .val = 0x0}, + { .reg = 0x3c000000+4*0x40074, .val = 0x2002}, + { .reg = 0x3c000000+4*0x40015, .val = 0x4040}, + { .reg = 0x3c000000+4*0x40035, .val = 0x80}, + { .reg = 0x3c000000+4*0x40055, .val = 0x0}, + { .reg = 0x3c000000+4*0x40075, .val = 0x0}, + { .reg = 0x3c000000+4*0x40016, .val = 0x60a}, + { .reg = 0x3c000000+4*0x40036, .val = 0x15}, + { .reg = 0x3c000000+4*0x40056, .val = 0x1200}, + { .reg = 0x3c000000+4*0x40076, .val = 0x0}, + { .reg = 0x3c000000+4*0x40017, .val = 0x61a}, + { .reg = 0x3c000000+4*0x40037, .val = 0x15}, + { .reg = 0x3c000000+4*0x40057, .val = 0x1300}, + { .reg = 0x3c000000+4*0x40077, .val = 0x0}, + { .reg = 0x3c000000+4*0x40018, .val = 0x60a}, + { .reg = 0x3c000000+4*0x40038, .val = 0x1a}, + { .reg = 0x3c000000+4*0x40058, .val = 0x1200}, + { .reg = 0x3c000000+4*0x40078, .val = 0x0}, + { .reg = 0x3c000000+4*0x40019, .val = 0x642}, + { .reg = 0x3c000000+4*0x40039, .val = 0x1a}, + { .reg = 0x3c000000+4*0x40059, .val = 0x1300}, + { .reg = 0x3c000000+4*0x40079, .val = 0x0}, + { .reg = 0x3c000000+4*0x4001a, .val = 0x4808}, + { .reg = 0x3c000000+4*0x4003a, .val = 0x880}, + { .reg = 0x3c000000+4*0x4005a, .val = 0x0}, + { .reg = 0x3c000000+4*0x4007a, .val = 0x0}, + { .reg = 0x3c000000+4*0x900a7, .val = 0x0}, + { .reg = 0x3c000000+4*0x900a8, .val = 0x790}, + { .reg = 0x3c000000+4*0x900a9, .val = 0x11a}, + { .reg = 0x3c000000+4*0x900aa, .val = 0x8}, + { .reg = 0x3c000000+4*0x900ab, .val = 0x7aa}, + { .reg = 0x3c000000+4*0x900ac, .val = 0x2a}, + { .reg = 0x3c000000+4*0x900ad, .val = 0x10}, + { .reg = 0x3c000000+4*0x900ae, .val = 0x7b2}, + { .reg = 0x3c000000+4*0x900af, .val = 0x2a}, + { .reg = 0x3c000000+4*0x900b0, .val = 0x0}, + { .reg = 0x3c000000+4*0x900b1, .val = 0x7c8}, + { .reg = 0x3c000000+4*0x900b2, .val = 0x109}, + { .reg = 0x3c000000+4*0x900b3, .val = 0x10}, + { .reg = 0x3c000000+4*0x900b4, .val = 0x2a8}, + { .reg = 0x3c000000+4*0x900b5, .val = 0x129}, + { .reg = 0x3c000000+4*0x900b6, .val = 0x8}, + { .reg = 0x3c000000+4*0x900b7, .val = 0x370}, + { .reg = 0x3c000000+4*0x900b8, .val = 0x129}, + { .reg = 0x3c000000+4*0x900b9, .val = 0xa}, + { .reg = 0x3c000000+4*0x900ba, .val = 0x3c8}, + { .reg = 0x3c000000+4*0x900bb, .val = 0x1a9}, + { .reg = 0x3c000000+4*0x900bc, .val = 0xc}, + { .reg = 0x3c000000+4*0x900bd, .val = 0x408}, + { .reg = 0x3c000000+4*0x900be, .val = 0x199}, + { .reg = 0x3c000000+4*0x900bf, .val = 0x14}, + { .reg = 0x3c000000+4*0x900c0, .val = 0x790}, + { .reg = 0x3c000000+4*0x900c1, .val = 0x11a}, + { .reg = 0x3c000000+4*0x900c2, .val = 0x8}, + { .reg = 0x3c000000+4*0x900c3, .val = 0x4}, + { .reg = 0x3c000000+4*0x900c4, .val = 0x18}, + { .reg = 0x3c000000+4*0x900c5, .val = 0xe}, + { .reg = 0x3c000000+4*0x900c6, .val = 0x408}, + { .reg = 0x3c000000+4*0x900c7, .val = 0x199}, + { .reg = 0x3c000000+4*0x900c8, .val = 0x8}, + { .reg = 0x3c000000+4*0x900c9, .val = 0x8568}, + { .reg = 0x3c000000+4*0x900ca, .val = 0x108}, + { .reg = 0x3c000000+4*0x900cb, .val = 0x18}, + { .reg = 0x3c000000+4*0x900cc, .val = 0x790}, + { .reg = 0x3c000000+4*0x900cd, .val = 0x16a}, + { .reg = 0x3c000000+4*0x900ce, .val = 0x8}, + { .reg = 0x3c000000+4*0x900cf, .val = 0x1d8}, + { .reg = 0x3c000000+4*0x900d0, .val = 0x169}, + { .reg = 0x3c000000+4*0x900d1, .val = 0x10}, + { .reg = 0x3c000000+4*0x900d2, .val = 0x8558}, + { .reg = 0x3c000000+4*0x900d3, .val = 0x168}, + { .reg = 0x3c000000+4*0x900d4, .val = 0x70}, + { .reg = 0x3c000000+4*0x900d5, .val = 0x788}, + { .reg = 0x3c000000+4*0x900d6, .val = 0x16a}, + { .reg = 0x3c000000+4*0x900d7, .val = 0x1ff8}, + { .reg = 0x3c000000+4*0x900d8, .val = 0x85a8}, + { .reg = 0x3c000000+4*0x900d9, .val = 0x1e8}, + { .reg = 0x3c000000+4*0x900da, .val = 0x50}, + { .reg = 0x3c000000+4*0x900db, .val = 0x798}, + { .reg = 0x3c000000+4*0x900dc, .val = 0x16a}, + { .reg = 0x3c000000+4*0x900dd, .val = 0x60}, + { .reg = 0x3c000000+4*0x900de, .val = 0x7a0}, + { .reg = 0x3c000000+4*0x900df, .val = 0x16a}, + { .reg = 0x3c000000+4*0x900e0, .val = 0x8}, + { .reg = 0x3c000000+4*0x900e1, .val = 0x8310}, + { .reg = 0x3c000000+4*0x900e2, .val = 0x168}, + { .reg = 0x3c000000+4*0x900e3, .val = 0x8}, + { .reg = 0x3c000000+4*0x900e4, .val = 0xa310}, + { .reg = 0x3c000000+4*0x900e5, .val = 0x168}, + { .reg = 0x3c000000+4*0x900e6, .val = 0xa}, + { .reg = 0x3c000000+4*0x900e7, .val = 0x408}, + { .reg = 0x3c000000+4*0x900e8, .val = 0x169}, + { .reg = 0x3c000000+4*0x900e9, .val = 0x6e}, + { .reg = 0x3c000000+4*0x900ea, .val = 0x0}, + { .reg = 0x3c000000+4*0x900eb, .val = 0x68}, + { .reg = 0x3c000000+4*0x900ec, .val = 0x0}, + { .reg = 0x3c000000+4*0x900ed, .val = 0x408}, + { .reg = 0x3c000000+4*0x900ee, .val = 0x169}, + { .reg = 0x3c000000+4*0x900ef, .val = 0x0}, + { .reg = 0x3c000000+4*0x900f0, .val = 0x8310}, + { .reg = 0x3c000000+4*0x900f1, .val = 0x168}, + { .reg = 0x3c000000+4*0x900f2, .val = 0x0}, + { .reg = 0x3c000000+4*0x900f3, .val = 0xa310}, + { .reg = 0x3c000000+4*0x900f4, .val = 0x168}, + { .reg = 0x3c000000+4*0x900f5, .val = 0x1ff8}, + { .reg = 0x3c000000+4*0x900f6, .val = 0x85a8}, + { .reg = 0x3c000000+4*0x900f7, .val = 0x1e8}, + { .reg = 0x3c000000+4*0x900f8, .val = 0x68}, + { .reg = 0x3c000000+4*0x900f9, .val = 0x798}, + { .reg = 0x3c000000+4*0x900fa, .val = 0x16a}, + { .reg = 0x3c000000+4*0x900fb, .val = 0x78}, + { .reg = 0x3c000000+4*0x900fc, .val = 0x7a0}, + { .reg = 0x3c000000+4*0x900fd, .val = 0x16a}, + { .reg = 0x3c000000+4*0x900fe, .val = 0x68}, + { .reg = 0x3c000000+4*0x900ff, .val = 0x790}, + { .reg = 0x3c000000+4*0x90100, .val = 0x16a}, + { .reg = 0x3c000000+4*0x90101, .val = 0x8}, + { .reg = 0x3c000000+4*0x90102, .val = 0x8b10}, + { .reg = 0x3c000000+4*0x90103, .val = 0x168}, + { .reg = 0x3c000000+4*0x90104, .val = 0x8}, + { .reg = 0x3c000000+4*0x90105, .val = 0xab10}, + { .reg = 0x3c000000+4*0x90106, .val = 0x168}, + { .reg = 0x3c000000+4*0x90107, .val = 0xa}, + { .reg = 0x3c000000+4*0x90108, .val = 0x408}, + { .reg = 0x3c000000+4*0x90109, .val = 0x169}, + { .reg = 0x3c000000+4*0x9010a, .val = 0x58}, + { .reg = 0x3c000000+4*0x9010b, .val = 0x0}, + { .reg = 0x3c000000+4*0x9010c, .val = 0x68}, + { .reg = 0x3c000000+4*0x9010d, .val = 0x0}, + { .reg = 0x3c000000+4*0x9010e, .val = 0x408}, + { .reg = 0x3c000000+4*0x9010f, .val = 0x169}, + { .reg = 0x3c000000+4*0x90110, .val = 0x0}, + { .reg = 0x3c000000+4*0x90111, .val = 0x8b10}, + { .reg = 0x3c000000+4*0x90112, .val = 0x168}, + { .reg = 0x3c000000+4*0x90113, .val = 0x0}, + { .reg = 0x3c000000+4*0x90114, .val = 0xab10}, + { .reg = 0x3c000000+4*0x90115, .val = 0x168}, + { .reg = 0x3c000000+4*0x90116, .val = 0x0}, + { .reg = 0x3c000000+4*0x90117, .val = 0x1d8}, + { .reg = 0x3c000000+4*0x90118, .val = 0x169}, + { .reg = 0x3c000000+4*0x90119, .val = 0x80}, + { .reg = 0x3c000000+4*0x9011a, .val = 0x790}, + { .reg = 0x3c000000+4*0x9011b, .val = 0x16a}, + { .reg = 0x3c000000+4*0x9011c, .val = 0x18}, + { .reg = 0x3c000000+4*0x9011d, .val = 0x7aa}, + { .reg = 0x3c000000+4*0x9011e, .val = 0x6a}, + { .reg = 0x3c000000+4*0x9011f, .val = 0xa}, + { .reg = 0x3c000000+4*0x90120, .val = 0x0}, + { .reg = 0x3c000000+4*0x90121, .val = 0x1e9}, + { .reg = 0x3c000000+4*0x90122, .val = 0x8}, + { .reg = 0x3c000000+4*0x90123, .val = 0x8080}, + { .reg = 0x3c000000+4*0x90124, .val = 0x108}, + { .reg = 0x3c000000+4*0x90125, .val = 0xf}, + { .reg = 0x3c000000+4*0x90126, .val = 0x408}, + { .reg = 0x3c000000+4*0x90127, .val = 0x169}, + { .reg = 0x3c000000+4*0x90128, .val = 0xc}, + { .reg = 0x3c000000+4*0x90129, .val = 0x0}, + { .reg = 0x3c000000+4*0x9012a, .val = 0x68}, + { .reg = 0x3c000000+4*0x9012b, .val = 0x9}, + { .reg = 0x3c000000+4*0x9012c, .val = 0x0}, + { .reg = 0x3c000000+4*0x9012d, .val = 0x1a9}, + { .reg = 0x3c000000+4*0x9012e, .val = 0x0}, + { .reg = 0x3c000000+4*0x9012f, .val = 0x408}, + { .reg = 0x3c000000+4*0x90130, .val = 0x169}, + { .reg = 0x3c000000+4*0x90131, .val = 0x0}, + { .reg = 0x3c000000+4*0x90132, .val = 0x8080}, + { .reg = 0x3c000000+4*0x90133, .val = 0x108}, + { .reg = 0x3c000000+4*0x90134, .val = 0x8}, + { .reg = 0x3c000000+4*0x90135, .val = 0x7aa}, + { .reg = 0x3c000000+4*0x90136, .val = 0x6a}, + { .reg = 0x3c000000+4*0x90137, .val = 0x0}, + { .reg = 0x3c000000+4*0x90138, .val = 0x8568}, + { .reg = 0x3c000000+4*0x90139, .val = 0x108}, + { .reg = 0x3c000000+4*0x9013a, .val = 0xb7}, + { .reg = 0x3c000000+4*0x9013b, .val = 0x790}, + { .reg = 0x3c000000+4*0x9013c, .val = 0x16a}, + { .reg = 0x3c000000+4*0x9013d, .val = 0x1f}, + { .reg = 0x3c000000+4*0x9013e, .val = 0x0}, + { .reg = 0x3c000000+4*0x9013f, .val = 0x68}, + { .reg = 0x3c000000+4*0x90140, .val = 0x8}, + { .reg = 0x3c000000+4*0x90141, .val = 0x8558}, + { .reg = 0x3c000000+4*0x90142, .val = 0x168}, + { .reg = 0x3c000000+4*0x90143, .val = 0xf}, + { .reg = 0x3c000000+4*0x90144, .val = 0x408}, + { .reg = 0x3c000000+4*0x90145, .val = 0x169}, + { .reg = 0x3c000000+4*0x90146, .val = 0xc}, + { .reg = 0x3c000000+4*0x90147, .val = 0x0}, + { .reg = 0x3c000000+4*0x90148, .val = 0x68}, + { .reg = 0x3c000000+4*0x90149, .val = 0x0}, + { .reg = 0x3c000000+4*0x9014a, .val = 0x408}, + { .reg = 0x3c000000+4*0x9014b, .val = 0x169}, + { .reg = 0x3c000000+4*0x9014c, .val = 0x0}, + { .reg = 0x3c000000+4*0x9014d, .val = 0x8558}, + { .reg = 0x3c000000+4*0x9014e, .val = 0x168}, + { .reg = 0x3c000000+4*0x9014f, .val = 0x8}, + { .reg = 0x3c000000+4*0x90150, .val = 0x3c8}, + { .reg = 0x3c000000+4*0x90151, .val = 0x1a9}, + { .reg = 0x3c000000+4*0x90152, .val = 0x3}, + { .reg = 0x3c000000+4*0x90153, .val = 0x370}, + { .reg = 0x3c000000+4*0x90154, .val = 0x129}, + { .reg = 0x3c000000+4*0x90155, .val = 0x20}, + { .reg = 0x3c000000+4*0x90156, .val = 0x2aa}, + { .reg = 0x3c000000+4*0x90157, .val = 0x9}, + { .reg = 0x3c000000+4*0x90158, .val = 0x0}, + { .reg = 0x3c000000+4*0x90159, .val = 0x400}, + { .reg = 0x3c000000+4*0x9015a, .val = 0x10e}, + { .reg = 0x3c000000+4*0x9015b, .val = 0x8}, + { .reg = 0x3c000000+4*0x9015c, .val = 0xe8}, + { .reg = 0x3c000000+4*0x9015d, .val = 0x109}, + { .reg = 0x3c000000+4*0x9015e, .val = 0x0}, + { .reg = 0x3c000000+4*0x9015f, .val = 0x8140}, + { .reg = 0x3c000000+4*0x90160, .val = 0x10c}, + { .reg = 0x3c000000+4*0x90161, .val = 0x10}, + { .reg = 0x3c000000+4*0x90162, .val = 0x8138}, + { .reg = 0x3c000000+4*0x90163, .val = 0x10c}, + { .reg = 0x3c000000+4*0x90164, .val = 0x8}, + { .reg = 0x3c000000+4*0x90165, .val = 0x7c8}, + { .reg = 0x3c000000+4*0x90166, .val = 0x101}, + { .reg = 0x3c000000+4*0x90167, .val = 0x8}, + { .reg = 0x3c000000+4*0x90168, .val = 0x0}, + { .reg = 0x3c000000+4*0x90169, .val = 0x8}, + { .reg = 0x3c000000+4*0x9016a, .val = 0x8}, + { .reg = 0x3c000000+4*0x9016b, .val = 0x448}, + { .reg = 0x3c000000+4*0x9016c, .val = 0x109}, + { .reg = 0x3c000000+4*0x9016d, .val = 0xf}, + { .reg = 0x3c000000+4*0x9016e, .val = 0x7c0}, + { .reg = 0x3c000000+4*0x9016f, .val = 0x109}, + { .reg = 0x3c000000+4*0x90170, .val = 0x0}, + { .reg = 0x3c000000+4*0x90171, .val = 0xe8}, + { .reg = 0x3c000000+4*0x90172, .val = 0x109}, + { .reg = 0x3c000000+4*0x90173, .val = 0x47}, + { .reg = 0x3c000000+4*0x90174, .val = 0x630}, + { .reg = 0x3c000000+4*0x90175, .val = 0x109}, + { .reg = 0x3c000000+4*0x90176, .val = 0x8}, + { .reg = 0x3c000000+4*0x90177, .val = 0x618}, + { .reg = 0x3c000000+4*0x90178, .val = 0x109}, + { .reg = 0x3c000000+4*0x90179, .val = 0x8}, + { .reg = 0x3c000000+4*0x9017a, .val = 0xe0}, + { .reg = 0x3c000000+4*0x9017b, .val = 0x109}, + { .reg = 0x3c000000+4*0x9017c, .val = 0x0}, + { .reg = 0x3c000000+4*0x9017d, .val = 0x7c8}, + { .reg = 0x3c000000+4*0x9017e, .val = 0x109}, + { .reg = 0x3c000000+4*0x9017f, .val = 0x8}, + { .reg = 0x3c000000+4*0x90180, .val = 0x8140}, + { .reg = 0x3c000000+4*0x90181, .val = 0x10c}, + { .reg = 0x3c000000+4*0x90182, .val = 0x0}, + { .reg = 0x3c000000+4*0x90183, .val = 0x1}, + { .reg = 0x3c000000+4*0x90184, .val = 0x8}, + { .reg = 0x3c000000+4*0x90185, .val = 0x8}, + { .reg = 0x3c000000+4*0x90186, .val = 0x4}, + { .reg = 0x3c000000+4*0x90187, .val = 0x8}, + { .reg = 0x3c000000+4*0x90188, .val = 0x8}, + { .reg = 0x3c000000+4*0x90189, .val = 0x7c8}, + { .reg = 0x3c000000+4*0x9018a, .val = 0x101}, + { .reg = 0x3c000000+4*0x90006, .val = 0x0}, + { .reg = 0x3c000000+4*0x90007, .val = 0x0}, + { .reg = 0x3c000000+4*0x90008, .val = 0x8}, + { .reg = 0x3c000000+4*0x90009, .val = 0x0}, + { .reg = 0x3c000000+4*0x9000a, .val = 0x0}, + { .reg = 0x3c000000+4*0x9000b, .val = 0x0}, + { .reg = 0x3c000000+4*0xd00e7, .val = 0x400}, + { .reg = 0x3c000000+4*0x90017, .val = 0x0}, + { .reg = 0x3c000000+4*0x9001f, .val = 0x2a}, + { .reg = 0x3c000000+4*0x90026, .val = 0x6a}, + { .reg = 0x3c000000+4*0x400d0, .val = 0x0}, + { .reg = 0x3c000000+4*0x400d1, .val = 0x101}, + { .reg = 0x3c000000+4*0x400d2, .val = 0x105}, + { .reg = 0x3c000000+4*0x400d3, .val = 0x107}, + { .reg = 0x3c000000+4*0x400d4, .val = 0x10f}, + { .reg = 0x3c000000+4*0x400d5, .val = 0x202}, + { .reg = 0x3c000000+4*0x400d6, .val = 0x20a}, + { .reg = 0x3c000000+4*0x400d7, .val = 0x20b}, + { .reg = 0x3c000000+4*0x2003a, .val = 0x2}, + { .reg = 0x3c000000+4*0x2000b, .val = 0x5d}, + { .reg = 0x3c000000+4*0x2000c, .val = 0xbb}, + { .reg = 0x3c000000+4*0x2000d, .val = 0x753}, + { .reg = 0x3c000000+4*0x2000e, .val = 0x2c}, + { .reg = 0x3c000000+4*0x9000c, .val = 0x0}, + { .reg = 0x3c000000+4*0x9000d, .val = 0x173}, + { .reg = 0x3c000000+4*0x9000e, .val = 0x60}, + { .reg = 0x3c000000+4*0x9000f, .val = 0x6110}, + { .reg = 0x3c000000+4*0x90010, .val = 0x2152}, + { .reg = 0x3c000000+4*0x90011, .val = 0xdfbd}, + { .reg = 0x3c000000+4*0x90012, .val = 0x60}, + { .reg = 0x3c000000+4*0x90013, .val = 0x6152}, + { .reg = 0x3c000000+4*0x20010, .val = 0x5a}, + { .reg = 0x3c000000+4*0x20011, .val = 0x3}, + { .reg = 0x3c000000+4*0x40080, .val = 0xe0}, + { .reg = 0x3c000000+4*0x40081, .val = 0x12}, + { .reg = 0x3c000000+4*0x40082, .val = 0xe0}, + { .reg = 0x3c000000+4*0x40083, .val = 0x12}, + { .reg = 0x3c000000+4*0x40084, .val = 0xe0}, + { .reg = 0x3c000000+4*0x40085, .val = 0x12}, + { .reg = 0x3c000000+4*0x400fd, .val = 0xf}, + { .reg = 0x3c000000+4*0x10011, .val = 0x1}, + { .reg = 0x3c000000+4*0x10012, .val = 0x1}, + { .reg = 0x3c000000+4*0x10013, .val = 0x180}, + { .reg = 0x3c000000+4*0x10018, .val = 0x1}, + { .reg = 0x3c000000+4*0x10002, .val = 0x6209}, + { .reg = 0x3c000000+4*0x100b2, .val = 0x1}, + { .reg = 0x3c000000+4*0x101b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x102b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x103b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x104b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x105b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x106b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x107b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x108b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x11011, .val = 0x1}, + { .reg = 0x3c000000+4*0x11012, .val = 0x1}, + { .reg = 0x3c000000+4*0x11013, .val = 0x180}, + { .reg = 0x3c000000+4*0x11018, .val = 0x1}, + { .reg = 0x3c000000+4*0x11002, .val = 0x6209}, + { .reg = 0x3c000000+4*0x110b2, .val = 0x1}, + { .reg = 0x3c000000+4*0x111b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x112b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x113b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x114b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x115b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x116b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x117b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x118b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x12011, .val = 0x1}, + { .reg = 0x3c000000+4*0x12012, .val = 0x1}, + { .reg = 0x3c000000+4*0x12013, .val = 0x180}, + { .reg = 0x3c000000+4*0x12018, .val = 0x1}, + { .reg = 0x3c000000+4*0x12002, .val = 0x6209}, + { .reg = 0x3c000000+4*0x120b2, .val = 0x1}, + { .reg = 0x3c000000+4*0x121b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x122b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x123b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x124b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x125b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x126b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x127b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x128b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x13011, .val = 0x1}, + { .reg = 0x3c000000+4*0x13012, .val = 0x1}, + { .reg = 0x3c000000+4*0x13013, .val = 0x180}, + { .reg = 0x3c000000+4*0x13018, .val = 0x1}, + { .reg = 0x3c000000+4*0x13002, .val = 0x6209}, + { .reg = 0x3c000000+4*0x130b2, .val = 0x1}, + { .reg = 0x3c000000+4*0x131b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x132b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x133b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x134b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x135b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x136b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x137b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x138b4, .val = 0x1}, + { .reg = 0x3c000000+4*0x2003a, .val = 0x2}, + { .reg = 0x3c000000+4*0xc0080, .val = 0x2}, + { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x08}, +}; + + + +void lpddr4_750M_cfg_phy(void) +{ + uint32_t index, reg, val, num; + + num = sizeof(phy_init_cfg)/sizeof(struct ddr_phy_param); + + dwc_ddrphy_phyinit_userCustom_overrideUserInput(); + dwc_ddrphy_phyinit_userCustom_A_bringupPower(); + dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(); + + for (index = 0; index < num; index++) { + val = phy_init_cfg[index].val; + reg = phy_init_cfg[index].reg; + writel(val,(void __iomem *)(u64)reg); + if(reg == DDR_PHY_FLAG_ADDR) { + switch(val) { + case 0x00: + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0); + break; + case 0x01: + ddr_load_train_code(FW_1D_IMAGE); + break; + case 0x02: + dwc_ddrphy_phyinit_userCustom_G_waitFwDone(); + break; + case 0x03: + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(0); + break; + case 0x04: + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0); + break; + case 0x05: + ddr_load_train_code(FW_2D_IMAGE); + break; + case 0x06: + dwc_ddrphy_phyinit_userCustom_G_waitFwDone(); + break; + case 0x07: + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(1); + break; + case 0x08: + dwc_ddrphy_phyinit_userCustom_customPostTrain(); + dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(); + break; + default: + break; + } + } + } +} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c b/board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c new file mode 100644 index 0000000..8240736 --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c @@ -0,0 +1,184 @@ +/* +* Copyright 2018 NXP +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include +#include +#include +#include +#include +#include "lpddr4_define.h" +#include "ddr.h" + +void ddr_init(void) +{ + volatile unsigned int tmp; + + /* + * Desc: assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, + * [4]src_system_rst_b! + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); + + /* Desc: deassert [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + + /* + * Desc: change the clock source of dram_apb_clk_root + * to source 4 --800MHz/4 + */ + #if 0 + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); + #else + + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | \ + CLK_ROOT_SOURCE_SEL(0) | \ + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | \ + CLK_ROOT_SOURCE_SEL(0) | \ + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | \ + CLK_ROOT_SOURCE_SEL(0) | \ + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); + clock_set_target_val(NOC_APB_CLK_ROOT, CLK_ROOT_ON | \ + CLK_ROOT_SOURCE_SEL(0) | \ + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); + #endif + + /* Desc: disable iso PGC_CPU_MAPPING,PU_PGC_SW_PUP_REQ */ + reg32_write(0x303A00EC,0x0000ffff); + reg32setbit(0x303A00F8,5); + + /* + * Desc: configure dram pll to 750M + */ + dram_pll_init(DRAM_PLL_OUT_750M); + + + /* + * Desc: release [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Desc: Configure uMCTL2's registers */ + lpddr4_3000mts_cfg_umctl2(); + + /* Desc: diable ctlupd */ + reg32_write(DDRC_DFIUPD0(0), 0xE0300018); + + /* + * Desc: release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, + * [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + + /* + * Desc: release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, + * [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + /* + * Desc: ('b00000000_00000000_00000000_00000000) ('d0) + */ + reg32_write(DDRC_DBG1(0), 0x00000000); + + /* + * Desc: [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR + */ + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + + tmp=0; + while(tmp != 0x223) { + tmp = 0x33f & (reg32_read(DDRC_STAT(0))); + ddr_dbg("C: waiting for STAT selfref_type= Self Refresh\n"); + } + + /* + * Desc: ('b00000000_00000000_00000000_00000000) ('d0) + */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* + * Desc: LPDDR4 mode + */ + reg32_write(DDRC_DDR_SS_GPR0, 0x01); + + /* + * Desc: [12:8]dfi_freq, [5]dfi_init_start, [4]ctl_idle_en + */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + + /* + * Desc: Configure LPDDR4 PHY's registers + */ + lpddr4_750M_cfg_phy(); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x0000); + + /* + * Desc: Set DFIMISC.dfi_init_start to 1 + * [5]--1: dfi_init_start, [4] ctl_idle_en + */ + reg32_write(DDRC_DFIMISC(0), 0x00000030); + reg32_write(DDRC_SWCTL(0), 0x0001); + + /* + * Desc: wait DFISTAT.dfi_init_complete to 1 + */ + while(!(0x1 & (reg32_read(DDRC_DFISTAT(0))))); + + reg32_write(DDRC_SWCTL(0), 0x0000); + + /* + * Desc: clear DFIMISC.dfi_init_complete_en + * ('b00000000_00000000_00000000_00010000) ('d16) + */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + + /* + * Desc: set DFIMISC.dfi_init_complete_en again + * ('b00000000_00000000_00000000_00010001) ('d17) + */ + reg32_write(DDRC_DFIMISC(0), 0x00000011); + + /* + * Desc: ('b00000000_00000000_00000000_10001000) ('d136) + */ + reg32_write(DDRC_PWRCTL(0), 0x00000088); + + /* + * Desc: set SWCTL.sw_done to enable quasi-dynamic + * register programming outside reset. + * ('b00000000_00000000_00000000_00000001) ('d1) + */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* + * Desc: wait SWSTAT.sw_done_ack to 1 + */ + while(!(0x1 & (reg32_read(DDRC_SWSTAT(0))))); + + /* + * Desc: wait STAT.operating_mode([2:0] for lpddr4) to normal state + */ + while(0x1 != (0x7 & (reg32_read(DDRC_STAT(0))))); + + /* + * Desc: ('b00000000_00000000_00000000_10001000) ('d136) + */ + reg32_write(DDRC_PWRCTL(0), 0x00000088); + + + /* + * Desc: enable port 0 + * ('b00000000_00000000_00000000_00000001) ('d1) + */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); +} diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c new file mode 100644 index 0000000..e7486c5 --- /dev/null +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -0,0 +1,263 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_FSPI +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) +static iomux_v3_cfg_t const qspi_pads[] = { + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL | PAD_CTL_PE | PAD_CTL_PUE), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); + + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +#define SPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) +static iomux_v3_cfg_t const ecspi1_pads[] = { + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const ecspi2_pads[] = { + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS"); + gpio_request(IMX_GPIO_NR(5, 13), "ECSPI2 CS"); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + if (bus == 0) + return IMX_GPIO_NR(5, 9); + else + return IMX_GPIO_NR(5, 13); +} +#endif + +#ifdef CONFIG_NAND_MXS +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + mxs_dma_init(); +} +#endif + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(FEC_RST_PAD, "fec1_rst"); + gpio_direction_output(FEC_RST_PAD, 0); + udelay(500); + gpio_direction_output(FEC_RST_PAD, 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_FSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno + 1; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + return 0; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + +#if 0 + /* unlock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x1); + + /* Set BUCK5 output for DRAM to 1.0V */ + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3); + + /* lock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x11); +#endif + return 0; +} +#endif diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c new file mode 100644 index 0000000..d2848e8 --- /dev/null +++ b/board/freescale/imx8mm_evk/spl.c @@ -0,0 +1,163 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include +#include +#include +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr train */ + ddr_init(); +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 1}, + {USDHC3_BASE_ADDR, 0, 1}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC3_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +void spl_board_init(void) +{ + /* TODO */ + /* enable_tzc380(); */ + + /* DDR initialization */ + spl_dram_init(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig new file mode 100644 index 0000000..a3fdfe0 --- /dev/null +++ b/configs/imx8mm_evk_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_OF_LIBFDT=y +CONFIG_FS_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_CMD_PMIC=y +CONFIG_NXP_TMU=n +CONFIG_DM_THERMAL=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=-1 +CONFIG_CMD_SF=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h new file mode 100644 index 0000000..07b2e95 --- /dev/null +++ b/include/configs/imx8mm_evk.h @@ -0,0 +1,281 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8MM_EVK_H +#define __IMX8MM_EVK_H + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00182000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_BOARD_LATE_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8mm-evk.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_32M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x30bb0000 +#define FSPI0_AMBA_BASE 0x0 +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_FSPI_QUAD_SUPPORT + +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* Enable SPI */ +#ifndef CONFIG_NAND_MXS +#ifndef CONFIG_FSL_FSPI +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif +#endif +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif -- 1.9.1